NVMFS5H610NLWFT1G [ONSEMI]
Power MOSFET 60 V, 10 mΩ, 48 A, Single N−Channel;
| 型号： | NVMFS5H610NLWFT1G |
| 厂家： | 
ONSEMI |
| 描述： | Power MOSFET 60 V, 10 mΩ, 48 A, Single N−Channel 脉冲 光电二极管 晶体管 |
| 文件： | 总7页 (文件大小：206K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
NVMFS5H610NL,
NVMFS5H610NLWF
Power MOSFET
60 V, 10 mW, 48 A, Single N−Channel
NVMFS5H610NLWF − Wettable Flank
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Option for Enhanced Optical Inspection
Features
• Small Footprint (5x6 mm) for Compact Design
V
R
MAX
I MAX
D
(BR)DSS
DS(ON)
• Low R
to Minimize Conduction Losses
DS(on)
10 mW @ 10 V
13 mW @ 4.5 V
• Low Q and Capacitance to Minimize Driver Losses
G
60 V
48 A
• AEC−Q101 Qualified and PPAP Capable
• These Devices are Pb−Free and are RoHS Compliant
D (5)
MAXIMUM RATINGS (T = 25°C unless otherwise noted)
J
Parameter
Drain−to−Source Voltage
Symbol
Value
60
Unit
V
V
DSS
Gate−to−Source Voltage
V
GS
20
V
G (4)
Continuous Drain
Current R
T
= 25°C
= 100°C
= 25°C
I
48
A
C
D
q
JC
S (1,2,3)
N−CHANNEL MOSFET
T
C
34
(Notes 1, 3)
Steady
State
Power Dissipation
T
C
P
52
W
A
D
R
(Note 1)
q
JC
T
C
= 100°C
26
MARKING
DIAGRAM
Continuous Drain
Current R
T = 25°C
A
I
D
13
q
JA
T = 100°C
A
9
(Notes 1, 2, 3)
Steady
State
D
1
Power Dissipation
T = 25°C
A
P
3.6
1.8
243
W
D
S
S
S
G
D
D
R
(Notes 1, 2)
q
JA
DFN5
(SO−8FL)
CASE 488AA
STYLE 1
XXXXXX
AYWZZ
T = 100°C
A
Pulsed Drain Current
T = 25°C, t = 10 ms
I
DM
A
A
p
D
Operating Junction and Storage Temperature
Range
T , T
−55 to
+175
°C
J
stg
XXXXXX = 5H610L (NVMFS5H610NL) or
= 610LWF (NVMFS5H610NLWF)
Source Current (Body Diode)
I
43
A
S
A
Y
W
ZZ
= Assembly Location
= Year
= Work Week
= Lot Traceability
Single Pulse Drain−to−Source Avalanche
E
AS
175
mJ
Energy (I
= 2.8 A)
L(pk)
Lead Temperature for Soldering Purposes
(1/8″ from case for 10 s)
T
260
°C
L
Stresses exceeding those listed in the Maximum Ratings table may damage the
device. If any of these limits are exceeded, device functionality should not be
assumed, damage may occur and reliability may be affected.
ORDERING INFORMATION
See detailed ordering, marking and shipping information in the
package dimensions section on page 5 of this data sheet.
THERMAL RESISTANCE MAXIMUM RATINGS
Parameter
Symbol
Value
2.9
Unit
Junction−to−Case − Steady State
Junction−to−Ambient − Steady State (Note 2)
R
°C/W
q
JC
R
42
q
JA
1. The entire application environment impacts the thermal resistance values shown,
they are not constants and are only valid for the particular conditions noted.
2
2. Surface−mounted on FR4 board using a 650 mm , 2 oz. Cu pad.
3. Maximum current for pulses as long as 1 second is higher but is dependent
on pulse duration and duty cycle.
© Semiconductor Components Industries, LLC, 2018
1
Publication Order Number:
October, 2018 − Rev. 0
NVMFS5H610NL/D
NVMFS5H610NL, NVMFS5H610NLWF
ELECTRICAL CHARACTERISTICS (T = 25°C unless otherwise specified)
J
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
OFF CHARACTERISTICS
Drain−to−Source Breakdown Voltage
V
V
GS
= 0 V, I = 250 mA
60
V
(BR)DSS
D
Drain−to−Source Breakdown Voltage
Temperature Coefficient
V
/
39.2
(BR)DSS
mV/°C
T
J
Zero Gate Voltage Drain Current
I
V
= 0 V,
T = 25 °C
10
DSS
GS
DS
J
V
= 60 V
mA
T = 125°C
J
250
100
Gate−to−Source Leakage Current
ON CHARACTERISTICS (Note 4)
Gate Threshold Voltage
I
V
= 0 V, V = 20 V
nA
GSS
DS
GS
V
V
= V , I = 40 mA
1.2
2.0
V
GS(TH)
GS
DS
D
Threshold Temperature Coefficient
Drain−to−Source On Resistance
V
/T
−5.0
8.0
mV/°C
GS(TH)
J
R
V
= 10 V
I
I
= 8 A
= 7 A
10
13
DS(on)
GS
D
mW
V
GS
= 4.5 V
10.5
D
CHARGES, CAPACITANCES & GATE RESISTANCE
Input Capacitance
C
880
150
6.0
12
ISS
Output Capacitance
C
OSS
C
RSS
Q
OSS
V
GS
= 0 V, f = 1 MHz, V = 30 V
pF
DS
Reverse Transfer Capacitance
Output Charge
V
GS
= 0 V, V = 30 V
DD
Total Gate Charge
Q
Q
V
= 10 V, V = 30 V; I = 8 A
13.7
6.4
1.6
2.6
1.3
2.6
G(TOT)
G(TOT)
GS
GS
DS
D
Total Gate Charge
nC
V
Threshold Gate Charge
Gate−to−Source Charge
Gate−to−Drain Charge
Plateau Voltage
Q
G(TH)
Q
V
=4.5 V, V = 30 V; I = 8 A
GS
GD
GP
DS
D
Q
V
SWITCHING CHARACTERISTICS (Note 5)
Turn−On Delay Time
Rise Time
t
9.5
23
22
6
d(ON)
t
r
V
= 4.5 V, V = 48 V,
DS
GS
D
ns
V
I
= 8 A, R = 2.5 W
G
Turn−Off Delay Time
Fall Time
t
d(OFF)
t
f
DRAIN−SOURCE DIODE CHARACTERISTICS
Forward Diode Voltage
V
T = 25°C
0.8
0.65
24
1.2
SD
RR
J
V
GS
I
= 0 V,
= 8 A
S
T = 125°C
J
Reverse Recovery Time
Charge Time
t
t
a
15
ns
V
= 0 V, dI /dt = 100 A/ms,
S
GS
I
S
= 4 A
Discharge Time
t
b
9
Reverse Recovery Charge
Q
17
nC
RR
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
4. Pulse Test: pulse width v 300 ms, duty cycle v 2%.
5. Switching characteristics are independent of operating junction temperatures.
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2
NVMFS5H610NL, NVMFS5H610NLWF
TYPICAL CHARACTERISTICS
50
45
40
35
30
25
20
15
10
50
10 V
4.5 V
3.6 V
3.2 V
40
30
20
3.0 V
2.8 V
T = 25°C
J
10
0
5
0
T = 125°C
J
T = −55°C
J
0
0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0
, DRAIN−TO−SOURCE VOLTAGE (V)
0
1
2
3
4
5
V
DS
V
, GATE−TO−SOURCE VOLTAGE (V)
GS
Figure 1. On−Region Characteristics
Figure 2. Transfer Characteristics
40
35
30
25
20
15
10
16
14
12
10
T = 25°C
J
T = 25°C
D
J
I
= 8 A
V
= 4.5 V
= 10 V
GS
V
GS
8
6
4
5
0
2
3
4
5
6
7
8
9
10
20
25
30
35
40
45
50
V
GS
, GATE−TO−SOURCE VOLTAGE (V)
I , DRAIN CURRENT (A)
D
Figure 3. On−Resistance vs. Gate−to−Source
Figure 4. On−Resistance vs. Drain Current and
Voltage
Gate Voltage
2.5
2.0
1.5
100K
10K
1K
V
= 10 V
= 8 A
GS
I
D
T = 150°C
J
T = 125°C
J
T = 85°C
J
100
1.0
0.5
10
1
−50 −25
0
25
50
75 100 125 150 175
5
15
25
35
45
55
T , JUNCTION TEMPERATURE (°C)
J
V
, DRAIN−TO−SOURCE VOLTAGE (V)
DS
Figure 5. On−Resistance Variation with
Figure 6. Drain−to−Source Leakage Current
Temperature
vs. Voltage
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3
NVMFS5H610NL, NVMFS5H610NLWF
TYPICAL CHARACTERISTICS
10K
1K
10
9
8
7
6
5
4
C
ISS
C
OSS
RSS
100
Q
GD
Q
GS
3
2
1
0
10
1
V
DS
= 30 V
C
V
= 0 V
GS
T = 25°C
J
T = 25°C
J
I
D
= 8 A
f = 1 MHz
0
10
20
30
40
50
60
0
2
4
6
8
10
12
14
V
DS
, DRAIN−TO−SOURCE VOLTAGE (V)
Q , TOTAL GATE CHARGE (nC)
G
Figure 7. Capacitance Variation
Figure 8. Gate−to−Source Voltage vs. Total
Charge
100
10
V
GS
= 0 V
t
r
t
t
d(off)
10
1
d(on)
t
f
T = 125°C
J
T = 25°C
J
T = −55°C
J
V
= 4.5 V
= 48 V
GS
V
DS
I
D
= 8 A
1
0.1
1
10
R , GATE RESISTANCE (W)
100
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1.0
V
SD
, SOURCE−TO−DRAIN VOLTAGE (V)
G
Figure 9. Resistive Switching Time Variation
vs. Gate Resistance
Figure 10. Diode Forward Voltage vs. Current
100
10
1000
100
10
T
= 25°C
C
Single Pulse
≤ 10 V
T
= 25°C
V
J(initial)
GS
10 ms
1
T
= 100°C
J(initial)
1
R
Limit
DS(on)
0.5 ms
1 ms
Thermal Limit
Package Limit
10 ms
0.1
0.1
0.1
1
10
100
1000
0.00001
0.0001
0.001
0.01
V
DS
, DRAIN−TO−SOURCE VOLTAGE (V)
TIME IN AVALANCHE (s)
Figure 11. Maximum Rated Forward Biased
Safe Operating Area
Figure 12. IPEAK vs. Time in Avalanche
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4
NVMFS5H610NL, NVMFS5H610NLWF
TYPICAL CHARACTERISTICS
100
10
1
Duty Cycle = 0.5
0.2
0.1
0.05
0.02
0.01
0.1
Single Pulse
0.01
0.000001 0.00001
0.0001
0.001
0.01
0.1
1
10
100
1000
PULSE TIME (sec)
Figure 13. Thermal Characteristics
DEVICE ORDERING INFORMATION
Device
†
Marking
Package
Shipping
NVMFS5H610NLT1G
5H610L
DFN5
1500 / Tape & Reel
1500 / Tape & Reel
(Pb−Free)
NVMFS5H610NLWFT1G
610LWF
DFN5
(Pb−Free, Wettable Flanks)
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
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5
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
DFN5 5x6, 1.27P
(SO−8FL)
CASE 488AA
ISSUE N
1
SCALE 2:1
2 X
DATE 25 JUN 2018
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ASME Y14.5M, 1994.
0.20
C
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION D1 AND E1 DO NOT INCLUDE
MOLD FLASH PROTRUSIONS OR GATE
BURRS.
D
A
2
B
E
2 X
D1
MILLIMETERS
0.20
C
DIM
A
A1
b
c
D
D1
D2
E
E1
E2
e
G
K
L
L1
M
MIN
0.90
0.00
0.33
0.23
5.00
4.70
3.80
6.00
5.70
3.45
NOM
1.00
−−−
0.41
0.28
5.15
4.90
4.00
6.15
MAX
1.10
0.05
0.51
0.33
5.30
5.10
4.20
6.30
6.10
3.85
4 X
q
E1
2
c
A1
5.90
3.65
1
2
3
4
1.27 BSC
0.575
1.35
0.575
0.125 REF
3.40
0.51
1.20
0.51
0.71
1.50
0.71
TOP VIEW
C
SEATING
DETAIL A
PLANE
0.10
0.10
C
C
3.00
0
3.80
q
−−−
12
A
_
_
GENERIC
SIDE VIEW
MARKING DIAGRAM*
DETAIL A
1
8X b
A B
XXXXXX
AYWZZ
0.10
0.05
C
c
e/2
e
L
1
4
XXXXXX = Specific Device Code
A
Y
= Assembly Location
= Year
K
RECOMMENDED
SOLDERING FOOTPRINT*
W
ZZ
= Work Week
= Lot Traceability
E2
2X
PIN 5
M
*This information is generic. Please refer to
device data sheet for actual part marking.
Pb−Free indicator, “G” or microdot “ G”,
may or may not be present. Some products
may not follow the Generic Marking.
(EXPOSED PAD)
L1
0.495
4.560
2X
1.530
D2
G
2X
BOTTOM VIEW
0.475
3.200
1.330
4.530
STYLE 1:
STYLE 2:
PIN 1. ANODE
2. ANODE
2X
0.905
PIN 1. SOURCE
2. SOURCE
3. SOURCE
4. GATE
1
3. ANODE
4. NO CONNECT
5. CATHODE
0.965
5. DRAIN
4X
1.000
1.270
PITCH
DIMENSIONS: MILLIMETERS
4X
0.750
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
DOCUMENT NUMBER:
DESCRIPTION:
98AON14036D
DFN5 5x6, 1.27P (SO−8FL)
PAGE 1 OF 1
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