NVMFS6H836N [ONSEMI]
MOSFET - Power, Single N-Channel;
| 型号： | NVMFS6H836N |
| 厂家： | 
ONSEMI |
| 描述： | MOSFET - Power, Single N-Channel |
| 文件： | 总7页 (文件大小：187K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
MOSFET - Power, Single
N-Channel
80 V, 6.7 mW, 80 A
NVMFS6H836N
Features
www.onsemi.com
• Small Footprint (5x6 mm) for Compact Design
• Low R
to Minimize Conduction Losses
DS(on)
• Low Q and Capacitance to Minimize Driver Losses
G
V
R
MAX
I MAX
D
(BR)DSS
DS(ON)
• NVMFS6H836NWF − Wettable Flank Option for Enhanced Optical
Inspection
80 V
6.7 mW @ 10 V
80 A
• AEC−Q101 Qualified and PPAP Capable
• These Devices are Pb−Free and are RoHS Compliant
D (5,6)
MAXIMUM RATINGS (T = 25°C unless otherwise noted)
J
Parameter
Drain−to−Source Voltage
Symbol
Value
80
Unit
V
V
DSS
G (4)
Gate−to−Source Voltage
V
GS
20
V
Continuous Drain
Current R
T
= 25°C
= 100°C
= 25°C
I
74
A
C
D
S (1,2,3)
N−CHANNEL MOSFET
q
JC
T
C
53
(Notes 1, 3)
Steady
State
Power Dissipation
T
C
P
89
W
A
D
R
(Note 1)
q
JC
T
C
= 100°C
44
MARKING
DIAGRAM
Continuous Drain
Current R
T = 25°C
A
I
D
15
q
JA
T = 100°C
A
11
(Notes 1, 2, 3)
D
Steady
State
1
S
S
S
G
D
D
Power Dissipation
T = 25°C
A
P
3.7
1.8
432
W
D
DFN5
(SO−8FL)
CASE 488AA
STYLE 1
XXXXXX
AYWZZ
R
(Notes 1, 2)
q
JA
T = 100°C
A
Pulsed Drain Current
T = 25°C, t = 10 ms
I
DM
A
A
p
D
Operating Junction and Storage Temperature
Range
T , T
−55 to
+175
°C
J
stg
XXXXXX = 6H836N
XXXXXX = (NVMFS6H836N) or
XXXXXX = 836NWF
Source Current (Body Diode)
I
S
74
A
XXXXXX = (NVMFS6H836NWF)
Single Pulse Drain−to−Source Avalanche
E
521
mJ
AS
Energy (I
= 4.6 A)
A
Y
= Assembly Location
= Year
L(pk)
Lead Temperature for Soldering Purposes
(1/8″ from case for 10 s)
T
260
°C
L
W
ZZ
= Work Week
= Lot Traceability
Stresses exceeding those listed in the Maximum Ratings table may damage the
device. If any of these limits are exceeded, device functionality should not be
assumed, damage may occur and reliability may be affected.
ORDERING INFORMATION
See detailed ordering, marking and shipping information in the
package dimensions section on page 5 of this data sheet.
THERMAL RESISTANCE MAXIMUM RATINGS
Parameter
Symbol
Value
1.7
Unit
Junction−to−Case − Steady State
Junction−to−Ambient − Steady State (Note 2)
R
°C/W
q
JC
R
40.6
q
JA
1. The entire application environment impacts the thermal resistance values shown,
they are not constants and are only valid for the particular conditions noted.
2
2. Surface−mounted on FR4 board using a 650 mm , 2 oz. Cu pad.
3. Maximum current for pulses as long as 1 second is higher but is dependent
on pulse duration and duty cycle.
© Semiconductor Components Industries, LLC, 2017
1
Publication Order Number:
August, 2020 − Rev. 3
NVMFS6H836N/D
NVMFS6H836N
ELECTRICAL CHARACTERISTICS (T = 25°C unless otherwise specified)
J
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
OFF CHARACTERISTICS
Drain−to−Source Breakdown Voltage
V
V
GS
= 0 V, I = 250 mA
80
V
(BR)DSS
D
Drain−to−Source Breakdown Voltage
Temperature Coefficient
V
/
39
(BR)DSS
mV/°C
T
J
Zero Gate Voltage Drain Current
I
V
= 0 V,
T = 25°C
10
DSS
GS
DS
J
V
= 80 V
mA
T = 125°C
J
100
100
Gate−to−Source Leakage Current
ON CHARACTERISTICS (Note 4)
Gate Threshold Voltage
I
V
= 0 V, V = 20 V
nA
GSS
DS
GS
V
V
= V , I = 95 mA
2.0
4.0
6.7
V
mV/°C
mW
S
GS(TH)
GS
DS
D
Threshold Temperature Coefficient
Drain−to−Source On Resistance
Forward Transconductance
V
/T
J
−7.3
5.6
97
GS(TH)
R
V
GS
= 10 V
I = 15 A
D
DS(on)
g
FS
V
=15 V, I = 25 A
DS D
CHARGES, CAPACITANCES & GATE RESISTANCE
Input Capacitance
C
1640
230
8.0
25
ISS
Output Capacitance
C
OSS
C
RSS
V
= 0 V, f = 1 MHz, V = 40 V
pF
GS
DS
Reverse Transfer Capacitance
Total Gate Charge
Q
V
GS
= 10 V, V = 40 V; I = 25 A
DS D
G(TOT)
Threshold Gate Charge
Gate−to−Source Charge
Gate−to−Drain Charge
Plateau Voltage
Q
5.2
8.5
4.3
4.9
G(TH)
nC
V
Q
GS
GD
GP
V
GS
= 10 V, V = 40 V; I = 25 A
DS
D
Q
V
SWITCHING CHARACTERISTICS (Note 5)
Turn−On Delay Time
t
16
45
41
34
d(ON)
Rise Time
t
r
V
= 10 V, V = 64 V,
DS
GS
D
ns
V
I
= 25 A, R = 2.5 W
G
Turn−Off Delay Time
t
d(OFF)
Fall Time
t
f
DRAIN−SOURCE DIODE CHARACTERISTICS
Forward Diode Voltage
V
T = 25°C
0.8
0.7
43
29
15
54
1.2
SD
J
V
S
= 0 V,
GS
I
= 15 A
T = 125°C
J
Reverse Recovery Time
Charge Time
t
RR
t
ns
a
V
= 0 V, dIS/dt = 100 A/ms,
GS
I
S
= 25 A
Discharge Time
t
b
Reverse Recovery Charge
Q
nC
RR
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
4. Pulse Test: pulse width v 300 ms, duty cycle v 2%.
5. Switching characteristics are independent of operating junction temperatures.
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2
NVMFS6H836N
TYPICAL CHARACTERISTICS
300
250
300
250
200
150
100
V
GS
= 10 V
T = 25°C
J
200
6 V
150
100
5 V
50
0
50
T = 125°C
J
4 V
T = −55°C
J
0
0
1
2
3
4
5
6
7
8
0
1
2
3
4
5
6
7
8
9
10
V
DS
, DRAIN−TO−SOURCE VOLTAGE (V)
V
GS
, GATE−TO−SOURCE VOLTAGE (V)
Figure 1. On−Region Characteristics
Figure 2. Transfer Characteristics
12
10
8
12
10
8
T = 25°C
D
J
T = 25°C
J
I
= 15 A
6
4
6
4
V
= 10 V
GS
5
6
7
8
9
10
5
6
7
8
9
10
11 12 13 14 15
V
GS
, GATE−TO−SOURCE VOLTAGE (V)
I , DRAIN CURRENT (A)
D
Figure 3. On−Resistance vs. Gate−to−Source
Figure 4. On−Resistance vs. Drain Current and
Voltage
Gate Voltage
1M
100K
10K
1K
V
= 10 V
= 15 A
GS
2.5
I
D
T = 175°C
J
T = 150°C
2.0
1.5
1.0
J
T = 125°C
J
T = 85°C
J
100
T = 25°C
J
0.5
0
10
1
−50 −25
0
25
50
75 100 125 150 175
5
15
V
25
35
45
55
65
75
T , JUNCTION TEMPERATURE (°C)
, DRAIN−TO−SOURCE VOLTAGE (V)
DS
J
Figure 5. On−Resistance Variation with
Figure 6. Drain−to−Source Leakage Current
Temperature
vs. Voltage
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3
NVMFS6H836N
TYPICAL CHARACTERISTICS
10,000
1000
100
10
9
C
C
ISS
8
7
Q
Q
GD
6
5
4
3
OSS
GS
C
10
1
RSS
V
= 0 V
V
DS
= 40 V
GS
2
T = 25°C
T = 25°C
J
J
1
0
f = 1 MHz
I
D
= 25 A
0
10
20
30
40
50
60
70
80
0
5
10
15
20
25
V
DS
, DRAIN−TO−SOURCE VOLTAGE (V)
Q , TOTAL GATE CHARGE (nC)
G
Figure 7. Capacitance Variation
Figure 8. Gate−to−Source Voltage vs. Total
Charge
100
10
1000
100
V
GS
= 0 V
t
t
d(off)
f
t
r
t
d(on)
1
10
1
V
V
= 10 V
= 64 V
= 25 A
GS
DS
I
D
T = 125°C T = 25°C T = −55°C
J
J
J
0.1
1
10
R , GATE RESISTANCE (W)
100
0.3
0.4
0.5
, SOURCE−TO−DRAIN VOLTAGE (V)
SD
0.6
0.7
0.8
0.9
1.0
V
G
Figure 9. Resistive Switching Time Variation
vs. Gate Resistance
Figure 10. Diode Forward Voltage vs. Current
100
1000
100
10
T
= 25°C
C
Single Pulse
≤ 10 V
V
0.5 ms
1 ms
GS
10 ms
T
= 25°C
J(initial)
10 ms
10
T
= 100°C
1E−04
J(initial)
1
R
Limit
DS(on)
Thermal Limit
Package Limit
0.1
1
0.1
1
10
100
1000
1E−05
1E−03
1E−02
V
DS
, DRAIN−TO−SOURCE VOLTAGE (V)
TIME IN AVALANCHE (s)
Figure 11. Maximum Rated Forward Biased
Safe Operating Area
Figure 12. IPEAK vs. Time in Avalanche
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4
NVMFS6H836N
TYPICAL CHARACTERISTICS
100
10
1
Duty Cycle = 0.5
0.2
0.1
0.05
0.02
0.01
0.1
Single Pulse
0.01
0.000001 0.00001
0.0001
0.001
0.01
0.1
1
10
100
1000
PULSE TIME (sec)
Figure 13. Thermal Characteristics
DEVICE ORDERING INFORMATION
Device
†
Marking
Package
Shipping
NVMFS6H836NT1G
6H836N
DFN5
1500 / Tape & Reel
5000 / Tape & Reel
1500 / Tape & Reel
5000 / Tape & Reel
(Pb−Free)
NVMFS6H836NT3G
6H836N
836NWF
836NWF
DFN5
(Pb−Free)
NVMFS6H836NWFT1G
NVMFS6H836NWFT3G
DFN5
(Pb−Free, Wettable Flanks)
DFN5
(Pb−Free, Wettable Flanks)
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
www.onsemi.com
5
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
DFN5 5x6, 1.27P
(SO−8FL)
CASE 488AA
ISSUE N
1
SCALE 2:1
2 X
DATE 25 JUN 2018
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ASME Y14.5M, 1994.
0.20
C
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION D1 AND E1 DO NOT INCLUDE
MOLD FLASH PROTRUSIONS OR GATE
BURRS.
D
A
2
B
E
2 X
D1
MILLIMETERS
0.20
C
DIM
A
A1
b
c
D
D1
D2
E
E1
E2
e
G
K
L
L1
M
MIN
0.90
0.00
0.33
0.23
5.00
4.70
3.80
6.00
5.70
3.45
NOM
1.00
−−−
0.41
0.28
5.15
4.90
4.00
6.15
MAX
1.10
0.05
0.51
0.33
5.30
5.10
4.20
6.30
6.10
3.85
4 X
q
E1
2
c
A1
5.90
3.65
1
2
3
4
1.27 BSC
0.575
1.35
0.575
0.125 REF
3.40
0.51
1.20
0.51
0.71
1.50
0.71
TOP VIEW
C
SEATING
DETAIL A
PLANE
0.10
0.10
C
C
3.00
0
3.80
q
−−−
12
A
_
_
GENERIC
SIDE VIEW
MARKING DIAGRAM*
DETAIL A
1
8X b
A B
XXXXXX
AYWZZ
0.10
0.05
C
c
e/2
e
L
1
4
XXXXXX = Specific Device Code
A
Y
= Assembly Location
= Year
K
RECOMMENDED
SOLDERING FOOTPRINT*
W
ZZ
= Work Week
= Lot Traceability
E2
2X
PIN 5
M
*This information is generic. Please refer to
device data sheet for actual part marking.
Pb−Free indicator, “G” or microdot “ G”,
may or may not be present. Some products
may not follow the Generic Marking.
(EXPOSED PAD)
L1
0.495
4.560
2X
1.530
D2
G
2X
BOTTOM VIEW
0.475
3.200
1.330
4.530
STYLE 1:
STYLE 2:
PIN 1. ANODE
2. ANODE
2X
0.905
PIN 1. SOURCE
2. SOURCE
3. SOURCE
4. GATE
1
3. ANODE
4. NO CONNECT
5. CATHODE
0.965
5. DRAIN
4X
1.000
1.270
PITCH
4X
0.750
DIMENSIONS: MILLIMETERS
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
DOCUMENT NUMBER:
DESCRIPTION:
98AON14036D
DFN5 5x6, 1.27P (SO−8FL)
PAGE 1 OF 1
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