NVTFS5124PLTWG [ONSEMI]
单 P 沟道功率 MOSFET -60V，-8A，260mΩ;
| 型号： | NVTFS5124PLTWG |
| 厂家： | 
ONSEMI |
| 描述： | 单 P 沟道功率 MOSFET -60V，-8A，260mΩ 脉冲 光电二极管 晶体管 |
| 文件： | 总7页 (文件大小：217K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
NVTFS5124PL
MOSFET – Power, Single
P-Channel
-60 V, -6 A, 260 mW
Features
• Small Footprint (3.3 x 3.3 mm) for Compact Design
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• Low R
to Minimize Conduction Losses
DS(on)
• Low Q and Capacitance to Minimize Driver Losses
G
V
R
MAX
I MAX
D
(BR)DSS
DS(on)
• NVTFS5124PLWF − Wettable Flanks Product
• AEC−Q101 Qualified and PPAP Capable
260 mW @ −10 V
380 mW @ −4.5 V
−60 V
−6 A
• These Devices are Pb−Free and are RoHS Compliant
MAXIMUM RATINGS (T = 25°C unless otherwise noted)
J
P−Channel MOSFET
D (5−8)
Parameter
Drain−to−Source Voltage
Symbol
Value
−60
20
Unit
V
V
DSS
Gate−to−Source Voltage
V
GS
V
Continuous Drain Cur-
T
= 25°C
= 100°C
= 25°C
I
−6.0
−4.0
18
A
mb
D
rent R
(Notes 1,
Y
J−mb
G (4)
T
mb
2, 3, 4)
Steady
State
Power Dissipation
T
mb
P
W
A
D
S (1,2,3)
R
(Notes 1, 2, 3)
Y
J−mb
T
mb
= 100°C
9.0
MARKING DIAGRAM
Continuous Drain Cur-
T = 25°C
I
D
−2.4
−1.7
3.0
A
rent R
4)
(Notes 1, 3,
q
JA
1
T = 100°C
A
Steady
State
1
S
S
S
G
D
D
D
D
XXXX
AYWWG
G
Power Dissipation
(Notes 1, 3)
T = 25°C
P
W
WDFN8
(m8FL)
CASE 511AB
A
D
R
q
JA
T = 100°C
A
1.5
Pulsed Drain Current
T = 25°C, t = 10 ms
I
DM
−24
A
A
p
Operating Junction and Storage Temperature
T , T
−55 to
°C
XXXX = Specific Device Code
J
stg
+175
A
Y
= Assembly Location
= Year
Source Current (Body Diode)
I
S
−18
A
WW
G
= Work Week
= Pb−Free Package
Single Pulse Drain−to−Source Avalanche
E
AS
8.5
mJ
Energy (T = 25°C, V = −50 V, V = −10 V,
J
DD
GS
(Note: Microdot may be in either location)
I
= −13 A, L = 0.1 mH, R = 25 W)
L(pk)
G
Lead Temperature for Soldering Purposes
(1/8″ from case for 10 s)
T
L
260
°C
ORDERING INFORMATION
See detailed ordering, marking and shipping information in the
package dimensions section on page 5 of this data sheet.
Stresses exceeding Maximum Ratings may damage the device. Maximum
Ratings are stress ratings only. Functional operation above the Recommended
Operating Conditions is not implied. Extended exposure to stresses above the
Recommended Operating Conditions may affect device reliability.
THERMAL RESISTANCE MAXIMUM RATINGS (Note 1)
Parameter
Symbol
Value
Unit
Junction−to−Mounting Board (top) − Steady
State (Note 2 and 3)
R
8.4
°C/W
Y
J−mb
Junction−to−Ambient − Steady State (Note 3)
R
49.2
q
JA
1. The entire application environment impacts the thermal resistance values shown,
they are not constants and are only valid for the particular conditions noted.
2. Psi (Y) is used as required per JESD51−12 for packages in which
substantially less than 100% of the heat flows to single case surface.
2
3. Surface−mounted on FR4 board using a 650 mm , 2 oz. Cu pad.
4. Continuous DC current rating. Maximum current for pulses as long as 1
second is higher but is dependent on pulse duration and duty cycle.
© Semiconductor Components Industries, LLC, 2013
1
Publication Order Number:
August, 2019 − Rev. 2
NVTFS5124PL/D
NVTFS5124PL
ELECTRICAL CHARACTERISTICS (T = 25°C unless otherwise noted)
J
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
OFF CHARACTERISTICS
Drain−to−Source Breakdown Voltage
Zero Gate Voltage Drain Current
V
V
= 0 V, I = −250 mA
−60
V
(BR)DSS
GS
D
I
T = 25°C
J
−1.0
−10
mA
DSS
V
GS
= 0 V,
= −60 V
V
DS
T = 125°C
J
Gate−to−Source Leakage Current
ON CHARACTERISTICS (Note 5)
Gate Threshold Voltage
I
V
= 0 V, V = "20 V
"100
nA
GSS
DS
GS
V
V
GS
= V , I = −250 mA
−1.5
−2.5
260
380
V
GS(TH)
DS
D
Drain−to−Source On Resistance
R
V
= −10 V, I = −3 A
200
290
mW
DS(on)
GS
GS
D
V
= −4.5 V, I = −3 A
D
Forward Transconductance
CHARGES AND CAPACITANCES
Input Capacitance
g
V
= −15 V, I = −5 A
4
S
FS
DS
D
C
250
27
iss
V
GS
= 0 V, f = 1.0 MHz,
Output Capacitance
C
oss
pF
V
DS
= −25 V
Reverse Transfer Capacitance
Total Gate Charge
C
17
rss
Q
Q
3.5
0.4
1.2
1.9
6
G(TOT)
Threshold Gate Charge
Gate−to−Source Charge
Gate−to−Drain Charge
Total Gate Charge
Q
G(TH)
V
= −4.5 V, V = −48 V,
DS
GS
I
= −3 A
D
Q
GS
nC
Q
GD
V
= −10 V, V = −48 V,
DS
G(TOT)
GS
I
D
= −3 A
SWITCHING CHARACTERISTICS (Note 6)
Turn−On Delay Time
Rise Time
t
7
d(on)
t
r
14
13
10
V
GS
I
= −4.5 V, V = −48 V,
DS
ns
= −3 A, R = 2.5 W
D
G
Turn−Off Delay Time
Fall Time
t
d(off)
t
f
DRAIN−SOURCE DIODE CHARACTERISTICS
Forward Diode Voltage
V
V
= 0 V,
T = 25°C
−0.87
−0.74
17
−1.0
V
SD
RR
GS
S
J
I
= −3 A
T = 125°C
J
Reverse Recovery Time
Charge Time
t
ns
V
GS
= 0 V,
t
14
a
dI /dt = 100 A/ms,
S
Discharge Time
t
3
I
= −3 A
b
S
Reverse Recovery Charge
Q
19
nC
RR
5. Pulse Test: Pulse Width ≤ 300 ms, Duty Cycle ≤ 2%.
6. Switching characteristics are independent of operating junction temperatures.
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2
NVTFS5124PL
TYPICAL CHARACTERISTICS
8
8
6
4
2
0
T = 25°C
V
DS
≥ −10 V
J
−4.5 V
−10 V
6
4
2
0
−4.0 V
−3.5 V
T = 25°C
J
V
GS
= −3 V
T = 125°C
J
T = −55°C
J
0
1
2
3
4
5
1
2
3
4
5
6
−V , DRAIN−TO−SOURCE VOLTAGE (V)
DS
−V , GATE−TO−SOURCE VOLTAGE (V)
GS
Figure 1. On−Region Characteristics
Figure 2. Transfer Characteristics
0.50
0.40
0.30
0.20
0.10
0.50
0.40
0.30
0.20
0.10
T = 25°C
I
= −3 A
J
D
T = 25°C
J
V
GS
= −4.5 V
V
GS
= −10 V
2
4
6
8
10
2
4
6
8
10
12
14
−V , GATE−TO−SOURCE VOLTAGE (V)
GS
−I , DRAIN CURRENT (A)
D
Figure 3. On−Resistance vs. Gate−to−Source
Figure 4. On−Resistance vs. Drain Current and
Voltage
Gate Voltage
2.2
10000
1000
100
V
GS
= 0 V
V
= −10 V
= −3 A
2.0
1.8
1.6
1.4
1.2
1.0
0.8
0.6
0.4
GS
I
D
T = 150°C
J
T = 125°C
J
10
−50 −25
0
25
50
75
100 125 150 175
10
20
30
40
50
60
T , JUNCTION TEMPERATURE (°C)
J
−V , DRAIN−TO−SOURCE VOLTAGE (V)
DS
Figure 5. On−Resistance Variation with
Figure 6. Drain−to−Source Leakage Current
Temperature
vs. Voltage
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3
NVTFS5124PL
TYPICAL CHARACTERISTICS
10
Q
T
V
GS
= 0 V
300
200
100
0
T = 25°C
J
8
6
4
2
0
C
iss
Q
Q
gd
gs
V
= −48 V
= −3 A
DS
I
D
C
oss
T = 25°C
J
C
rss
0
10
20
30
40
50
60
0
2
4
6
−V , DRAIN−TO−SOURCE VOLTAGE (V)
DS
Q , TOTAL GATE CHARGE (nC)
g
Figure 7. Capacitance Variation
Figure 8. Gate−to−Source Voltage vs. Total
Charge
30
20
10
0
1000.0
100.0
10.0
V
= 0 V
GS
V
= −48 V
= −3 A
= −10 V
DD
T = 25°C
J
I
D
V
GS
t
d(off)
t
r
t
f
t
d(on)
1.0
1
10
R , GATE RESISTANCE (W)
100
0.5
0.6
0.7
0.8
0.9
1.0
1.1
1.2
1.3
−V , SOURCE−TO−DRAIN VOLTAGE (V)
G
SD
Figure 9. Resistive Switching Time Variation
vs. Gate Resistance
Figure 11. Diode Forward Voltage vs. Current
1000
100
10
10
8
V
= −10 V
GS
I
D
= −13 A
Single Pulse
= 25°C
T
C
100 ms
1 ms
6
10 ms
10 ms
4
dc
1
2
R
Limit
DS(on)
Thermal Limit
Package Limit
0.1
0
0.1
1
10
100
25
50
75
100
125
150
175
T , STARTING JUNCTION TEMPERATURE (°C)
J
−V , DRAIN−TO−SOURCE VOLTAGE (V)
DS
Figure 12. Maximum Avalanche Energy vs.
Starting Junction Temperature
Figure 10. Maximum Rated Forward Biased
Safe Operating Area
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4
NVTFS5124PL
TYPICAL CHARACTERISTICS
100
10
1
Duty Cycle = 0.5
0.2
0.1
0.05
0.02
0.01
Single Pulse
0.1
0.000001
0.00001
0.0001
0.001
0.01
0.1
1
10
100
1000
PULSE TIME (sec)
Figure 13. Thermal Response
DEVICE ORDERING INFORMATION
Device
†
Marking
Package
Shipping
NVTFS5124PLTAG
5124
24LW
5124
24LW
WDFN8
1500 / Tape & Reel
1500 / Tape & Reel
5000 / Tape & Reel
5000 / Tape & Reel
(Pb−Free)
NVTFS5124PLWFTAG
NVTFS5124PLTWG
WDFN8
(Pb−Free)
WDFN8
(Pb−Free)
NVTFS5124PLWFTWG
WDFN8
(Pb−Free)
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
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5
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
WDFN8 3.3x3.3, 0.65P
CASE 511AB
1
SCALE 2:1
2X
ISSUE D
DATE 23 APR 2012
NOTES:
0.20
C
1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS.
3. DIMENSION D1 AND E1 DO NOT INCLUDE MOLD FLASH
PROTRUSIONS OR GATE BURRS.
D
A
B
E
2X
D1
MILLIMETERS
INCHES
NOM
0.030
−−−
0.012
0.20
C
8
1
7
6
5
4
DIM
A
A1
b
c
MIN
0.70
0.00
0.23
0.15
NOM
0.75
−−−
0.30
0.20
MAX
MIN
MAX
0.031
0.002
0.016
0.010
0.80
0.05
0.40
0.25
0.028
0.000
0.009
0.006
4X
q
E1
0.008
D
3.30 BSC
3.05
2.11
3.30 BSC
3.05
1.60
0.30
0.65 BSC
0.41
0.80
0.43
0.130 BSC
0.120
0.083
0.130 BSC
0.120
0.063
0.012
0.026 BSC
0.016
0.032
0.017
0.005
0.059
−−−
D1
D2
E
E1
E2
E3
e
G
K
L
L1
M
2.95
1.98
3.15
2.24
0.116
0.078
0.124
0.088
c
2
3
A1
TOP VIEW
2.95
1.47
0.23
3.15
1.73
0.40
0.116
0.058
0.009
0.124
0.068
0.016
0.10
0.10
C
C
A
C
6X
e
0.012
0.026
0.012
0.002
0.055
0
0.020
0.037
0.022
0.008
0.063
0.30
0.65
0.30
0.06
1.40
0
0.51
0.95
0.56
0.20
1.60
SEATING
PLANE
0.13
1.50
−−−
DETAIL A
SIDE VIEW
DETAIL A
q
12
12
_
_
_
_
8X b
0.10
0.05
C
C
A
B
SOLDERING FOOTPRINT*
8X
e/2
0.42
0.65
4X
L
4X
0.66
PITCH
1
8
4
5
PACKAGE
OUTLINE
K
E2
M
E3
3.60
L1
D2
G
2.30
BOTTOM VIEW
0.57
0.47
0.75
GENERIC
MARKING DIAGRAM*
2.37
3.46
1
XXXXX
DIMENSION: MILLIMETERS
AYWWG
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
G
XXXXX = Specific Device Code
A
Y
= Assembly Location
= Year
WW
G
= Work Week
= Pb−Free Package
*This information is generic. Please refer to
device data sheet for actual part marking.
Pb−Free indicator, “G” or microdot “G”, may
or may not be present. Some products may
not follow the Generic Marking.
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
DOCUMENT NUMBER:
DESCRIPTION:
98AON30561E
WDFN8 3.3X3.3, 0.65P
PAGE 1 OF 1
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