NVTFS6H854NLWFTAG [ONSEMI]
Single N-Channel Power MOSFET 80V, 48A, 14.5mΩ;型号: | NVTFS6H854NLWFTAG |
厂家: | ONSEMI |
描述: | Single N-Channel Power MOSFET 80V, 48A, 14.5mΩ |
文件: | 总8页 (文件大小:292K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
MOSFET - Power, Single
N-Channel
80 V, 13.4 mW, 41 A
NVTFS6H854NL
Features
• Small Footprint (3.3 x 3.3 mm) for Compact Design
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• Low R
to Minimize Conduction Losses
DS(on)
• Low Capacitance to Minimize Driver Losses
• NVTFS6H854NLWF − Wettable Flanks Product
• AEC−Q101 Qualified and PPAP Capable
V
R
MAX
I MAX
D
(BR)DSS
DS(ON)
13.4 mW @ 10 V
17.3 mW @ 4.5 V
• These Devices are Pb−Free and are RoHS Compliant
80 V
41 A
MAXIMUM RATINGS (T = 25°C unless otherwise noted)
J
Parameter
Drain−to−Source Voltage
Symbol
Value
80
Unit
V
N−Channel
D (5 − 8)
V
DSS
Gate−to−Source Voltage
V
GS
20
V
Continuous Drain
Current R
T
= 25°C
= 100°C
= 25°C
I
41
A
C
D
q
JC
T
C
29
(Notes 1, 2, 3, 4)
Steady
State
G (4)
Power Dissipation
T
C
P
54
W
A
D
R
(Notes 1, 2, 3)
q
JC
T
C
= 100°C
27
S (1, 2, 3)
Continuous Drain
Current R
T = 25°C
A
I
D
10
q
JA
T = 100°C
A
7
(Notes 1, 3, 4)
Steady
State
MARKING
DIAGRAMS
Power Dissipation
T = 25°C
A
P
3.2
1.6
182
W
D
R
(Notes 1, 3)
q
JA
1
T = 100°C
A
1
S
S
S
D
D
D
D
Pulsed Drain Current
T = 25°C, t = 10 ms
I
A
A
p
DM
XXXX
AYWWG
G
WDFN8
(m8FL)
Operating Junction and Storage Temperature
Range
T , T
−55 to
+175
°C
J
stg
G
CASE 511AB
Source Current (Body Diode)
I
S
45
A
Single Pulse Drain−to−Source Avalanche
E
AS
168
mJ
Energy (I
= 2.2 A)
L(pk)
XXXX
AYWWG
G
Lead Temperature for Soldering Purposes
T
260
°C
L
(1/8″ from case for 10 s)
WDFNW8
(Full−Cut m8FL)
CASE 515AN
Stresses exceeding those listed in the Maximum Ratings table may damage the
device. If any of these limits are exceeded, device functionality should not be
assumed, damage may occur and reliability may be affected.
XXXX = Specific Device Code
THERMAL RESISTANCE MAXIMUM RATINGS (Note 1)
A
Y
= Assembly Location
= Year
Parameter
Symbol
Value
2.8
Unit
WW
G
= Work Week
= Pb−Free Package
(Note: Microdot may be in either location)
Junction−to−Case − Steady State (Note 3)
Junction−to−Ambient − Steady State (Note 3)
R
°C/W
q
JC
R
47
q
JA
1. The entire application environment impacts the thermal resistance values shown,
they are not constants and are only valid for the particular conditions noted.
2. Psi (Y) is used as required per JESD51−12 for packages in which
substantially less than 100% of the heat flows to single case surface.
ORDERING INFORMATION
See detailed ordering, marking and shipping information in the
package dimensions section on page 5 of this data sheet.
2
3. Surface−mounted on FR4 board using a 650 mm , 2 oz. Cu pad.
4. Continuous DC current rating. Maximum current for pulses as long as 1
second is higher but is dependent on pulse duration and duty cycle.
© Semiconductor Components Industries, LLC, 2019
1
Publication Order Number:
November, 2020 − Rev. 1
NVTFS6H854NL/D
NVTFS6H854NL
ELECTRICAL CHARACTERISTICS (T = 25°C unless otherwise noted)
J
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
OFF CHARACTERISTICS
Drain−to−Source Breakdown Voltage
Zero Gate Voltage Drain Current
V
V
= 0 V, I = 250 mA
80
V
(BR)DSS
GS
D
I
T = 25°C
10
mA
DSS
J
V
= 0 V,
= 80 V
GS
DS
V
T = 125°C
J
100
100
Gate−to−Source Leakage Current
ON CHARACTERISTICS (Note 5)
Gate Threshold Voltage
I
V
V
V
= 0 V, V = 20 V
nA
GSS
DS
GS
V
= V , I = 45 mA
1.2
2.0
V
GS(TH)
GS
DS
D
Drain−to−Source On Resistance
R
V
= 10 V, I = 10 A
11.1
13.8
56
13.4
17.3
mW
DS(on)
GS
D
= 4.5 V, I = 10 A
GS
D
Forward Transconductance
CHARGES AND CAPACITANCES
Input Capacitance
g
FS
V
= 15 V, I = 20 A
S
DS
D
C
902
118
7
pF
iss
V
= 0 V, f = 1 MHz,
DS
GS
Output Capacitance
C
oss
V
= 40 V
Reverse Transfer Capacitance
Total Gate Charge
C
rss
Q
Q
V
V
= 10 V, V = 40 V, I = 20 A
17
2
nC
G(TOT)
GS
DS
D
Threshold Gate Charge
Gate−to−Source Charge
Gate−to−Drain Charge
Plateau Voltage
Q
G(TH)
Q
3.0
2.9
3.0
8
GS
GD
GP
Q
V
= 4.5 V, V = 40 V, I = 20 A
GS
DS
D
V
Total Gate Charge
nC
G(TOT)
SWITCHING CHARACTERISTICS (Note 6)
Turn−On Delay Time
Rise Time
t
10
36
17
6
ns
d(on)
t
r
V
= 4.5 V, V = 64 V,
DS
GS
D
I
= 20 A, R = 2.5 W
G
Turn−Off Delay Time
Fall Time
t
d(off)
t
f
DRAIN−SOURCE DIODE CHARACTERISTICS
Forward Diode Voltage
V
T = 25°C
0.82
0.68
32
1.2
V
SD
J
V
= 0 V,
GS
S
I
= 10 A
T = 125°C
J
Reverse Recovery Time
Charge Time
t
ns
RR
t
t
20
a
V
GS
= 0 V, dl /dt = 100 A/ms,
S
I
S
= 20 A
Discharge Time
12
b
Reverse Recovery Charge
Q
25
nC
RR
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
5. Pulse Test: Pulse Width ≤ 300 ms, Duty Cycle ≤ 2%.
6. Switching characteristics are independent of operating junction temperatures.
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2
NVTFS6H854NL
TYPICAL CHARACTERISTICS
40
35
30
25
20
15
10
40
3.2 V to 10 V
V
DS
= 5 V
3.0 V
2.8 V
30
20
T = 25°C
J
2.6 V
10
0
V
= 2.4 V
5
0
GS
T = 125°C
J
T = −55°C
J
0
1
2
3
4
5
6
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
V
DS
, DRAIN−TO−SOURCE VOLTAGE (V)
V
GS
, GATE−TO−SOURCE VOLTAGE (V)
Figure 1. On−Region Characteristics
Figure 2. Transfer Characteristics
20
18
16
14
12
15
14
13
12
11
T = 25°C
J
T = 25°C
D
J
V
= 4.5 V
= 10 V
6
GS
I
= 10 A
V
GS
10
10
9
8
6
3
4
5
6
7
8
9
10
11
12
1
2
3
4
5
7
8
9
10
V
GS
, GATE−TO−SOURCE VOLTAGE (V)
I , DRAIN CURRENT (A)
D
Figure 3. On−Resistance vs. Gate−to−Source
Figure 4. On−Resistance vs. Drain Current and
Voltage
Gate Voltage
100K
10K
1K
2.5
2.0
T = 175°C
J
V
GS
= 10 V
T = 150°C
J
T = 125°C
J
T = 85°C
J
100
10
1.5
1.0
0.5
T = 25°C
J
1
0.1
5
15
V
25
35
45
55
65
75
−50 −25
0
25
50
75 100 125 150 175
T , JUNCTION TEMPERATURE (°C)
, DRAIN−TO−SOURCE VOLTAGE (V)
DS
J
Figure 5. On−Resistance Variation with
Figure 6. Drain−to−Source Leakage Current
Temperature
vs. Voltage
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3
NVTFS6H854NL
TYPICAL CHARACTERISTICS
10
10K
1K
V
= 40 V
= 20 A
DS
9
8
7
6
5
4
3
2
I
D
C
ISS
C
C
100
OSS
Q
Q
4
GS
GD
10
1
V
= 0 V
RSS
GS
T = 25°C
J
1
0
f = 1 MHz
0
10
20
30
40
50
60
70
80
0
2
6
8
10
12
14
16 18
V
DS
, DRAIN−TO−SOURCE VOLTAGE (V)
Q , TOTAL GATE CHARGE (nC)
G
Figure 7. Capacitance Variation
Figure 8. Gate−to−Source vs. Total Charge
100
10
V
GS
= 0 V
t
r
t
d(off)
t
d(on)
10
t
f
V
V
= 4.5 V
= 64 V
GS
DS
I
D
= 20 A
T = 125°C
T = 25°C
T = −55°C
J
J
J
1
1
1
10
R , GATE RESISTANCE (W)
100
0.4
0.5
0.6
0.7
0.8
0.9
1.0
V
SD
, SOURCE−TO−DRAIN VOLTAGE (V)
G
Figure 9. Resistive Switching Time Variation
vs. Gate Resistance
Figure 10. Diode Forward Voltage vs. Current
100
10
1K
100
10
T (initial) = 25°C
J
T
V
= 25°C
C
T (initial) = 100°C
J
≤ 10 V
GS
1
10 ms
Single Pulse
1
0.5 ms
1 ms
R
Limit
DS(on)
Thermal Limit
Package Limit
10 ms
0.1
0.1
0.00001
0.0001
0.001
0.01
0.1
1
10
100
1K
V
DS
, DRAIN−TO−SOURCE VOLTAGE (V)
TIME IN AVALANCHE (s)
Figure 11. Maximum Rated Forward Biased
Safe Operating Area
Figure 12. Maximum Drain Current vs. Time in
Avalanche
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4
NVTFS6H854NL
TYPICAL CHARACTERISTICS
100
10
1
50% Duty Cycle
20%
10%
5%
2%
1%
0.1
Single Pulse
0.01
0.000001 0.00001
0.0001
0.001
0.01
0.1
1
10
100
1000
t, PULSE TIME (sec)
Figure 13. Thermal Response
DEVICE ORDERING INFORMATION
Device
†
Marking
Package
Shipping
NVTFS6H854NLTAG
854L
WDFN8
1500 / Tape & Reel
1500 / Tape & Reel
(Pb−Free)
NVTFS6H854NLWFTAG
54LW
WDFN8
(Pb−Free, Wettable Flanks)
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
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5
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
WDFN8 3.3x3.3, 0.65P
CASE 511AB
1
SCALE 2:1
2X
ISSUE D
DATE 23 APR 2012
NOTES:
0.20
C
1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS.
3. DIMENSION D1 AND E1 DO NOT INCLUDE MOLD FLASH
PROTRUSIONS OR GATE BURRS.
D
A
B
E
2X
D1
MILLIMETERS
INCHES
NOM
0.030
−−−
0.012
0.20
C
8
1
7
6
5
4
DIM
A
A1
b
c
MIN
0.70
0.00
0.23
0.15
NOM
0.75
−−−
0.30
0.20
MAX
MIN
MAX
0.031
0.002
0.016
0.010
0.80
0.05
0.40
0.25
0.028
0.000
0.009
0.006
4X
q
E1
0.008
D
3.30 BSC
3.05
2.11
3.30 BSC
3.05
1.60
0.30
0.65 BSC
0.41
0.80
0.43
0.130 BSC
0.120
0.083
0.130 BSC
0.120
0.063
0.012
0.026 BSC
0.016
0.032
0.017
0.005
0.059
−−−
D1
D2
E
E1
E2
E3
e
G
K
L
L1
M
2.95
1.98
3.15
2.24
0.116
0.078
0.124
0.088
c
2
3
A1
TOP VIEW
2.95
1.47
0.23
3.15
1.73
0.40
0.116
0.058
0.009
0.124
0.068
0.016
0.10
0.10
C
C
A
C
6X
e
0.012
0.026
0.012
0.002
0.055
0
0.020
0.037
0.022
0.008
0.063
0.30
0.65
0.30
0.06
1.40
0
0.51
0.95
0.56
0.20
1.60
SEATING
PLANE
0.13
1.50
−−−
DETAIL A
SIDE VIEW
DETAIL A
q
12
12
_
_
_
_
8X b
0.10
0.05
C
C
A
B
SOLDERING FOOTPRINT*
8X
e/2
0.42
0.65
4X
L
4X
0.66
PITCH
1
8
4
5
PACKAGE
OUTLINE
K
E2
M
E3
3.60
L1
D2
G
2.30
BOTTOM VIEW
0.57
0.47
0.75
GENERIC
MARKING DIAGRAM*
2.37
3.46
1
XXXXX
DIMENSION: MILLIMETERS
AYWWG
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
G
XXXXX = Specific Device Code
A
Y
= Assembly Location
= Year
WW
G
= Work Week
= Pb−Free Package
*This information is generic. Please refer to
device data sheet for actual part marking.
Pb−Free indicator, “G” or microdot “G”, may
or may not be present. Some products may
not follow the Generic Marking.
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
DOCUMENT NUMBER:
DESCRIPTION:
98AON30561E
WDFN8 3.3X3.3, 0.65P
PAGE 1 OF 1
onsemi and
are trademarks of Semiconductor Components Industries, LLC dba onsemi or its subsidiaries in the United States and/or other countries. onsemi reserves
the right to make changes without further notice to any products herein. onsemi makes no warranty, representation or guarantee regarding the suitability of its products for any particular
purpose, nor does onsemi assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation
special, consequential or incidental damages. onsemi does not convey any license under its patent rights nor the rights of others.
© Semiconductor Components Industries, LLC, 2019
www.onsemi.com
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
WDFNW8 3.3x3.3, 0.65P (Full−Cut m8FL WF)
CASE 515AN
ISSUE O
DATE 25 AUG 2020
GENERIC
MARKING DIAGRAM*
XXXX = Specific Device Code
*This information is generic. Please refer to
A
Y
= Assembly Location
= Year
device data sheet for actual part marking.
Pb−Free indicator, “G” or microdot “G”, may
or may not be present. Some products may
not follow the Generic Marking.
XXXX
AYWWG
G
WW = Work Week
G
= Pb−Free Package
(Note: Microdot may be in either location)
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
DOCUMENT NUMBER:
DESCRIPTION:
98AON24556H
WDFNW8 3.3x3.3, 0.65P (Full−Cut m8FL WF)
PAGE 1 OF 1
ON Semiconductor and
are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.
ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding
the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically
disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the
rights of others.
© Semiconductor Components Industries, LLC, 2018
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