NXV65HR82DS2 [ONSEMI]

汽车功率模块H桥APM16系列,用于LLC和移相DC-DC转换器。;
NXV65HR82DS2
型号: NXV65HR82DS2
厂家: ONSEMI    ONSEMI
描述:

汽车功率模块H桥APM16系列,用于LLC和移相DC-DC转换器。

DC-DC转换器
文件: 总13页 (文件大小:765K)
中文:  中文翻译
下载:  下载PDF数据表文档文件
H-Bridge in APM16 Series  
for LLC and Phase-shifted  
DC-DC Converter  
NXV65HR82DS1,  
NXV65HR82DS2,  
NXV65HR82DZ1,  
NXV65HR82DZ2  
www.onsemi.com  
Features  
SIP or DIP HBridge Power Module for Onboard Charger (OBC) in  
EV or PHEV  
5 kV/1 s Electrically Isolated Substrate for Easy Assembly  
Creepage and Clearance per IEC606641, IEC 609501  
Compact Design for Low Total Module Resistance  
Module Serialization for Full Traceability  
APMCAA16  
16 LEAD  
CASE MODGF  
Lead Free, RoHS and UL94V0 Compliant  
Automotive Qualified per AEC Q101 and AQG324 Guidelines  
Applications  
DCDC Converter for Onboard Charger in EV or PHEV  
Benefits  
Enable Design of Small, Efficient and Reliable System for Reduced  
APMCAB16  
16 LEAD  
CASE MODGJ  
Vehicle Fuel Consumption and CO Emission  
2
Simplified Assembly, Optimized Layout, High Level of Integration,  
and Improved Thermal Performance  
MARKING DIAGRAM  
XXXXXXXXXXX  
ZZZ ATYWW  
NNNNNNN  
XXXX = Specific Device Code  
ZZZ = Lot ID  
AT  
Y
= Assembly & Test Location  
= Year  
W
= Work Week  
NNN = Serial Number  
ORDERING INFORMATION  
See detailed ordering, marking and shipping information on  
page 10 of this data sheet.  
© Semiconductor Components Industries, LLC, 2020  
1
Publication Order Number:  
April, 2021 Rev. 2  
NXV65HR82D/D  
NXV65HR82DS1, NXV65HR82DS2, NXV65HR82DZ1, NXV65HR82DZ2  
Pin Configuration and Block Diagram  
Figure 1. Pin Configuration  
Table 1. PIN DESCRIPTION  
Pin Number  
Pin Name  
Pin Description  
1, 2  
3
AC1  
Q1 Sense  
Q1 Gate  
B+  
Phase 1 Leg of the HBridge  
Source Sense of Q1  
Gate Terminal of Q1  
Positive Battery Terminal  
Negative Battery Terminal  
Source Sense of Q2  
Gate Terminal of Q2  
Source Sense of Q4  
Gate Terminal of Q4  
Source Sense of Q3  
Gate Terminal of Q3  
Phase 2 Leg of the HBridge  
4
5, 6  
7, 8  
9
B−  
Q2 Sense  
Q2 Gate  
Q4 Sense  
Q4 Gate  
Q3 Sense  
Q3 Gate  
AC2  
10  
11  
12  
13  
14  
15, 16  
Block Diagram  
NXV65HR82DZ1/2 (No Capacitor)  
NXV65HR82DS1/2 (With Capacitor)  
Figure 2. Schematic  
www.onsemi.com  
2
NXV65HR82DS1, NXV65HR82DS2, NXV65HR82DZ1, NXV65HR82DZ2  
Table 2. ABSOLUTE MAXIMUM RATINGS (T = 25°C, Unless Otherwise Specified)  
J
Symbol  
Parameter  
Max  
650  
Unit  
V
V
V
(Q1~Q4)  
(Q1~Q4)  
DraintoSource Voltage  
GatetoSource Voltage  
DS  
GS  
20  
V
Drain Current Continuous (T = 25°C, V = 10 V) (Note 1)  
26  
A
I
D
(Q1~Q4)  
C
GS  
Drain Current Continuous (T = 100°C, V = 10 V) (Note 1)  
17  
A
C
GS  
P
Power Dissipation (Note 1)  
126  
W
°C  
°C  
°C  
D
T
Maximum Junction Temperature  
Maximum Case Temperature  
Storage Temperature  
55 to +150  
40 to +125  
40 to +125  
J
T
C
T
STG  
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality  
should not be assumed, damage may occur and reliability may be affected.  
1. Maximum continuous current and power, without switching losses, to reach T = 150°C respectively at T = 25°C and T = 100°C; defined  
J
C
C
by design based on MOSFET R  
and R  
and not subject to production test  
q
DS(ON)  
JC  
Table 3. SINGLE PULSE AVALANCHE ENERGY  
Symbol  
Parameter  
Max  
510  
21  
Unit  
mJ  
mJ  
A
E
E
(Q1~Q4)  
(Q1~Q4)  
Single Pulsed Avalanche Energy (Note 2)  
Single Pulsed Avalanche Energy (Note 2)  
Avalanche Current  
AS  
AS  
I
AS  
4.8  
2. 510 mJ is characterized at T = 25°C, L = 44.3 mH, I = 4.8 A, V = 145 V.  
J
AS  
DD  
21 mJ is 100% tested at T = 25°C, L = 1 mH, I = 4.8 A, V = 145 V.  
J
AS  
DD  
Table 4. COMPONENTS (Note 3)  
Device  
Parameter  
Capacitance  
Rated Voltage  
Condition  
Min  
Typ  
150  
630  
Max  
165  
Unit  
Capacitor (Snubber)  
AEC Q200 qualified  
T = 25°C  
J
135  
nF  
V
3. These values are obtained from the specification provided by the manufacturer.  
DBC Substrate  
Compliance to RoHS Directives  
0.63 mm Al O alumina with 0.3 mm copper on both sides.  
DBC substrate is NOT nickel plated.  
The power module is 100% lead free and RoHS compliant  
2000/53/C directive.  
2
3
Lead Frame  
Solder  
OFC copper alloy, 0.50 mm thick. Plated with 8 um to  
25.4 um thick Matte Tin  
Solder used is a lead free SnAgCu alloy.  
Solder presents high risk to melt at temperature beyond  
210°C. Base of the leads, at the interface with the package  
body, should not be exposed to more than 200°C during  
mounting on the PCB or during welding to prevent the  
remelting of the solder joints.  
Flammability Information  
All materials present in the power module meet UL  
flammability rating class 94V0.  
www.onsemi.com  
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NXV65HR82DS1, NXV65HR82DS2, NXV65HR82DZ1, NXV65HR82DZ2  
Table 5. ELECTRICAL SPECIFICATIONS (T = 25°C, Unless Otherwise Specified)  
J
Symbol  
Parameter  
Conditions  
I = 1 mA, V = 0 V  
D
Min  
650  
3.0  
Typ  
Max  
Unit  
V
BV  
DraintoSource Breakdown Voltage  
Gate to Source Threshold Voltage  
Q1 – Q4 MOSFET On Resistance  
Q1 – Q4 MOSFET On Resistance  
Forward Transconductance  
DSS  
GS  
V
GS(th)  
V
GS  
V
GS  
V
GS  
V
DS  
V
GS  
V
DS  
= V , I = 0.97 mA  
5.0  
82  
V
DS  
D
R
R
= 10 V, I = 20 A  
73  
133  
29  
mW  
mW  
S
DS(ON)  
DS(ON)  
D
= 10 V, I = 20 A, T = 125°C (Note 4)  
D
J
g
FS  
= 20 V, I = 20 A (Note 4)  
D
I
GatetoSource Leakage Current  
DraintoSource Leakage Current  
=
30 V, V = 0 V  
100  
+100  
10  
nA  
mA  
GSS  
DS  
I
= 650 V, V = 0 V  
DSS  
GS  
DYNAMIC CHARACTERISTICS (Note 4)  
C
Input Capacitance  
V
V
= 400 V  
= 0 V  
3608  
72.3  
5.56  
448  
pF  
pF  
pF  
pF  
iss  
DS  
GS  
C
Output Capacitance  
oss  
f = 1 MHz  
C
Reverse Transfer Capacitance  
Effective Output Capacitance  
rss  
C
V
DS  
V
GS  
= 0 to 520 V  
= 0 V  
oss(eff)  
R
Gate Resistance  
f = 1 MHz  
1.7  
W
g
Q
Total Gate Charge  
V
DS  
= 380 V  
79.7  
24.9  
31.9  
nC  
nC  
nC  
g(tot)  
I
D
= 20 A  
Q
GatetoSource Gate Charge  
GatetoDrain “Miller” Charge  
gs  
V
GS  
= 0 to 10 V  
Q
gd  
SWITCHING CHARACTERISTICS (Note 4)  
t
Turnon Time  
V
= 400 V  
= 20 A  
= 10 V  
= 4.7 W  
96  
54  
ns  
ns  
ns  
ns  
ns  
ns  
on  
DS  
GS  
I
D
t
t
Turnon Delay Time  
Turnon Rise Time  
Turnoff Time  
d(on)  
V
R
t
r
42  
G
t
117  
84  
off  
d(off)  
Turnoff Delay Time  
Turnoff Fall Time  
t
f
33  
BODY DIODE CHARACTERISTICS  
V
SourcetoDrain Diode Voltage  
Reverse Recovery Time  
I
= 20 A, V = 0 V  
1.1  
107  
430  
V
SD  
SD  
GS  
T
V
= 520 V, I = 20 A,  
ns  
nC  
rr  
DS  
D
d /d = 100 A/ms (Note 4)  
I
t
Q
Reverse Recovery Charge  
rr  
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product  
performance may not be indicated by the Electrical Characteristics if operated under different conditions.  
4. Defined by design, not subject to production test  
Table 6. THERMAL RESISTANCE  
Parameters  
Min  
Typ  
0.7  
Max  
0.99  
Unit  
°C/W  
°C/W  
R
R
(per chip)  
(per chip)  
Q1~Q4 Thermal Resistance JunctiontoCase (Note 5)  
Q1~Q4 Thermal Resistance JunctiontoSink (Note 6)  
θ
JC  
JS  
1.32  
θ
5. Test method compliant with MIL STD 8831012.1, from case temperature under the chip to case temperature measured below the package  
at the chip center, Cosmetic oxidation and discoloration on the DBC surface allowed  
6. Defined by thermal simulation assuming the module is mounted on a 5 mm Al360 die casting material with 30 um of 1.8 W/mK thermal  
interface material  
Table 7. ISOLATION (Isolation resistance at tested voltage from the base plate to control pins or power terminals.)  
Test  
Test Conditions  
= 5 kV, 50 Hz  
Isolation Resistance  
Unit  
Leakage @ Isolation Voltage (HiPot)  
V
AC  
100M <  
W
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NXV65HR82DS1, NXV65HR82DS2, NXV65HR82DZ1, NXV65HR82DZ2  
PARAMETER DEFINITIONS  
Reference to Table 5: Parameter of Electrical Specifications  
BV  
Q1 – Q4 MOSFET DraintoSource Breakdown Voltage  
The maximum draintosource voltage the MOSFET can endure without the avalanche breakdown of the bodydrain  
PN junction in off state.  
The measurement conditions are to be found in Table 5.  
The typ. Temperature behavior is described in Figure 13  
DSS  
V
GS(th)  
Q1 – Q4 MOSFET Gate to Source Threshold Voltage  
The gatetosource voltage measurement is triggered by a threshold ID current given in conditions at Table 11.  
The typ. Temperature behavior can be found in Figure 12  
R
Q1 – Q4 MOSFET On Resistance  
DS(ON)  
RDS(on) is the total resistance between the source and the drain during the on state.  
The measurement conditions are to be found in Table 5.}  
The typ behavior can be found in Figure 10 and Figure 11 as well as Figure 17  
g
FS  
Q1 – Q4 MOSFET Forward Transconductance  
Transconductance is the gain in the MOSFET, expressed in the Equation below.  
t describes the change in drain current by the change in the gatesource bias voltage: g = [ DI / DV ]  
fs  
DS  
GS VDS  
I
Q1 – Q4 MOSFET GatetoSource Leakage Current  
The current flowing from Gate to Source at the maximum allowed VGS  
The measurement conditions are described in the Table 5.  
GSS  
DSS  
I
Q1 – Q4 MOSFET DraintoSource Leakage Current  
Drain – Source current is measured in off state while providing the maximum allowed drainto-source voltage and the  
gate is shorted to the source.  
IDSS has a positive temperature coefficient.  
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5
NXV65HR82DS1, NXV65HR82DS2, NXV65HR82DZ1, NXV65HR82DZ2  
Figure 3. Timing Measurement Variable Definition  
Table 8. PARAMETER OF SWITCHING CHARACTERISTICS  
TurnOn Delay (t ):  
d(on)  
This is the time needed to charge the input capacitance, Ciss, before the load current ID starts flowing.  
The measurement conditions are described in the Table 5.  
For signal definition please check Figure 3 above.  
Rise Time (t ):  
The rise time is the time to discharge output capacitance, Coss.  
After that time the MOSFET conducts the given load current ID.  
The measurement conditions are described in the Table 5.  
For signal definition please check Figure 3 above.  
r
TurnOn Time (t ):  
Is the sum of turnondelay and rise time  
on  
TurnOff Delay (t ):  
d(off)  
td(off) is the time to discharge Ciss after the MOSFET is turned off.  
During this time the load current ID is still flowing  
The measurement conditions are described in the Table 5.  
For signal definition please check Figure 3 above.  
Fall Time (t ):  
The fall time, tf, is the time to charge the output capacitance, Coss.  
During this time the load current drops down and the voltage VDS rises accordingly.  
The measurement conditions are described in the Table 5.  
f
For signal definition please check Figure 3 above.  
TurnOff Time (t ):  
Is the sum of turnoffdelay and fall time  
off  
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NXV65HR82DS1, NXV65HR82DS2, NXV65HR82DZ1, NXV65HR82DZ2  
TYPICAL CHARACTERISTICS  
1.2  
1.0  
0.8  
0.6  
0.4  
30  
V
GS  
= 10 V  
25  
20  
15  
10  
R
= 0.99°C/W  
R
= 0.99°C/W  
JC  
q
q
JC  
0.2  
0
5
0
0
25  
50  
75  
100  
125  
150  
25  
50  
75  
100  
125  
150  
T , CASE TEMPERATURE (°C)  
C
T , CASE TEMPERATURE (°C)  
C
Figure 4. Normalized Power Dissipation vs. Case  
Temperature  
Figure 5. Maximum Continuous ID vs. Case  
Temperature  
45  
40  
35  
30  
25  
20  
15  
10  
20  
10  
V = 0 V  
GS  
V
DS  
= 20 V  
1
T = 150°C  
J
T = 25°C  
J
0.1  
T = 150°C  
J
T = 55°C  
J
0.01  
T = 55°C  
J
T = 25°C  
J
5
0
0.001  
2
3
4
5
6
7
8
0
0.2  
0.4  
0.6  
0.8  
1.0  
1.2  
V
GS  
, GATE TO SOURCE VOLTAGE (V)  
V
SD  
, BODY DIODE FORWARD VOLTAGE (V)  
Figure 6. Transfer Characteristics  
Figure 7. Forward Diode  
80  
70  
60  
50  
40  
30  
20  
80  
70  
60  
50  
40  
30  
20  
V
GS  
= 20 V  
10 V  
10 V  
8 V  
V
GS  
= 20 V  
8 V  
7 V  
7 V  
6.5 V  
6 V  
6.5 V  
6 V  
5.5 V  
5.5 V  
5 V  
10  
0
10  
0
5 V  
0
5
10  
15  
20  
0
5
10  
15  
20  
V
DS  
, DRAINSOURCE VOLTAGE (V)  
V
DS  
, DRAINSOURCE VOLTAGE (V)  
Figure 8. Saturation (255C)  
Figure 9. Saturation (1505C)  
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NXV65HR82DS1, NXV65HR82DS2, NXV65HR82DZ1, NXV65HR82DZ2  
TYPICAL CHARACTERISTICS (continued)  
400  
300  
200  
2.5  
I
V
= 20 A  
I
D
= 20 A  
D
= 10 V  
GS  
2.0  
1.5  
1.0  
T = 150°C  
J
100  
0
T = 25°C  
J
0.5  
0
6
8
10  
12  
14  
75 50 25  
0
25  
50 75 100 125 150 175  
V
GS  
, GATE TO SOURCE VOLTAGE (V)  
T , JUNCTION TEMPERATURE (°C)  
J
Figure 10. OnResistance vs. GatetoSource  
Figure 11. RDS(norm) vs. Junction Temperature  
Voltage  
1.2  
1.1  
1
1.2  
1.1  
1.0  
I
D
= 0.97 mA  
I = 1 mA  
D
0.9  
0.8  
0.9  
0.8  
0.7  
0.6  
75 50 25  
0
25 50 75 100 125 150 175  
75 50 25  
0
25 50 75 100 125 150 175  
T , AMBIENT TEMPERATURE (°C)  
J
T , JUNCTION TEMPERATURE (°C)  
J
Figure 12. Normalized Vth vs. Temperature  
Figure 13. Breakdown Voltage vs. Temperature  
20  
16  
12  
8
100000  
10000  
1000  
100  
C
iss  
C
oss  
10  
f = 1 MHz  
4
0
1
0
V
GS  
= 0 V  
C
rss  
0
100  
200  
300  
400  
500  
600  
700  
0.1  
1
10  
100  
1000  
V
DS  
, DRAIN TO SOURCE VOLTAGE (V)  
V
DS  
, DRAIN TO SOURCE VOLTAGE (V)  
Figure 14. Eoss vs. DraintoSource Voltage  
Figure 15. Capacitance Variation  
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NXV65HR82DS1, NXV65HR82DS2, NXV65HR82DZ1, NXV65HR82DZ2  
TYPICAL CHARACTERISTICS (continued)  
10  
8
0.10  
130 V  
380 V  
0.09  
400 V  
0.08  
6
V
GS  
= 10 V  
0.07  
4
V
GS  
= 20 V  
0.06  
0.05  
2
0
0
15  
30  
45  
60  
75  
90  
0
20  
40  
I , DRAIN CURRENT (A)  
60  
80  
CHARGE (nC)  
D
Figure 16. Gate Charge  
Figure 17. RDS(ON) vs. ID  
1000  
100  
10  
For temperature above 25°C  
Derate peak current as follows:  
1000  
* Ǹb2  
* 4ac  
I + I2  
2a  
Notes:  
Limited I  
203 A  
DM  
R
= 0.99°C/W  
q
JC  
Peak T = P  
x Z (t)+ T  
q
JC C  
J
DM  
100 ms  
Duty Cycle, D = t / t  
1
2
R
LIMIT  
DS(ON)  
100  
10  
1 ms  
1
SINGLE PULSE  
10 ms  
R
Limit  
DS(on)  
R
T
= 0.99°C/W  
= 25°C  
q
JC  
Thermal Limit  
Package Limit  
100 ms/  
DC  
C
Single Pulse  
0.1  
1
10  
100  
1000  
0.000001 0.00001 0.0001  
0.001  
0.01  
0.1  
1
V
DS  
, DRAINSOURCE VOLTAGE (V)  
t, PULSE WIDTH (s)  
Figure 18. Safe Operating Area  
Figure 19. Peak Current Capability  
10  
1
Duty cycle = 0.5  
0.2  
0.1  
0.1  
0.05  
0.02  
Notes:  
(t) = r(t) x R  
0.01  
0.01  
Z
q
q
JC  
JC  
R
= 0.99°C/W  
q
JC  
Peak T = P  
Duty Cycle, D = t / t  
x Z (t) + T  
q
JC C  
J
DM  
Single pulse  
1
2
0.001  
0.00001  
0.0001  
0.001  
0.01  
0.1  
1
t, PULSE TIME (s)  
Figure 20. Transient Thermal Impedance  
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NXV65HR82DS1, NXV65HR82DS2, NXV65HR82DZ1, NXV65HR82DZ2  
ORDERING INFORMATION  
Snubber  
DBC  
PbFree and  
Operating  
Packing  
Capacitor Inside Material RoHS Compliant Temperature (T ) Method  
Part Number  
NXV65HR82DS1  
NXV65HR82DS2  
NXV65HR82DZ1  
NXV65HR82DZ2  
Package  
Lead Forming  
YShape  
A
APM16CAA  
APM16CAB  
APM16CAA  
APM16CAB  
Yes  
Yes  
No  
Al O  
Yes  
Yes  
Yes  
Yes  
40°C~125°C  
40°C~125°C  
40°C~125°C  
40°C~125°C  
Tube  
Tube  
Tube  
Tube  
2
3
3
3
3
LShape  
Al O  
2
YShape  
Al O  
2
LShape  
No  
Al O  
2
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MECHANICAL CASE OUTLINE  
PACKAGE DIMENSIONS  
APMCAA16 / 16LD, AUTOMOTIVE MODULE  
CASE MODGF  
ISSUE C  
DATE 03 NOV 2021  
GENERIC  
MARKING DIAGRAM*  
XXXX = Specific Device Code  
ZZZ = Lot ID  
*This information is generic. Please refer to  
device data sheet for actual part marking.  
PbFree indicator, “G” or microdot “G”, may  
or may not be present. Some products may  
not follow the Generic Marking.  
AT  
Y
W
= Assembly & Test Location  
= Year  
= Work Week  
XXXXXXXXXXXXXXXX  
ZZZ ATYWW  
NNNNNNN  
NNN = Serial Number  
Electronic versions are uncontrolled except when accessed directly from the Document Repository.  
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.  
DOCUMENT NUMBER:  
DESCRIPTION:  
98AON94732G  
APMCAA16 / 16LD, AUTOMOTIVE MODULE  
PAGE 1 OF 1  
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© Semiconductor Components Industries, LLC, 2018  
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MECHANICAL CASE OUTLINE  
PACKAGE DIMENSIONS  
APMCAB16 / 16LD, AUTOMOTIVE MODULE  
CASE MODGJ  
ISSUE C  
DATE 03 NOV 2021  
GENERIC  
MARKING DIAGRAM*  
XXXX = Specific Device Code  
ZZZ = Lot ID  
*This information is generic. Please refer to  
device data sheet for actual part marking.  
PbFree indicator, “G” or microdot “G”, may  
or may not be present. Some products may  
not follow the Generic Marking.  
AT  
Y
W
= Assembly & Test Location  
= Year  
= Work Week  
XXXXXXXXXXXXXXXX  
ZZZ ATYWW  
NNNNNNN  
NNN = Serial Number  
Electronic versions are uncontrolled except when accessed directly from the Document Repository.  
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APMCAB16 / 16LD, AUTOMOTIVE MODULE  
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