P1727DG-08-SR [ONSEMI]
1727 SERIES, PLL BASED CLOCK DRIVER, 1 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO8, 0.150 INCH, GREEN, SOIC-8;型号: | P1727DG-08-SR |
厂家: | ONSEMI |
描述: | 1727 SERIES, PLL BASED CLOCK DRIVER, 1 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO8, 0.150 INCH, GREEN, SOIC-8 驱动 光电二极管 输出元件 逻辑集成电路 |
文件: | 总6页 (文件大小:162K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
P1727
Notebook LCD Panel EMI
Reduction IC
Features
• FCC approved method of EMI attenuation
system cost savings by reducing the number of circuit
board layers and shielding that are traditionally required
to pass EMI regulations.
• Generates a low EMI spread spectrum of the input
clock frequency
The P1727 modulates the output of a single PLL in
order to “spread” the bandwidth of a synthesized clock,
thereby decreasing the peak amplitudes of its
harmonics. This result in significantly lower system EMI
compared to the typical narrow band signal produced
by oscillators and most clock generators. Lowering EMI
by increasing a signal’s bandwidth is called spread
spectrum clock generation.
• Optimized for frequency range: P1727X: 20MHz to
40MHz
• Internal loop filter minimizes external components
and board space
• 8 different frequency deviations ranging from
±0.625% to –3.50%
• Low inherent Cycle-to-cycle jitter
• 3.3V Operating Voltage
The P1727 uses the most efficient and optimized
modulation profile approved by the FCC and is
implemented by using a proprietary all-digital method.
• Supports notebook VGA and other LCD timing
controller applications
• Available in 8-pin SOIC.
Applications
The P1727 is targeted towards notebook LCD displays,
other displays using an LVDS interface, PC peripheral
devices and embedded systems.
Product Description
The P1727 is a versatile spread spectrum frequency
modulator designed specifically for a wide range of
clock frequencies. The P1727 reduces electromagnetic
interference (EMI) at the clock source, allowing system
wide reduction of EMI of down stream (clock and data
dependent signals). The P1727 allows significant
Block Diagram
VDD
PDB
PLL
Modulation
CLKIN
Frequency
Divider
Phase
Detector
ModOUT
REFOUT
Loop
Filter
VCO
Output
Divider
Feedback
Divider
VSS
©2010 SCILLC. All rights reserved.
Publication Order Number:
NOVEMBER 2010 – Rev. 1.1
P1727/D
P1727
Pin Configuration
PDB
NC
CLKIN
VDD
1
2
3
4
8
7
6
5
P1727
NC
VSS
ModOUT
REFOUT
Table 1 – Power Down Selection
PDB
Spread Spectrum
ModOUT
Disabled
Normal
PLL
Mode
Power Down
Normal
0
1
N/A
ON
Disabled
Normal
Table 2 – Frequency Deviation Selection
P/ N
Deviation
-1.25%
P/N
Deviation
P1727A
P1727B
P1727C
P1727D
P1727E
P1727F
P1727G
P1727H
±0.625%
±0.875%
±1.25%
±1.75%
-1.75%
-2.50%
-3.50%
Pin Description
Pin#
Pin Name
Type
Description
External reference frequency input. Connect to externally generated
reference signal.
1
CLKIN
I
2
3
4
5
6
7
8
VDD
VSS
P
P
Connect to +3.3V.
Ground Connection. Connect to system ground.
Spread Spectrum Clock output.
Reference output.
ModOUT
REFOUT
NC
O
O
No connect.
NC
No connect.
PDB
I
Powerdown Pin. Pull low to disable spread spectrum clock output.
Rev. 1 | Page 2 of 6 | www.onsemi.com
P1727
Schematic for notebook VGA application
27MHz Pixel Clock input
Tie low to enable
Powerdown mode.
CLKIN
VDD
1
2
3
PDB 8
VDD
NC
7
P1727
0.1 µF
NC
6
VSS
4
ModOUT
REFOUT
5
ModOut Clock
Reference Clock O/P
Absolute Maximum Ratings
Symbol
Parameter
Rating
-0.5 to +7
-65 to +125
260
Unit
V
VDD, VIN
TSTG
Ts
Voltage on any pin with respect to Ground
Storage temperature
°C
Max. Soldering Temperature (10 sec)
Junction Temperature
°C
TJ
150
°C
TDV
Static Discharge Voltage (As per JEDEC STD22- A114-B)
2
KV
Note: These are stress ratings only and are not implied for functional use. Exposure to absolute maximum ratings for prolonged periods of time may affect
device reliability.
Operating Conditions
Symbol
VDD
TA
Parameter
Supply Voltage with respect to VSS
Min
3.0
Max
3.6
+85
15
Unit
V
Operating temperature
Load Capacitance
Input Capacitance
-40
°C
CL
pF
pF
CIN
7
Rev. 1 | Page 3 of 6 | www.onsemi.com
P1727
DC Electrical Characteristics
Symbol
Parameter
Min
VSS – 0.3
2.0
Typ
Max
Unit
VIL
VIH
IIL
Input Low voltage
Input High voltage
Input Low current
Input High current
Output Low current
Output High current
0.8
V
VDD +0.3
-35
V
µA
µA
V
IIH
35
VOL
VOH
IDD
VDD = 3.3V, IOL = 20mA
VDD = 3.3V, IOH = 20mA
0.4
2.5
3.0
V
Static Supply Current (CLKIN, PDB pulled Low)
Dynamic Supply Current (No Load)
Operating Voltage
2
mA
mA
V
ICC
14
3.3
0.18
50
18
3.6
VDD
tON
ZOUT
Power up time (first locked clock cycle after power up)
Clock Output impedance
mS
ꢀ
AC Electrical Characteristics
Symbol
Parameter
Min
Typ
Max
Unit
fIN
Input Frequency:
Output Frequency:
Output Rise time
Output Fall time
P1727X
20
20
40
40
MHz
MHz
nS
fOUT
P1727X
1
tLH
Measured from 0.8V to 2.0V
Measured from 2.0V to 0.8V
0.7
0.6
0.9
0.8
225
50
1.1
1.0
325
55
1
tHL
nS
tJC
Jitter (Cycle-to-cycle)
pS
tD
Output Duty cycle
45
%
Note: 1. tLH and tHL are measured with a capacitive load of 15pF.
Rev. 1 | Page 4 of 6 | www.onsemi.com
P1727
Package Information
8-lead (150-mil) SOIC Package
H
E
D
A2
A
C
θ
e
A1
L
B
Dimensions
Symbol
Inches
Millimeters
Min
Max
0.010
0.069
0.059
0.020
0.010
Min
0.10
1.35
1.25
0.31
0.18
Max
0.25
1.75
1.50
0.51
0.25
A1
A
0.004
0.053
0.049
0.012
0.007
A2
B
C
D
E
0.193 BSC
0.154 BSC
0.050 BSC
0.236 BSC
4.90 BSC
3.91 BSC
1.27 BSC
6.00 BSC
e
H
L
0.016
0°
0.050
8°
0.41
0°
1.27
8°
θ
Rev. 1 | Page 5 of 6 | www.onsemi.com
P1727
Ordering Information
Part number
Marking
Package Configuration
Temperature Range
0°C to +70°C
P1727AF-08SR
ABW
8-PIN SOIC, TAPE & REEL, Green
A “microdot” placed at the end of last row of marking or just below the last row toward the center of package indicates Pb-free.
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including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or
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