PCA9655EDTR2G [ONSEMI]
Remote 16-bit I/O Expander for I2C Bus with Interrupt; 远程16位I2C总线I / O扩展器，带有中断
| 型号： | PCA9655EDTR2G |
| 厂家： | 
ONSEMI |
| 描述： | Remote 16-bit I/O Expander for I2C Bus with Interrupt |
| 文件： | 总20页 (文件大小：215K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
PCA9655E
Remote 16-bit I/O Expander
for I2C Bus with Interrupt
The PCA9655E provides 16 bits of General Purpose parallel Input /
2
Output (GPIO) expansion through the I C−bus / SMBus.
The PCA9655E consists of two 8−bit Configuration (Input or
Output selection); Input, Output and Polarity Inversion (active−HIGH
or active−LOW operation) registers. At power on, all I/Os default to
inputs. Each I/O may be configured as either input or output by writing
to its corresponding I/O configuration bit. The data for each Input or
Output is kept in its corresponding Input or Output register. The
Polarity Inversion register may be used to invert the polarity of the
read register. All registers can be read by the system master.
The PCA9655E provides an open−drain interrupt output which is
activated when any input state differs from its corresponding input
port register state. The interrupt output is used to indicate to the system
master that an input state has changed. The power−on reset sets the
registers to their default values and initializes the device state
machine.
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MARKING
DIAGRAMS
PCA9655E
AWLYYWWG
SOIC−24
DW SUFFIX
CASE 751E
PCA96
55EG
Three hardware pins (AD0, AD1, AD2) are used to configure the
2
I C−bus slave address of the device. Up to 64 devices are allowed to
AWLYYWW
TSSOP−24
DT SUFFIX
CASE 948H
2
share the same I C−bus / SMBus.
Features
• V Operating Range: 1.65 V to 5.5 V
DD
• SDA Sink Capability: 30 mA
• 5.5 V Tolerant I/Os
PCA
9655E
ALYWG
G
1
WQFN24
MT SUFFIX
CASE 485BG
• Polarity Inversion Register
• Active LOW Interrupt Output
• Low Standby Current
• Noise Filter on SCL/SDA Inputs
• No Glitch on Power−up
XXXX = Specific Device Code
= Assembly Location
WL, L = Wafer Lot
YY, Y = Year
WW, W = Work Week
A
• Internal Power−on Reset
• 64 Programmable Slave Addresses Using Three Address Pins
• 16 I/O Pins Which Default to 16 Inputs
G or G = Pb−Free Package
(Note: Microdot may be in either location)
2
• I C SCL Clock Frequencies Supported:
Standard Mode: 100 kHz
Fast Mode: 400 kHz
Fast Mode +: 1 MHz
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 17 of this data sheet.
• ESD Performance: 2000 V Human Body Model,
200 V Machine Model
• These are Pb−Free Devices
© Semiconductor Components Industries, LLC, 2012
1
Publication Order Number:
May, 2012 − Rev. 1
PCA9655E/D
PCA9655E
BLOCK DIAGRAM
PCA9655E
IO1_0
IO1_1
IO1_2
IO1_3
IO1_4
IO1_5
IO1_6
IO1_7
8−bit
AD0
AD1
AD2
INPUT/
OUTPUT
PORTS
write pulse
read pulse
2
I C−BUS/SMBus
CONTROL
SCL
SDA
IO0_0
IO0_1
IO0_2
IO0_3
IO0_4
IO0_5
IO0_6
IO0_7
INPUT
FILTER
8−bit
INPUT/
OUTPUT
PORTS
write pulse
read pulse
V
DD
POWER−ON
RESET
V
SS
V
DD
LP filter
INT
Remark: All I/Os are set as inputs at reset.
Figure 1. Block Diagram
data from
output port
shift register
register data
configuration
register
V
DD
data from
shift register
Q1
D
Q
100 kW
FF
write
configuration
pulse
D
Q
CK
Q
FF
I/O pin
Q2
write pulse
read pulse
CK
V
input port
register
SS
output port
register
D
Q
input port
register data
FF
CK
to INT
polarity inversion
register
data from
shift register
polarity
inversion
register data
D
Q
FF
write polarity
pulse
CK
At power−on reset, all registers return to default values.
Figure 2. Simplified Schematic of I/Os
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2
PCA9655E
PIN ASSIGNMENT
terminal 1
index area
1
2
24
23
22
21
20
19
18
17
16
15
14
13
INT
AD1
V
DD
1
2
3
4
5
6
18
17
16
15
14
13
IO0_0
AD0
SDA
IO0_1
IO0_2
IO0_3
IO0_4
IO0_5
IO1_7
IO1_6
IO1_5
IO1_4
IO1_3
3
AD2
SCL
4
IO0_0
IO0_1
IO0_2
IO0_3
IO0_4
IO0_5
IO0_6
IO0_7
AD0
PCA9655E
5
IO1_7
IO1_6
IO1_5
IO1_4
IO1_3
IO1_2
IO1_1
IO1_0
6
PCA9655E
7
8
9
10
11
12
Transparent top view
V
SS
(The exposed thermal pad at the bottom
is not connected to internal circuitry)
Figure 4. WQFN24
Figure 3. SOIC24 / TSSOP24
Table 1. PIN DESCRIPTIONS
Pin
SOIC24, TSSOP24
WQFN24
Symbol
INT
Description
Interrupt Output (active−LOW)
Address Input 1
Address Input 2
Port 0 I/O 0
1
2
22
23
24
1
AD1
AD2
3
IO0_0
IO0_1
IO0_2
IO0_3
IO0_4
IO0_5
IO0_6
IO0_7
4
5
2
Port 0 I/O 1
6
3
Port 0 I/O 2
7
4
Port 0 I/O 3
9
5
Port 0 I/O 4
9
6
Port 0 I/O 5
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
7
Port 0 I/O 6
9
Port 0 I/O 7
V
SS
9
Supply Ground
Port 1 I/O 0
IO1_0
IO1_1
IO1_2
IO1_3
IO1_4
IO1_5
IO1_6
IO1_7
AD0
10
11
12
13
14
15
16
17
18
19
20
21
Port 1 I/O 1
Port 1 I/O 2
Port 1 I/O 3
Port 1 I/O 4
Port 1 I/O 5
Port 1 I/O 6
Port 1 I/O 7
Address Input 0
Serial Clock Line
Serial Data Line
Supply Voltage
SCL
SDA
V
DD
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3
PCA9655E
Table 2. MAXIMUM RATINGS
Symbol
Parameter
Value
−0.5 to +7.0
−0.5 to +7.0
$20
Unit
V
V
DD
DC Supply Voltage
V
Input / Output Pin Voltage
Input Current
V
I/O
I
mA
mA
mA
mA
mW
mW
°C
I
I
O
Output Current
$50
I
DC Supply Current
$100
DD
I
DC Ground Current
Total Power Dissipation
Power Dissipation per Output
Storage Temperature Range
$600
GND
P
600
TOT
OUT
STG
P
T
200
−65 to +150
260
T
Lead Temperature, 1 mm from Case for 10 Seconds
Junction Temperature Under Bias
°C
L
T
150
°C
J
q
Thermal Resistance (Note 1)
SOIC−24
TSSOP−24
WQFN24
85
91
68
°C/W
JA
MSL
Moisture Sensitivity
Level 1
F
R
Flammability Rating Oxygen Index: 28 to 34
UL 94 V−0 @ 0.125 in
V
ESD
ESD Withstand Voltage
Human Body Model (Note 2)
Machine Model (Note 3)
> 2000
> 200
V
I
Latchup Performance Above V and Below GND at 125°C (Note 4)
$300
mA
LATCHUP
DD
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
1. Measured with minimum pad spacing on an FR4 board, using 10 mm−by−1 inch, 2 ounce copper trace no air flow.
2. Tested to EIA / JESD22−A114−A.
3. Tested to EIA / JESD22−A115−A.
4. Tested to EIA / JESD78.
Table 3. RECOMMENDED OPERATING CONDITIONS
Symbol
Parameter
Min
1.65
0
Max
5.5
Unit
V
V
DD
Positive DC Supply Voltage
V
I/O
Switch Input / Output Voltage
Operating Free−Air Temperature
Input Transition Rise or Fall Rate
5.5
V
T
A
−55
0
+125
5
°C
Dt / DV
nS/V
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4
PCA9655E
Table 4. DC ELECTRICAL CHARACTERISTICS V = 1.65 V to 5.5 V, unless otherwise specified.
DD
T
= −555C to +1255C
A
Min
Typ
Max
Symbol
Parameter
Conditions
Unit
SUPPLIES
I
Standby Current
Standby mode; no load;
STB
V = 0 V; f
= 0 Hz; I/O = inputs
= 0 Hz; I/O = inputs
DD SCL
1.1
0.25
1.5
1
mA
mA
I
I
SCL
V = V ; f
V
POR
Power−On Reset Voltage
(Note 5)
1.5
1.65
V
INPUT SCL; Input / Output SDA
V
High−Level Input Voltage
Low−Level Input Voltage
Low−Level Output Current
0.7 x V
V
V
IH
DD
V
0.3 x V
IL
DD
I
OL
V
V
= 0.4 V; V < 2.3 V
10
20
mA
OL
DD
w 2.3 V
DD
DD
I
L
Leakage Current
Input Capacitance
V = V or 0 V
I
$1
6
mA
C
V = 0 V
I
4.6
pF
I
I/Os
V
High−Level Input Voltage
Low−Level Input Voltage
0.7 x V
V
V
IH
DD
V
0.3 x V
DD
IL
I
OL
Low−Level Output Current
(Note 6)
V
OL
V
OL
V
OL
V
OL
= 0.5 V; V = 1.65 V
8
20
28
35
42
mA
DD
= 0.5 V; V = 2.3 V
12
17
25
DD
= 0.5 V; V = 3.0 V
DD
= 0.5 V; V = 4.5 V
DD
I
Total Low−Level Output Current
V
= 0.5 V; V = 4.5 V
400
mA
V
OL(tot)
OL
DD
(Note 6)
V
OH
High−Level Output Voltage
I
I
I
I
I
I
I
I
= −3 mA; V = 1.65 V
1.2
1.1
1.8
1.7
2.6
2.5
4.1
4.0
OH
OH
OH
OH
OH
OH
OH
OH
DD
= −4 mA; V = 1.65 V
DD
= −8 mA; V = 2.3 V
DD
= −10 mA; V = 2.3 V
DD
= −8 mA; V = 3.0 V
DD
= −10 mA; V = 3.0 V
DD
= −8 mA; V = 4.5 V
DD
= −10 mA; V = 4.5 V
DD
I
Input Leakage Current
Input Leakage Current
V
= 5.5 V; V = V
DD
1
mA
mA
pF
LH
DD
DD
I
I
V
= 5.5 V; V = 0 V
−100
LL
I
C
Input / Output Capacitance
(Note 7)
5.0
5.0
6.0
I/O
INTERRUPT (INT)
I
OL
Low−Level Output Current
V
OL
= 0.4 V
6.0
mA
pF
C
Output Capacitance
5.5
O
INPUTS AD0, AD1, AD2
V
High−Level Input Voltage
Low−Level Input Voltage
Leakage Current
0.7 x V
V
V
IH
DD
V
I
0.3 x V
$1
IL
DD
V = V or 0 V
mA
pF
L
I
DD
C
Input Capacitance
4.5
5.0
I
2
5. The power−on reset circuit resets the I C bus logic with V < V
and set all I/Os to logic 1 upon power−up. Thereafter, V must be lower
DD
DD
POR
than 0.2 V to reset the part.
6. Each bit must be limited to a maximum of 25 mA and the total package limited to 400 mA due to internal bussing limits.
7. The value is not tested, but verified on sampling basis.
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5
PCA9655E
Table 5. AC ELECTRICAL CHARACTERISTICS V = 1.65 V to 5.5 V; T = −55°C to +125°C, unless otherwise specified.
DD
A
Standard
Mode
Fast Mode
Fast Mode +
Min
Max
Min
0
Max
Min
0
Max
Symbol
Parameter
SCL Clock Frequency
Unit
MHz
ms
f
0
0.1
0.4
1.0
SCL
t
Bus−Free Time between a STOP and START
Condition
4.7
1.3
0.5
BUF
t
Hold Time (Repeated) START Condition
4.0
4.7
0.6
0.6
0.26
0.26
ms
ms
HD:STA
t
Setup Time for a Repeated START Condition
SU:STA
t
Setup Time for STOP Condition
4.0
0.6
0.26
ms
SU:STO
t
Data Hold Time
0
0
0
ns
ms
ns
ns
ms
ms
ns
HD:DAT
t
Data Valid Acknowledge Time (Note 8)
Data Valid Time (Note 9)
Data Setup Time
0.3
300
250
4.7
4.0
3.45
0.1
50
0.9
0.05
50
0.45
450
VD:ACK
t
t
VD:DAT
100
1.3
0.6
50
SU:DAT
t
LOW Period of SCL
0.5
0.26
LOW
t
HIGH Period of SCL
HIGH
t
f
Fall Time of SDA and SCL (Notes 11 and 12)
300
1000
50
20 + 0.1C
(Note 10)
300
300
50
120
120
50
b
t
r
Rise Time of SDA and SCL
20 + 0.1C
(Note 10)
ns
ns
b
t
SP
Pulse Width of Spikes Suppressed by Input Filter
(Note 13)
PORT TIMING: C v 100 pF (See Figures 6, 9 and 10)
L
t
Data Output Valid Time
(V = 4.5 V to 5.5 V)
200
350
550
200
350
550
200
350
550
ns
V(Q)
DD
DD
(V = 2.3 V to 4.5 V)
(V = 1.65 V to 2.3 V)
DD
t
Data Input Setup Time
Data Input Hold Time
100
1
100
1
100
1
ns
SU(D)
t
ms
H(D)
INTERRUPT TIMING: C v 100 pF (See Figures 9 and 10)
V(INT_N)
L
t
Data Valid Time
4
4
4
4
4
4
ms
ms
t
Reset Delay Time
RST(INT_N)
8. t
9. t
= time for Acknowledgment signal from SCL LOW to SDA (out) LOW.
= minimum time for SDA data out to be valid following SCL LOW.
VD:ACK
VD:DAT
b
10.C = total capacitance of one bus line in pF.
11. A master device must internally provide a hold time of al least 300 ns for the SDA signal (refer to V of the SCL signal) in order to bridge
IL
the undefined region SCL’s falling edge.
12.The maximum t for the SDA and SCL bus lines is specified at 300 ns. The maximum fall time for the SDA output stage t is specified at 250 ns.
f
f
This allows series protection resistors to be connected between the SDA and the SCL pins and the SDA/SCL bus lines without exceeding
the maximum specified t .
f
13.Input filters on the SDA and SCL inputs suppress noise spikes less than 50 ns.
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6
PCA9655E
slave address
A3
Device Address
Before the bus master can access a slave device, it must
send the address of the slave it is accessing and the operation
it wants to perform (read or write) following a START
condition. The slave address of the PCA9655E is shown in
Figure 5. Address pins AD2, AD1, and AD0 choose 1 of 64
slave addresses. To conserve power, no internal pull−up
resistors are provided on AD2, AD1, and AD0.
A6
A5
A4
A2
A1
A0
R/W
programmable
Figure 5. PCA9655E device Address
A logic 1 on the last bit of the first byte selects a read
operation while a logic 0 selects a write operation.
Table 6. PCA9655E ADDRESS MAP
Address Input
Slave Address
AD2
GND
GND
GND
GND
VDD
VDD
VDD
VDD
GND
GND
GND
GND
VDD
VDD
VDD
VDD
GND
GND
GND
GND
VDD
VDD
VDD
VDD
GND
GND
GND
GND
VDD
VDD
VDD
VDD
AD1
SCL
SCL
SDA
SDA
SCL
SCL
SDA
SDA
SCL
SCL
SDA
SDA
SCL
SCL
SDA
SDA
GND
GND
VDD
VDD
GND
GND
VDD
VDD
GND
GND
VDD
VDD
GND
GND
VDD
VDD
AD0
GND
VDD
GND
VDD
GND
VDD
GND
VDD
SCL
SDA
SCL
SDA
SCL
SDA
SCL
SDA
GND
VDD
GND
VDD
GND
VDD
GND
VDD
SCL
SDA
SCL
SDA
SCL
SDA
SCL
SDA
A6
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
A5
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
A4
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
A3
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
A2
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
A1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
A0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
HEX
20h
22h
24h
26h
28h
2Ah
2Ch
2Eh
30h
32h
34h
36h
38h
3Ah
3Ch
3Eh
40h
42h
44h
46h
48h
4Ah
4Ch
4Eh
50h
52h
54h
56h
58h
5Ah
5Ch
5Eh
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7
PCA9655E
Table 6. PCA9655E ADDRESS MAP
Address Input
Slave Address
AD2
SCL
SCL
SCL
SCL
SDA
SDA
SDA
SDA
SCL
SCL
SCL
SCL
SDA
SDA
SDA
SDA
SCL
SCL
SCL
SCL
SDA
SDA
SDA
SDA
SCL
SCL
SCL
SCL
SDA
SDA
SDA
SDA
AD1
SCL
SCL
SDA
SDA
SCL
SCL
SDA
SDA
SCL
SCL
SDA
SDA
SCL
SCL
SDA
SDA
GND
GND
VDD
VDD
GND
GND
VDD
VDD
GND
GND
VDD
VDD
GND
GND
VDD
VDD
AD0
GND
VDD
GND
VDD
GND
VDD
GND
VDD
SCL
SDA
SCL
SDA
SCL
SDA
SCL
SDA
GND
VDD
GND
VDD
GND
VDD
GND
VDD
SCL
SDA
SCL
SDA
SCL
SDA
SCL
SDA
A6
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
A5
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
A4
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
A3
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
A2
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
A1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
A0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
HEX
A0h
A2h
A4h
A6h
A8h
AAh
ACh
AEh
B0h
B2h
B4h
B6h
B8h
BAh
BCh
BEh
C0h
C2h
C4h
C6h
C8h
CAh
CCh
CEh
E0h
E2h
E4h
E6h
E8h
EAh
ECh
EEh
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8
PCA9655E
REGISTERS
Command Byte
During a write transmission, the address byte is followed
by the command byte. The command byte determines which
of the following registers will be written or read.
Table 7. COMMAND BYTE
COMMAND
REGISTER
0
1
2
3
4
5
6
7
Input Port 0
Input Port 1
Output Port 0
Output Port 1
Polarity Inversion Port 0
Polarity Inversion Port 1
Configuration Port 0
Configuration Port 1
Registers 0 and 1: Input Port Registers
The externally−applied logic level determines the default
These registers are input−only. They reflect the incoming
logic levels of the pins, regardless of whether the pin is
defined as an input or an output by Registers 6 or 7. Writes
to these registers have no effect.
value ‘X’.
Table 8. INPUT PORT 0 REGISTER
Bit
Symbol
Default
7
I0.7
X
6
I0.6
X
5
I0.5
X
4
I0.4
X
3
I0.3
X
2
I0.2
X
1
I0.1
X
0
I0.0
X
Table 9. INPUT PORT 1 REGISTER
Bit
Symbol
Default
7
I1.7
X
6
I1.6
X
5
I1.5
X
4
I1.4
X
3
I1.3
X
2
I1.2
X
1
I1.1
X
0
I1.0
X
Registers 2 and 3: Output Port Registers
as inputs. In turn, reads from these registers reflect the values
that are in the flip−flops controlling the output selection, not
the actual pin values.
These registers are output−only. They reflect the outgoing
logic levels of the pins defined as outputs by Registers 6 and
7. Bit values in these registers have no effect on pins defined
Table 10. OUTPUT PORT 0 REGISTER
Bit
Symbol
Default
7
O0.7
1
6
O0.6
1
5
O0.5
1
4
O0.4
1
3
O0.3
1
2
O0.2
1
1
O0.1
1
0
O0.0
1
Table 11. OUTPUT PORT 1 REGISTER
Bit
Symbol
Default
7
O1.7
1
6
O1.6
1
5
O1.5
1
4
O1.4
1
3
O1.3
1
2
O1.2
1
1
O1.1
1
0
O1.0
1
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9
PCA9655E
Registers 4 and 5: Polarity Inversion Registers
These registers allow the polarity of the data in the input
port registers to be inverted. The input port data polarity will
be inverted when its corresponding bit in these registers is
set (written with ‘1’), and retained when the bit is cleared
(written with a ‘0’).
Table 12. POLARITY INVERSION PORT 0 REGISTER
Bit
Symbol
Default
7
N0.7
0
6
N0.6
0
5
N0.5
0
4
N0.4
0
3
N0.3
0
2
N0.2
0
1
N0.1
0
0
N0.0
0
Table 13. POLARITY INVERSION PORT 1 REGISTER
Bit
Symbol
Default
7
N1.7
0
6
N1.6
0
5
N1.5
0
4
N1.4
0
3
N1.3
0
2
N1.2
0
1
N1.1
0
0
N1.0
0
Registers 6 and 7: Configuration Registers
high−impedance. When a bit is cleared (written with ‘0’),
The I/O pin directions are configured through the
configuration registers. When a bit in the configuration
registers is set (written with ‘1’), the bit’s corresponding port
pin is enabled as an input with the output driver in
the corresponding port pin is enabled as an output. Note that
there is a high value resistor tied to V at each pin. At reset,
DD
the device’s ports are inputs with a pull−up to V
.
DD
Table 14. CONFIGURATION PORT 0 REGISTER
Bit
Symbol
Default
7
C0.7
1
6
C0.6
1
5
C0.5
1
4
C0.4
1
3
C0.3
1
2
C0.2
1
1
C0.1
1
0
C0.0
1
Table 15. CONFIGURATION PORT 1 REGISTER
Bit
Symbol
Default
7
C1.7
1
6
C1.6
1
5
C1.5
1
4
C1.4
1
3
C1.3
1
2
C1.2
1
1
C1.1
1
0
C1.0
1
Power−on Reset
I/O Port (see Figure 2)
Upon application of power, an internal Power−On Reset
(POR) holds the PCA9655E in a reset condition while V
When an I/O pin is configured as an input, FETs Q1 and
Q2 are off, creating a high−impedance input with a weak
DD
is ramping up. When V has reached V
, the reset
POR
pull−up (100 kW typ) to V . The input voltage may be
DD
DD
condition is released and the PCA9655E registers and
SMBus state machine will initialize to their default states.
The reset is typically completed by the POR and the part
raised above V to a maximum of 5.5 V.
DD
When the I/O pin is configured as an output, then either Q1
or Q2 is enabled, depending on the state of the Output Port
register. Care should be exercised if an external voltage is
applied to an I/O configured as an output because of the
low−impedance path that exists between the pin and either
enabled by the time the power supply is above V
.
POR
However, when doing a power reset cycle, it is necessary to
lower the power supply below 0.2 V, and then restored to the
operating voltage.
V
DD
or V .
SS
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10
PCA9655E
BUS TRANSACTIONS
Writing to the Port Registers
Input Ports, Output Ports, Polarity Inversion Ports, and
Configuration Ports. Data bytes are sent alternately to each
register in a register pair (see Figures 6 and 7). For example,
if one byte is sent to Output Port 1 (register 3), then the next
byte will be stored in Output Port 0 (register 2). There is no
limitation on the number of data bytes sent in one write
transmission. In this way, each 8−bit register may be updated
independently of the other registers.
To transmit data to the PCA9655E, the bus master must
first send the device address with the least significant bit set
to logic 0 (see Figure 5 “PCA9655E device address”). The
command byte is sent after the address and determines
which registers will receive the data following the command
byte.
There are eight registers within the PCA9655E. These
registers are configured to operate as four register pairs:
SCL
1
2
3
4
5
6
7
8
9
slave address
A6 A5 A4 A3 A2 A1 A0
START condition
command byte
data to port 0
DATA 0
data to port 1
DATA 1
SDA
S
0
A
0
0
0
0
0
0
1
0
A
0.7
0.0 A 1.7
1.0 A
P
R/W acknowledge
from slave
acknowledge
from slave
acknowledge
from slave
STOP
condition
write to port
t
v(Q)
data out
from port 0
t
v(Q)
data out
DATA VALID
from port 1
Figure 6. Write to Output Port Registers
SCL
SDA
1
2
3
4
5
6
7
8
9
data to register
data to register
slave address
A6 A5 A4 A3 A2 A1 A0
command byte
MSB
LSB
MSB
LSB
S
0
A
0
0
0
0
0
1
1
0
A
DATA 0
A
DATA 1
A
P
START condition
acknowledge
from slave
acknowledge
from slave
acknowledge
from slave
STOP
condition
R/W
Figure 7. Write to Configuration Registers
Reading the Port Registers
by the PCA9655E (see Figures 8, 9 and 10). Data is clocked
into the register on the falling edge of the acknowledge clock
pulse. After the first byte is read, additional bytes may be
read but with data alternately coming from each register in
the pair. For example, if you read Input Port 1, then the next
byte read would be Input Port 0. There is no limitation on the
number of data bytes received in one read transmission but
the bus master must not acknowledge the data for the final
byte received.
To read data from the PCA9655E, the bus master must
first send the PCA9655E address with the least significant
bit set to logic 0 (see Figure 5 “PCA9655E device address”).
The command byte is sent after the address and determines
which register will be accessed.
After a restart, the device address must be sent again, but
this time, the least significant bit is set to logic 1. Data from
the register defined by the command byte will then be sent
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11
PCA9655E
slave address
(cont.)
SDA
S
A6 A5 A4 A3 A2 A1 A0
0
A
COMMAND BYTE
A
START condition
R/W
acknowledge
from slave
acknowledge
from slave
data from lower or
upper byte of register
data from upper or
lower byte of register
slave address
A6 A5 A4 A3 A2 A1 A0
MSB
LSB
MSB
LSB
(cont.)
S
1
A
DATA (first byte)
A
DATA (last byte)
NA P
(repeated)
START condition
acknowledge
from master
STOP
condition
R/W
no acknowledge
from master
acknowledge
from slave
at this moment master−transmitter becomes master−receiver
and slave−receiver becomes slave−transmitter
Remark: Transfer can be stopped at any time by a STOP condition.
Figure 8. Read from Register
SCL
1 2 3 4 5 6 7 8 9
STOP condition
slave address
SDA S A6 A5 A4 A3 A2 A1 A0 1
I0.x
I1.x
I0.x
I1.x
A
7 6 5 4 3 2 1 0 A 7 6 5 4 3 2 1 0 A 7 6 5 4 3 2 1 0 A 7 6 5 4 3 2 1 0 1 P
acknowledge
from master
START condition
R/W
acknowledge
acknowledge
from master
acknowledge
from master
non acknowledge
from master
from slave
read from port 0
data into port 0
read from port 1
data into port 1
INT
t
t
rst(INT_N)
v(INT_N)
Remark: Transfer of data can be stopped at any moment by a STOP condition. When this occurs, data present at the latest acknowledge
phase is valid (output mode). It is assumed that the command byte has previously been set to ’00’ (read Input Port register).
Figure 9. Read from Input Port Register, Scenario 1
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12
PCA9655E
SCL
1 2 3 4 5 6 7 8 9
R/W
STOP condition
slave address
SDA S A6 A5A4 A3 A2 A1 A0 1
I0.x
I1.x
I0.x
I1.x
A
DATA00
A
DATA10
A
DATA03
A
DATA12
1 P
START condition acknowledge
from slave
acknowledge
from master
t
su(D)
non acknowledge
from master
acknowledge
from master
acknowledge
from master
t
h(D)
read from port 0
data into port 0
read from port 1
data into port 1
DATA 00
DATA 01
DATA 02
DATA 03
t
t
su(D)
h(D)
DATA10
DATA11
DATA12
INT
t
t
rst(INT_N)
v(INT_N)
Remark: Transfer of data can be stopped at any moment by a STOP condition. When this occurs, data present at the latest acknowledge
phase is valid (output mode). It is assumed that the command byte has previously been set to ’00’ (read Input Port register).
Figure 10. Read from Input Port Register, Scenario 2
Interrupt Output
each 8−bit port is read independently, the interrupt caused by
Port 0 will not be cleared by a read of Port 1 or the other way
around.
The open−drain interrupt output is activated when an I/O
pin configured as an input changes state. The interrupt is
deactivated when the input pin returns to its previous state
or when the Input Port register is read (see Figure 9). A pin
configured as an output cannot cause an interrupt. Since
Remark: Changing an I/O from an output to an input may
cause a false interrupt to occur if the state of the pin does not
match the contents of the Input Port register.
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13
PCA9655E
APPLICATION INFORMATION
V
DD
(5 V)
SUB−SYSTEM 1
sensor)
10 kW
10 kW
10 kW
2 kW
(e.g., temp
V
V
DD
DD
INT
MASTER
CONTROLLER
PCA9655E
SCL
IO0_0
IO0_1
IO0_2
IO0_3
IO0_4
IO0_5
SCL
SUB−SYSTEM 2
counter)
(e.g.,
SDA
INT
SDA
INT
RESET
A
B
GND
controlled
switch
ENABLE
(e.g.,
7SB or FST)
IO0_6
IO0_7
IO1_0
IO1_1
IO1_2
IO1_3
IO1_4
IO1_5
IO1_6
IO1_7
SUB−SYSTEM 3
system)
(e.g., alarm
10
DIGIT
ALARM
NUMERIC
KEYPAD
AD2
AD1
AD0
V
DD
V
SS
Device address configured as 0100 000xb for this example.
IO0_0, IO0_2, IO0_3 configured as outputs.
IO0_1, IO0_4, IO0_5 configured as inputs.
IO0_6, IO0_7, and IO1_0 to IO1_7 configured as inputs.
Figure 11. Typical Application
Bit Transfer
Characteristics of the I2C−Bus
2
The I C−bus is meant for 2−way, 2−line communication
between different ICs or modules. The two lines are the
serial data line (SDA) and the serial clock line (SCL). Both
lines must be connected to a positive supply via a pull−up
resistor when connected to the output stages of a device.
Data transfer may only be initiated when the bus is not busy.
One data bit is transferred during each clock pulse. The
data on the SDA line must remain stable during the HIGH
period of the clock pulse. Changes in the data line during the
HIGH period of the clock pulse will be interpreted as control
signals (see Figure 12).
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14
PCA9655E
SDA
SCL
data line
stable;
data valid
change
of data
allowed
Figure 12. Bit Transfer
START and STOP Conditions
HIGH. A STOP condition (P) occurs when there is a
LOW−to−HIGHtransition of the data line while the clock is
HIGH (see Figure 13).
Both data and clock lines remain HIGH when the bus is
not busy. A START condition (S) occurs when there is a
HIGH−to−LOWtransition of the data line while the clock is
SDA
SDA
SCL
SCL
S
P
STOP condition
START condition
Figure 13. Definition of START and STOP Conditions
System Configuration
A device generating a message is a ‘transmitter’; a device
receiving is the ‘receiver’. The device that controls the
message is the ‘master’ and the devices which are controlled
by the master are the ‘slaves’ (see Figure 14).
SDA
SCL
SLAVE
TRANSMITTER/
RECEIVER
MASTER
2
MASTER
TRANSMITTER/
RECEIVER
SLAVE
RECEIVER
MASTER
TRANSMITTER
I C−BUS
TRANSMITTER/
RECEIVER
MULTIPLEXER
SLAVE
Figure 14. System Configuration
Acknowledge
device that acknowledges has to pull down the SDA line
during the acknowledge clock pulse, such that the SDA line
is stable LOW during the HIGH period of the acknowledge
clock pulse; set−up time and hold time must be taken into
account.
A master receiver signals an end of data to the transmitter
by not generating an acknowledge on the last byte that has
been clocked out of the slave. In this event, the transmitter
must leave the data line HIGH to enable the master to
generate a STOP condition.
The number of data bytes transferred between the START
and the STOP conditions from transmitter to receiver is not
limited. Each 8−bit byte is followed by one acknowledge bit.
The acknowledge bit is a HIGH level put on the bus by the
transmitter, whereas the master generates an extra clock
pulse for the acknowledge bit.
A slave receiver which is addressed must generate an
acknowledge after the reception of each byte. Also, a master
must generate an acknowledge after the reception of each
byte that has been clocked out of the slave transmitter. The
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15
PCA9655E
data output
by transmitter
not acknowledge
data output
by receiver
acknowledge
8
SCL from master
1
2
9
S
clock pulse for
START
acknowledgement
condition
Figure 15. Acknowledgement of the I2C Bus
TIMING AND TEST SETUP
SDA
SCL
t
t
t
t
SP
t
r
f
HD;STA
BUF
t
LOW
t
t
t
SU;STO
HD;STA
SU;STA
t
t
t
SU;DAT
HD;DAT
HIGH
P
S
Sr
P
Figure 16. Definition of Timing on the I2C Bus
V
DD
open
GND
V
R
500 W
DD
L
V
I
V
O
PULSE
DUT
GENERATOR
C
50 pF
L
R
T
R = load resistor.
L
C = load capacitance includes jig and probe capacitance.
L
R = termination resistance should be equal to the output impedance of Z of the pulse generators.
T
o
Figure 17. Test Circuitry for Switching Times
R
2V
open
GND
S1
L
DD
from output under test
500 W
C
50 pF
R
L
500 W
L
Figure 18. Load Circuit
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16
PCA9655E
ORDERING INFORMATION
Device
†
Package
Shipping
PCA9655EDWR2G
SOIC−24
(Pb−Free)
1000 / Tape & Reel
2500 / Tape & Reel
3000 / Tape & Reel
PCA9655EDTR2G
PCA9655EMTTXG
TSSOP−24
(Pb−Free)
WQFN24
(Pb−Free)
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
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17
PCA9655E
PACKAGE DIMENSIONS
SOIC−24
CASE 751E−04
ISSUE E
−A−
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
24
13
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS A AND B DO NOT INCLUDE
MOLD PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.
−B− 12X P
M
M
B
0.010 (0.25)
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.13 (0.005) TOTAL IN
EXCESS OF D DIMENSION AT MAXIMUM
MATERIAL CONDITION.
1
12
24X D
J
MILLIMETERS
INCHES
MIN
0.601
M
S
S
0.010 (0.25)
T A
B
DIM MIN
MAX
MAX
0.612
0.299
0.104
0.019
0.035
A
B
C
D
F
15.25
7.40
2.35
0.35
0.41
15.54
7.60 0.292
2.65 0.093
0.49 0.014
0.90 0.016
F
R X 45
_
G
J
1.27 BSC
0.050 BSC
0.23
0.13
0
0.32 0.009
0.29 0.005
0.013
0.011
8
C
K
K
M
P
R
−T−
SEATING
PLANE
8
10.55
0
0.395
_
_
_
_
M
10.05
0.25
0.415
0.029
0.75 0.010
22X G
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18
PCA9655E
PACKAGE DIMENSIONS
24 LEAD TSSOP
CASE 948H
ISSUE A
24X KREF
M
S
S
V
0.10 (0.004)
T U
S
0.15 (0.006) T U
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
24
13
2X L/2
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A DOES NOT INCLUDE MOLD FLASH,
PROTRUSIONS OR GATE BURRS. MOLD FLASH
OR GATE BURRS SHALL NOT EXCEED 0.15
(0.006) PER SIDE.
4. DIMENSION B DOES NOT INCLUDE INTERLEAD
FLASH OR PROTRUSION. INTERLEAD FLASH OR
PROTRUSION SHALL NOT EXCEED
0.25 (0.010) PER SIDE.
B
−U−
L
PIN 1
IDENT.
12
1
5. DIMENSION K DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN
EXCESS OF THE K DIMENSION AT MAXIMUM
MATERIAL CONDITION.
S
0.15 (0.006) T U
A
−V−
6. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
7. DIMENSION A AND B ARE TO BE DETERMINED
AT DATUM PLANE -W-.
MILLIMETERS
INCHES
MIN
DIM MIN
MAX
7.90
4.50
1.20
0.15
0.75
MAX
0.311
0.177
0.047
0.006
0.030
C
A
B
7.70
4.30
---
0.303
0.169
---
C
0.10 (0.004)
D
0.05
0.50
0.002
0.020
SEATING
PLANE
−T−
G
F
H
D
G
H
0.65 BSC
0.026 BSC
0.27
0.09
0.09
0.19
0.19
0.37
0.20
0.16
0.30
0.25
0.011
0.004
0.004
0.007
0.007
0.015
0.008
0.006
0.012
0.010
J
J1
K
−W−
K1
L
6.40 BSC
_
0.252 BSC
0
M
0
8
8
_
_
_
DETAIL E
N
0.25 (0.010)
K
K1
M
N
J1
F
SECTION N−N
DETAIL E
J
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19
PCA9655E
PACKAGE DIMENSIONS
WQFN24 4x4, 0.5P
CASE 485BG
ISSUE A
NOTES:
1. DIMENSIONING AND TOLERANCING PER ASME
Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS.
3. DIMENSION b APPLIES TO PLATED TERMINAL
AND IS MEASURED BETWEEN 0.15 AND 0.30 MM
FROM TERMINAL TIP.
B
E
A
D
L
L
PIN ONE
REFERENCE
L1
4. COPLANARITY APPLIES TO THE EXPOSED PAD
AS WELL AS THE TERMINALS.
DETAIL A
MILLIMETERS
ALTERNATE TERMINAL
CONSTRUCTIONS
DIM MIN
MAX
0.80
0.05
A
A1
A3
b
0.70
0.00
0.20 REF
EXPOSED Cu
MOLD CMPD
0.20
0.30
D
D2
E
E2
e
K
4.00 BSC
0.15
0.15
C
2.00
2.20
4.00 BSC
C
2.00
2.20
TOP VIEW
DETAIL B
0.50 BSC
ALTERNATE
0.20
0.30
0.00
−−−
0.50
0.15
A
0.10
C
C
CONSTRUCTION
L
L1
A3
0.08
DETAIL B
NOTE 4
A1
K
SEATING
PLANE
SIDE VIEW
C
MOUNTING FOOTPRINT*
4.30
2.26
DETAIL A
24X
0.63
D2
7
1
13
24X L
E2
2.26
4.30
1
PACKAGE
OUTLINE
19
24X
0.30
24X
b
0.50
PITCH
e
0.10 C A B
DIMENSIONS: MILLIMETERS
e/2
BOTTOM VIEW
0.05
C
NOTE 3
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
ON Semiconductor and
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All
operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights
nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications
intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should
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PCA9655E/D
相关型号：
PCA9665APW
IC I2C BUS CONTROLLER, PDSO20, 4.40 MM, PLASTIC, MO-153, SOT360-1, TSSOP-20, Bus Controller
NXP
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