RFD14N05SM9A [ONSEMI]
N 沟道，功率 MOSFET，50V，14A，100mΩ;
| 型号： | RFD14N05SM9A |
| 厂家： | 
ONSEMI |
| 描述： | N 沟道，功率 MOSFET，50V，14A，100mΩ 开关 晶体管 |
| 文件： | 总10页 (文件大小：761K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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RFD14N05SM9A
September 2013
Data Sheet
N-Channel Power MOSFET
Features
50V, 14A, 100 mΩ
• 14A, 50V
• r = 0.100Ω
These are N-channel power MOSFETs manufactured using
the MegaFET process. This process, which uses feature
sizes approaching those of LSI integrated circuits, gives
optimum utilization of silicon, resulting in outstanding
performance. They were designed for use in applications
such as switching regulators, switching converters, motor
drivers and relay drivers. These transistors can be operated
directly from integrated circuits.
DS(ON)
®
• Temperature Compensating PSPICE Model
• Peak Current vs Pulse Width Curve
• UIS Rating Curve
o
• 175 C Operating Temperature
• Related Literature
Formerly developmental type TA09770.
- TB334 “Guidelines for Soldering Surface Mount
Components to PC Boards”
Ordering Information
Symbol
PART NUMBER
PACKAGE
BRAND
F14N05
D
RFD14N05SM9A
TO-252AA
G
S
Packaging
JEDEC TO-252AA
DRAIN (FLANGE)
GATE
SOURCE
©2004 Fairchild Semiconductor Corporation
RFD14N05SM9A Rev. C1
RFD14N05SM9A
o
Absolute Maximum Ratings
T = 25 C, Unless Otherwise Specified
C
RFD14N05SM9A
UNITS
Drain to Source Voltage (Note 1). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . V
50
50
±20
14
V
V
V
A
DSS
DGR
Drain to Gate Voltage (R
= 20kΩ) (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . V
GS
Gate to Source Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . V
Continuous Drain Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I
GS
D
Pulsed Drain Current (Note 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .I
Refer to Peak Current Curve
DM
Pulsed Avalanche Rating. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . E
Refer to UIS Curve
AS
Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . P
Derate above 25 C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
48
0.32
-55 to 175
W
D
o
o
W/ C
o
Operating and Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . T
Maximum Temperature for Soldering
T
C
J, STG
o
Leads at 0.063in (1.6mm) from Case for 10s. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .T
300
260
C
L
o
Package Body for 10s, See Techbrief 334 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . T
C
pkg
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE:
o
o
1. T = 25 C to 150 C.
J
o
Electrical Specifications
T = 25 C, Unless Otherwise Specified
C
PARAMETER
Drain to Source Breakdown Voltage
Gate Threshold Voltage
SYMBOL
BV
TEST CONDITIONS
= 0V (Figure 9)
MIN
TYP
MAX
-
UNITS
V
I
= 250µA, V
50
2
-
-
-
DSS
GS(TH)
D
GS
V
V
V
V
V
= V , I = 250µA
4
V
GS
DS
DS
GS
DS
D
Zero Gate Voltage Drain Current
I
= Rated BV
, V
= 0V
, V
-
25
250
±100
0.100
60
-
µA
µA
nA
Ω
DSS
DSS GS
o
= 0.8 x Rated BV
= 0V, T = 150 C
-
-
DSS GS
C
Gate to Source Leakage Current
I
= ±2 0V
-
-
GSS
Drain to Source On Resistance (Note 2)
Turn-On Time
r
I
= 14A, V
= 10V, (Figure 11)
-
-
DS(ON)
D
GS
= 25V, I ≈ 14A, V = 10V,
GS
t
V
-
-
ns
ON
DD
D
R
= 25Ω, R = 1.7Ω
GS
(Figure 13)
L
Turn-On Delay Time
Rise Time
t
-
14
26
45
17
-
ns
d(ON)
t
-
-
ns
r
Turn-Off Delay Time
Fall Time
t
-
-
ns
d(OFF)
t
-
-
ns
f
Turn-Off Time
t
-
100
40
25
1.5
ns
OFF
Total Gate Charge
Gate Charge at 5V
Threshold Gate Charge
Q
V
V
V
= 0V to 20V
= 0V to 10V
= 0V to 2V
V
R
= 40V, I = 14A,
= 2.86Ω
-
-
nC
nC
nC
g(TOT)
GS
GS
GS
DD
D
L
Q
-
-
g(10)
I
= 0.4mA
g(REF)
Q
-
-
(Figure 13)
= 25V, V = 0V, f = 1MHz
GS
g(TH)
Input Capacitance
C
V
-
-
-
-
-
570
185
50
-
-
pF
pF
pF
ISS
OSS
RSS
DS
(Figure 12)
Output Capacitance
C
C
-
-
Reverse Transfer Capacitance
Thermal Resistance Junction to Case
Thermal Resistance Junction to Ambient
o
R
3.125
100
C/W
θJC
θJA
o
R
-
C/W
Source to Drain Diode Specifications
PARAMETER
Source to Drain Diode Voltage (Note 2)
Diode Reverse Recovery Time
NOTES:
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
1.5
UNITS
V
I
I
= 14A
-
-
-
-
V
SD
SD
t
= 14A, dI /dt = 100A/µs
SD
125
ns
rr
SD
2. Pulse Test: Pulse Width ≤300ms, Duty Cycle ≤2%.
3. Repetitive Rating: Pulse Width limited by max junction temperature. See Transient Thermal Impedance Curve (Figure 3) and Peak Current
Capability Curve (Figure 5).
©2004 Fairchild Semiconductor Corporation
RFD14N05SM9A Rev. C1
RFD14N05SM9A
Typical Performance Curves Unless Otherwise Specified
1.2
1.0
0.8
0.6
0.4
0.2
0
16
12
8
4
0
125
o
0
25
50
75
100
175
150
25
50
75
T , CASE TEMPERATURE ( C)
C
100
125
150
175
o
T
, CASE TEMPERATURE ( C)
C
FIGURE 1. NORMALIZED POWER DISSIPATION vs CASE
TEMPERATURE
FIGURE 2. MAXIMUM CONTINUOUS DRAIN CURRENT vs
CASE TEMPERATURE
1
0.5
0.2
P
DM
0.1
0.1
0.05
t
t
1
2
0.02
0.01
NOTES:
DUTY FACTOR: D = t /t
1 2
SINGLE PULSE
PEAK T = P
x Z
x R
+ T
JA A
J
DM
JA
θ
θ
0.01
-5
-4
-3
-2
10
-1
10
0
1
10
10
10
10
10
t, RECTANGULAR PULSE DURATION (s)
FIGURE 3. NORMALIZED MAXIMUM TRANSIENT THERMAL IMPEDANCE
100
T
= MAX RATED
J
FOR TEMPERATURES
ABOVE 25 C DERATE PEAK
CURRENT AS FOLLOWS:
o
SINGLE PULSE
T
V
= 20V
GS
o
= 25 C
C
100
V
= 10V
GS
175 – T
C
I = I
---------------------
25
150
100µs
10
OPERATION IN THIS
AREA MAY BE
1ms
LIMITED BY r
DS(ON)
TRANSCONDUCTANCE
MAY LIMIT CURRENT
IN THIS REGION
10ms
DC
100ms
1
10
10
, DRAIN TO SOURCE VOLTAGE (V)
1
100
-5
10
-4
-3
-2
-1
10
0
1
10
10
10
10
10
V
DS
t, PULSE WIDTH (s)
FIGURE 4. FORWARD BIAS SAFE OPERATING AREA
FIGURE 5. PEAK CURRENT CAPABILITY
©2004 Fairchild Semiconductor Corporation
RFD14N05SM9A Rev. C1
RFD14N05SM9A
Typical Performance Curves Unless Otherwise Specified (Continued)
50
35
o
T
= 25 C
V
= 20V
GS
C
V
= 10V
= 8V
GS
30
25
20
15
10
5
V
GS
V
= 7V
= 6V
GS
o
STARTING T = 25 C
J
PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX
10
V
GS
o
STARTING T = 150 C
J
If R = 0
AV
If R ≠ 0
V
= 5V
t
= (L)(I )/(1.3*RATED BV
- V
)
DD
GS
AS DSS
V
= 4.5V
GS
t
= (L/R)ln[(I *R)/(1.3*RATED BV -V ) +1]
DSS DD
AV
AS
1
0.01
0
2
0
4
6
8
0.1
1
10
t
, TIME IN AVALANCHE (ms)
V
, DRAIN TO SOURCE VOLTAGE (V)
DS
AV
NOTE: Refer to Fairchild Application Notes AN9321 and AN9322.
FIGURE 6. UNCLAMPED INDUCTIVE SWITCHING
FIGURE 7. SATURATION CHARACTERISTICS
35
2.0
PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX
I
= 250µA
o
D
-25 C
30
V
= 15V
DD
o
o
-55 C
175 C
1.5
1.0
0.5
0
25
20
15
10
5
0
-80
-40
0
40
80
120
160
200
0
2
4
6
8
10
o
V
, GATE TO SOURCE VOLTAGE (V)
T , JUNCTION TEMPERATURE ( C)
GS
J
FIGURE 8. TRANSFER CHARACTERISTICS
FIGURE 9. NORMALIZED DRAIN TO SOURCE BREAKDOWN
VOLTAGE vs JUNCTION TEMPERATURE
2.5
2.0
1.5
PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX
V
= V , I = 250µA
DS
GS
D
V
= 10V, ID = 14A
GS
2.0
1.5
1.0
0.5
0
1.0
0.5
0
-80
-40
0
40
80
120
160
200
-80
-40
0
40
80
120
o
160
200
o
T , JUNCTION TEMPERATURE ( C)
T , JUNCTION TEMPERATURE ( C)
J
J
FIGURE 10. NORMALIZED GATE THRESHOLD VOLTAGE vs
JUNCTION TEMPERATURE
FIGURE 11. NORMALIZED DRAIN TO SOURCE ON
RESISTANCE vs JUNCTION TEMPERATURE
©2004 Fairchild Semiconductor Corporation
RFD14N05SM9A Rev. C1
RFD14N05SM9A
Typical Performance Curves Unless Otherwise Specified (Continued)
60
10
700
V
= BV
V = BV
DD DSS
DD
DSS
C
ISS
600
500
400
300
200
45
30
7.5
5.0
V
= 0V, f = 1MHz
GS
C
C
C
= C
+ C
ISS
GS
= C
GD
RSS
OSS
GD
C
C
0.75 BV
0.50 BV
0.25 BV
OSS
RSS
DSS
DSS
DSS
≈
C
+ C
DS
GD
15
0
2.5
0
R
= 3.57Ω
L
I
= 0.4mA
G(REF)
V
= 10V
GS
100
0
I
I
G(REF)
G(REF)
---------------------
t, TIME (µs)
---------------------
20
80
I
I
G(ACT)
G(ACT)
0
5
10
15
20
25
V
, DRAIN TO SOURCE VOLTAGE (V)
DS
NOTE: Refer to Fairchild Application Notes AN7254 and AN7260,
FIGURE 13. NORMALIZED SWITCHING WAVEFORMS FOR
CONSTANT CURRENT GATE DRIVE
FIGURE 12. CAPACITANCE vs DRAIN TO SOURCE VOLTAGE
Test Circuits and Waveforms
V
DS
BV
DSS
L
t
P
V
DS
I
VARY t TO OBTAIN
P
AS
+
-
V
DD
R
REQUIRED PEAK I
G
AS
V
DD
V
GS
DUT
t
P
I
AS
0V
0
0.01Ω
t
AV
FIGURE 14. UNCLAMPED ENERGY TEST CIRCUIT
FIGURE 15. UNCLAMPED ENERGY WAVEFORMS
t
t
ON
OFF
t
d(OFF)
t
d(ON)
V
DS
t
t
f
r
V
DS
90%
90%
R
L
V
GS
+
10%
10%
0
0
V
DD
-
DUT
90%
50%
R
GS
V
GS
50%
PULSE WIDTH
10%
V
GS
FIGURE 16. SWITCHING TIME TEST CIRCUIT
FIGURE 17. RESISTIVE SWITCHING WAVEFORMS
©2004 Fairchild Semiconductor Corporation
RFD14N05SM9A Rev. C1
RFD14N05SM9A
Test Circuits and Waveforms (Continued)
V
DS
V
Q
DD
g(TOT)
R
L
V
DS
V
= 20V
GS
Q
g(10)
V
GS
+
-
V
V
= 10V
DD
V
GS
GS
V
= 2V
GS
DUT
0
I
G(REF)
Q
g(TH)
I
G(REF)
0
FIGURE 18. GATE CHARGE TEST CIRCUIT
FIGURE 19. GATE CHARGE WAVEFORMS
©2004 Fairchild Semiconductor Corporation
RFD14N05SM9A Rev. C1
RFD14N05SM9A
PSPICE Electrical Model
.SUBCKT RFD14N05 2 1 3 ;
rev 9/12/94
CA 12 8 8.84e-10
CB 15 14 9.34e-10
CIN 6 8 5.2e-10
DPLCAP
5
5
DRAIN
2
10
LDRAIN
DBODY 7 5 DBDMOD
DBREAK 5 11 DBKMOD
DPLCAP 10 5 DPLCAPMOD
RSCL1
DBREAK
RSCL2
51
+
EBREAK 11 7 17 18 62.87
EDS 14 8 5 8 1
EGS 13 8 6 8 1
ESG 6 10 6 8 1
EVTO 20 6 18 8 1
ESCL
51
-
50
+
DBODY
6
8
11
RDRAIN
ESG
17
18
16
EBREAK
+
VTO
+
-
MOS2
EVTO
GATE
1
21
IT 8 17 1
+
-
6
9
20
18
8
MOS1
8
LGATE RGATE
LDRAIN 2 5 1e-9
LGATE 1 9 4.34e-9
LSOURCE 3 7 3.79e-9
RIN
CIN
LSOURCE
RSOURCE
7
3
SOURCE
MOS1 16 6 8 8 MOSMOD M = 0.99
MOS2 16 21 8 8 MOSMOD M = 0.01
S1A
S2A
12
RBREAK
15
13
8
14
13
RBREAK 17 18 RBKMOD 1
RDRAIN 50 16 RDSMOD 2.2e-3
RGATE 9 20 5.64
RIN 6 8 1e9
RSCL1 5 51 RSCLMOD 1e-6
RSCL2 5 50 1e3
17
18
S1B
CA
S2B
13
RVTO
19
CB
+
IT
14
+
VBAT
5
8
6
8
EGS
EDS
+
-
RSOURCE 8 7 RDSMOD 42.3e-3
RVTO 18 19 RVTOMOD 1
-
S1A 6 12 13 8 S1AMOD
S1B 13 12 13 8 S1BMOD
S2A 6 15 14 13 S2AMOD
S2B 13 15 14 13 S2BMOD
VBAT 8 19 DC 1
VTO 21 6 0.82
ESCL 51 50 VALUE = {(V(5,51)/ABS(V(5,51)))*(PWR(V(5,51)*1e6/50,6))}
.MODEL DBDMOD D (IS = 1.5e-13 RS = 10.9e-3 TRS1 = 2.3e-3 TRS2 = -1.75e-5 CJO = 6.84e-10 TT = 4.2e-8)
.MODEL DBKMOD D (RS = 4.15e-1 TRS1 = 3.73e-3 TRS2 = -3.21e-5)
.MODEL DPLCAPMOD D (CJO = 26.2e-11 IS = 1e-30 N = 10)
.MODEL MOSMOD NMOS (VTO = 3.91 KP = 12.68 IS = 1e-30 N = 10 TOX = 1 L = 1u W = 1u)
.MODEL RBKMOD RES (TC1 = 7.73e-4 TC2 = 2.12e-6)
.MODEL RDSMOD RES (TC1 = 5.0e-3 TC2 = 2.53e-5)
.MODEL RSCLMOD RES (TC1 = 2.05e-3 TC2 = 1.35e-5)
.MODEL RVTOMOD RES (TC1 = -4.44e-3 TC2 = -6.45e-6)
.MODEL S1AMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON = -5.29 VOFF= -3.29)
.MODEL S1BMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON = -3.29 VOFF= -5.29)
.MODEL S2AMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON = -2.25 VOFF= 2.75)
.MODEL S2BMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON = 2.75 VOFF= -2.25)
.ENDS
NOTE: For further discussion of the PSPICE model, consult A New PSPICE Sub-circuit for the Power MOSFET Featuring Global
Temperature Options; written by William J. Hepp and C. Frank Wheatley.
©2004 Fairchild Semiconductor Corporation
RFD14N05SM9A Rev. C1
RFD14N05SM9A
TRADEMARKS
The following includes registered and unregistered trademarks and service marks, owned by Fairchild Semiconductor and/or its global subsidiaries, and is not
intended to be an exhaustive list of all such trademarks.
AccuPower™
AX-CAP *
BitSiC™
Build it Now™
CorePLUS™
CorePOWER™
CROSSVOLT™
CTL™
F-PFS™
FRFET
Sync-Lock™
®*
®
®
®
tm
®
Global Power ResourceSM
GreenBridge™
Green FPS™
PowerTrench
PowerXS™
Programmable Active Droop™
QFET
QS™
Quiet Series™
RapidConfigure™
™
®
TinyBoost
TinyBuck
®
®
Green FPS™ e-Series™
Gmax™
GTO™
TinyCalc™
®
TinyLogic
TINYOPTO™
TinyPower™
TinyPWM™
TinyWire™
TranSiC™
TriFault Detect™
Current Transfer Logic™
IntelliMAX™
®
DEUXPEED
ISOPLANAR™
Marking Small Speakers Sound Louder
and Better™
MegaBuck™
MICROCOUPLER™
MicroFET™
MicroPak™
MicroPak2™
MillerDrive™
MotionMax™
Dual Cool™
®
EcoSPARK
Saving our world, 1mW/W/kW at a time™
SignalWise™
SmartMax™
EfficentMax™
ESBC™
®
TRUECURRENT *
SerDes™
SMART START™
®
Solutions for Your Success™
®
®
SPM
Fairchild
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STEALTH™
SuperFET
SuperSOT™-3
SuperSOT™-6
SuperSOT™-8
Fairchild Semiconductor
FACT Quiet Series™
®
®
UHC
®
Ultra FRFET™
UniFET™
VCX™
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OptoHiT™
OPTOLOGIC
OPTOPLANAR
FACT
FAST
®
®
FastvCore™
FETBench™
FPS™
®
®
SupreMOS
SyncFET™
*Trademarks of System General Corporation, used under license by Fairchild Semiconductor.
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FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY PRODUCTS HEREIN TO IMPROVE
RELIABILITY, FUNCTION, OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY
PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS.
THESE SPECIFICATIONS DO NOT EXPAND THE TERMS OF FAIRCHILD’S WORLDWIDE TERMS AND CONDITIONS, SPECIFICALLY THE WARRANTY
THEREIN, WHICH COVERS THESE PRODUCTS.
LIFE SUPPORT POLICY
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Counterfeiting of semiconductor parts is a growing problem in the industry. All manufactures of semiconductor products are experiencing counterfeiting of their
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PRODUCT STATUS DEFINITIONS
Definition of Terms
Datasheet Identification
Product Status
Definition
Datasheet contains the design specifications for product development. Specifications
may change in any manner without notice.
Advance Information
Formative / In Design
Datasheet contains preliminary data; supplementary data will be published at a later
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Preliminary
First Production
Datasheet contains final specifications. Fairchild Semiconductor reserves the right to
make changes at any time without notice to improve the design.
No Identification Needed
Obsolete
Full Production
Datasheet contains specifications on a product that is discontinued by Fairchild
Semiconductor. The datasheet is for reference information only.
Not In Production
Rev. I66
©2004 Fairchild Semiconductor Corporation
RFD14N05SM9A Rev. C1
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