RFD16N05LSM9A [ONSEMI]
N 沟道逻辑电平功率 MOSFET 50V，16A，47mΩ;
| 型号： | RFD16N05LSM9A |
| 厂家： | 
ONSEMI |
| 描述： | N 沟道逻辑电平功率 MOSFET 50V，16A，47mΩ 开关 脉冲 晶体管 |
| 文件： | 总9页 (文件大小：426K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
RFD16N05LSM
Product Preview
MOSFET - Power,
N-Channel, Logic Level
50 V, 16 A, 47 mW
www.onsemi.com
These are N−Channel logic level power MOSFETs manufactured
using the MegaFET process. This process, which uses feature sizes
approaching those of LSI integrated circuits gives optimum utilization
of silicon, resulting in outstanding performance. They were designed
for use with logic level (5 V) driving sources in applications such as
programmable controllers, switching regulators, switching converters,
motor relay drivers and emitter switches for bipolar transistors. This
performance is accomplished through a special gate oxide design
which provides full rated conductance at gate biases in the 3 V to 5 V
range, thereby facilitating true on−off power control directly from
logic circuit supply voltages.
D
G
S
Formerly developmental type TA09871.
D
Features
G
S
• 16 A, 50 V
• rDS(ON) = 0.047 W
DPAK
TO−252
CASE 369AS
• UIS SOA Rating Curve (Single Pulse)
• Design Optimized for 5 V Gate Drives
• Can be Driven Directly from CMOS, NMOS, TTL Circuits
• SOA is Power Dissipation Limited
• Nanosecond Switching Speeds
• Linear Transfer Characteristics
• High Input Impedance
MARKING DIAGRAM
$Y&Z&3&K
RFD16N
05LSM
• Majority Carrier Device
• Related Literature
♦ TB334 “Guidelines for Soldering Surface Mount Components to
PC Boards”
&Y
&Z
&3
&K
= ON Semiconductor Logo
= Assembly Plant Code
= Numeric Date Code
= Lot Code
RFD16N05LSM = Specific Device Code
ORDERING INFORMATION
Part Number
Package
Brand
RFD16N05LSM9A TO−252AA RFD16N05LSM
© Semiconductor Components Industries, LLC, 2003
1
Publication Order Number:
May, 2019 − Rev. 2
RFD16N05LSM/D
RFD16N05LSM
MAXIMUM RATINGS
Rating
Drain to Source Voltage (Note 1)
Symbol
RFD16N05LSM9A
Units
V
V
DS
50
50
Drain to Gate Voltage (R 20 kW) (Note 1)
V
DGR
V
GS
Continuous Drain Current
I
D
16
A
Pulsed Drain Current (Note 3)
Gate to Source Voltage
I
45
A
DM
V
10
V
GS
Maximum Power Dissipation
P
D
60
W
Derate Above 25°C
0.48
−55 to 150
W/°C
°C
Operating and Storage Temperature
Maximum Temperature for Soldering
Leads at 0.063 in (1.6 mm) from Case for 10 s
Package Body for 10 s, See Techbrief 334
T , T
J STG
T
L
300
260
°C
°C
T
pkg
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
1. T = 25°C to 125°C.
J
ELECTRICAL SPECIFICATIONS (T = 25°C unless otherwise specified)
C
PARAMETER
SYMBOL
BV
TEST CONDITIONS
= 250 mA, V = 0 V, Figure 10
MIN
50
1
TYP
MAX
UNITS
Drain to Source Breakdown Voltage
Gate to Threshold Voltage
I
-
-
V
V
DSS
D
GS
V
V
V
= V , I = 250 mA, Figure 9
−
−
2
1
GS(TH)
GS
DS
DS
D
Zero Gate Voltage Drain Current
I
= 40 V, V = 0 V
−
mA
DSS
GS
°
T
= 150 C
C
mA
nA
W
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
50
100
0.047
0.056
60
Gate to Source Leakage Current
I
V = 10 V, V = 0 V
GS DS
GSS
Drain to Source On Resistance (Note 2)
r
I
D
= 16 A, V = 5 V
−
DS(ON)
GS
I
D
= 16 A, V = 4 V
−
W
GS
Turn−On Time
t
V
= 25 V, I = 8 A, V
5 V,
−
ns
(ON)
DD
GS
D
GS =
R
= 12.5 W
Turn−On Delay Time
Rise Time
t
14
30
42
14
−
−
ns
d(ON)
Figures 15, 16
t
r
−
ns
Turn−Off Delay Time
Fall Time
t
−
ns
d(OFF)
t
f
−
ns
Turn−Off Time
t
−
ns
(OFF)
Total Gate Charge
Q
V
GS
V
GS
V
GS
= 0 V to 10 V
= 0 V to 5 V
= 0 V to 1 V
V = 40 V,
DD
−
80
nC
nC
nC
°C/W
°C/W
g(TOT)
I
= 16 A,
D
Gate Charge at 5 V
Threshold Gate Charge
Thermal Resistance Junction to Case
Thermal Resistance Junction to Ambient
Q
−
45
g(5)
R = 2.5 Ω
L
Figures 17, 18
Q
−
3
g(TH)
R
−
2.083
100
q
JC
JA
R
−
q
SOURCE TO DRAIN DIODE SPECIFICATIONS
PARAMETER
Source to Drain Diode Voltage
Diode Reverse Recovery Time
SYMBOL
TEST CONDITIONS
= 16 A
MIN
TYP
MAX
UNITS
VSD
trr
I
I
-
-
-
-
1.5
V
SD
= 16 A, dI /dt = 100 A/ms
125
ns
SD
SD
2. Pulse Test: Pulse Width ≤300 ms, Duty Cycle ≤2%.
3. Repetitive Rating: Pulse Width limited by max junction temperature.
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2
RFD16N05LSM
TYPICAL PERFORMANCE CURVES (Unless Otherwise Specified)
1.2
20
15
1.0
0.8
0.6
0.4
10
5
0
0.2
0
0
25
50
75
100
125
150
25
50
75
100
125
150
T , CASE TEMPERATURE (°C)
C
T , CASE TEMPERATURE (°C)
C
Figure 1. Normalized Power Dissipation vs
Case Temperature
Figure 2. Maximum Continuous Drain Current
vs Case Temperature
2
2
10
10
T
T
= 25°C
= MAX RATED
C
J
Idm
I
D
MAX CONTINUOUS
Starting T = 25°C
J
Starting T = 150°C
J
OPERATION IN THIS AREA
LIMITED BY r
10
)
DS(ON
DC
1
If R = 0
t
AV
= (L)(I )/(1.3 RATED BV
− V
DD
)
AS
DSS
If R ≠ 0
t
= (L/R)ln[(I × R)/(1.3 RATED BV
− V ) +1]
AV
AS
DSS DD
1
0.1
2
1
10
10
0.01
0.10
1
10
V , DRAIN TO SOURCE VOLTAGE (V)
DS
t , TIME IN AVALANCHE (ms)
AV
Figure 3. Forward Bias Safe Operating Area
Figure 4. Unclamped Inductive Switching SOA
(Single Pulse UIS SOA)
45
30
15
0
45
30
15
0
TC = 25°C
PULSE DURATION = 80 ms
DUTY CYCLE = 0.5% MAX.
V
GS
= 10 V
V
= 15 V
V
= 4 V
DS
GS
PULSE DURATION = 80 ms
DUTY CYCLE = 0.5% MAX
V
GS
= 5 V
V
V
= 3 V
= 2 V
GS
GS
0
1.5
V
3.0
4.5
6.0
7.5
0
1.5
3.0
4.5
6.0
, DRAIN TO SOURCE VOLTAGE (V)
V , GATE TO SOURCE VOLTAGE (V)
GS
DS
Figure 5. Saturation Characteristics
Figure 6. Transfer Characteristics
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3
RFD16N05LSM
TYPICAL PERFORMANCE CURVES (Unless Otherwise Specified) (continued)
1.4
1.3
1.2
2.5
I
V
= 16 V
PULSE DURATION = 80 ms
DUTY CYCLE = 0.5% MAX.
I = 16 A
D
D
= 15 V
PULSE DURATION = 80 ms
DUTY CYCLE = 0.5% MAX.
DS
2.0
1.1
1.0
0.9
0.8
0.7
0.6
0.5
1.5
1.0
0.5
0
4
5
6
7
−50
0
50
100
150
200
V , GATE TO SOURCE VOLTAGE (V)
GS
T , JUNCTION TEMPERATURE (°C)
J
Figure 7. Drain to Source on Resitance vs
Gate Voltageand Drain Current
Figure 8. Normalized Drain to Source on
Resistance vs. Junction Temperature
1.4
1.3
1.2
1.4
1.2
1.0
I
V
= 250 mA
I
D
= 250 mA
D
= V
GS
DS
1.1
1.0
0.9
0.8
0.8
0.7
0.6
0.6
0
−50
0
50
100
150
200
−50
0
50
100
150
200
T , JUNCTION TEMPERATURE (°C)
J
T , JUNCTION TEMPERATURE (°C)
J
Figure 9. Normalized Gate Threshold vs
Junction Temperature
Figure 10. Normalized Drain to Source
Breakdown Voltage vs Junction Temperature
50
2000
R
= 3.125 W, V = 5 V
GS
L
V
= 0 V
GS
I
= 0.60 mA
G(REF)
f = 1 MHz
PLATEAU VOLTAGES IN DESCENDING ORDER:
1600
1200
V
= BV
DSS
37.5
25
DD
V
DD
= BV
V
= BV
DSS
DD DSS
V
V
V
= 0.75 BV
= 0.50 BV
= 0.25 BV
DD
DD
DD
DSS
DSS
DSS
C
ISS
C
C
C
= C + C
GS GD
ISS
GATE
SOURCE
VOLTAGE
= C
= C + C
RSS
OSS
GD
800
400
0
DS
GD
12.5
0
C
C
OSS
RSS
DRAIN TO SOURCE VOLTAGE
0
5
10
15
20
25
0
I
I
I
G(REF)
G(REF)
20
80
I
V
, DRAIN TO SOURCE VOLTAGE (V)
t, TIME (ms)
DS
G(ACT)
G(ACT)
Figure 11. Capacitance vs Drain to Source
Voltage
Figure 12. Normalized Switching Waveforms
for Constant Gate Current
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4
RFD16N05LSM
TEST CIRCUITS AND WAVEFORMS
V
BV
DS
DSS
t
P
V
DS
L
I
AS
V
DD
VARY t TOOBTAIN
P
+
R
REQUIRED PEAK I
G
AS
V
DD
−
V
GS
DUT
0
t
P
I
0 V
AS
t
AV
0.01 W
Figure 13. Unclamped Energy Test Circuit
Figure 14. Unclamped Energy Waveforms
t
t
ON
OFF
t
d(OFF)
t
d(ON)
t
t
f
r
V
DS
90%
90%
R
L
+
10%
10%
0
0
V
DD
R
G
−
90%
50%
DUT
V
GS
50%
PULSE WIDTH
10%
V
GS
Figure 15. Switching Time Test Circuit
Figure 16. Resistive Switching Waveforms
V
DS
(ISOL ATED
SUPPLY)
CURRENT
REGULATOR
V
DD
Q
g(TOT)
V
GS
SAME TYPE
AS DUT
Q
gd
12V
BATTERY
0.2 mF
Q
50 kW
gs
0.3 mF
V
DS
D
S
0
0
G
DUT
I
I
G(RE F)
G(REF)
0
V
DS
CURRENT
I
D
SAMPLING
RESISTOR
I
CURRENT
SAMPLING
RESISTOR
G
Figure 17. Gate Charge Test Circuit
Figure 18. Gate Charge Waveforms
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5
RFD16N05LSM
PSPICE ELECTRICAL MODEL
.SUBCKT RFD16N05L 2 1 3 ; REV 4/8/92
Ca 12 8 3.33e-9
Cb 15 14 3.11e-9
Cin 6 8 1.21e-9
Dbody 7 5 DBDMOD
Dbreak 5 11 DBKMOD
Dplcap 10 5 DPLCAPMOD
Ebreak 11 7 17 18 70.9
Eds 14 8 5 8 1
Egs 13 8 6 8 1
Esg 6 10 6 8 1
Evto 20 6 18 8 1
IT 8 17 1
Lgate 1 9 1.38e-9
Ldrain 2 5 1.0e-12
Lsource 3 7 1.0e-9
Mos1 16 6 8 8 MOSMOD M = 0.99
Mos2 16 21 8 8 MOSMOD M = 0.01
Rin 6 8 1e9
Rbreak 17 18 RBKMOD 1
Rdrain 5 16 RDSMOD 27.38e-3
Rgate 9 20 2.98
Rsource 8 7 RDSMOD 0.614e-3
Rvto 18 19 RVTOMOD 1
S1a 6 12 13 8 S1AMOD
S1b 13 12 13 8 S1BMOD
S2a 6 15 14 13 S2AMOD
S2b 13 15 14 13 S2BMOD
Vbat 8 19 DC 1
Vto 21 6 0.448
.MODEL DBDMOD D (IS = 1.34e-13 RS = 1.21e-2 TRS1 = 1.64e-3 TRS2 = 2.59e-6 +CJO = 1.13e-9
TT = 4.14e-8)
.MODEL DBKMOD D (RS = 8.82e-2 TRS1 = -2.01e-3 TRS2 = 7.32e-10)
.MODEL DPLCAPMOD D (CJO = 0.522e-9 IS = 1e-30 N = 10)
.MODEL MOSMOD NMOS (VTO = 2.054 KP = 24.73 IS = 1e-30 N = 10 TOX = 1 L = 1u W = 1u)
.MODEL RBKMOD RES (TC1 = 1.01e-3 TC2 = 5.21e-8)
.MODEL RDSMOD RES (TC1 = 3.66e-3 TC2 = 1.46e-5)
.MODEL RVTOMOD RES (TC1 = -1.81e-3 TC2 = 1.41e-6)
.MODEL S1AMOD VSWITCH(RON = 1e-5 ROFF = 0.1 VON = -4.25 VOFF = -2.25)
.MODEL S1BMOD VSWITCH(RON = 1e-5 ROFF = 0.1 VON = -2.25 VOFF = -4.25)
.MODEL S2AMOD VSWITCH(RON = 1e-5 ROFF = 0.1 VON = -0.65 VOFF = 4.35)
.MODEL S2BMOD VSWITCH(RON = 1e-5 ROFF = 0.1 VON = 4.35 VOFF = -0.65)
.ENDS
NOTE: For further discussion of the PSPICE model, consult A New PSPICE Sub−Circuit for the Power MOSFET Featuring Global
Temperature Options; written by William J. Hepp and C. Frank Wheatley.
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6
RFD16N05LSM
DPLCAP
5
DRAIN
2
10
LDRAIN
RSCL1
51
+
DBREAK
RSCL2
5
ESCL
51
50
−
+
DBODY
6
8
11
RDRAIN
ESG
17
18
16
EBREAK
+
VTO
+
−
MOS2
EVTO
GATE
1
21
+
−
6
9
20
18
8
MOS1
8
LGATE RGATE
RIN
CIN
LSOURCE
RSOURCE
7
3
SOURCE
S1A
S2A
12
RBREAK
15
14
13
13
8
17
18
S1B
CA
S2B
13
RVTO
19
CB
+
IT
14
+
VBAT
5
8
6
8
EGS
EDS
+
−
−
Figure 19.
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7
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
DPAK3 (TO−252 3 LD)
CASE 369AS
ISSUE A
DATE 28 SEP 2022
GENERIC
MARKING DIAGRAM*
XXXXXX
XXXXXX
AYWWZZ
XXXX = Specific Device Code
*This information is generic. Please refer to
device data sheet for actual part marking.
Pb−Free indicator, “G” or microdot “G”, may
or may not be present. Some products may
not follow the Generic Marking.
A
Y
= Assembly Location
= Year
WW = Work Week
ZZ
= Assembly Lot Code
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
DOCUMENT NUMBER:
98AON13810G
DPAK3 (TO−252 3 LD)
PAGE 1 OF 1
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相关型号：
RFD16N05LSM9A_NL
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