RFD3055LESM9A [ONSEMI]
N 沟道，逻辑电平，功率 MOSFET，60V，11A，107mΩ;
| 型号： | RFD3055LESM9A |
| 厂家： | 
ONSEMI |
| 描述： | N 沟道，逻辑电平，功率 MOSFET，60V，11A，107mΩ 局域网 开关 晶体管 |
| 文件： | 总10页 (文件大小：1304K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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RFD3055LE, RFD3055LESM
Data Sheet
September 2013
Features
N-Channel Logic Level Power MOSFET
60V, 11A, 107 mΩ
• 11A, 60V
These N-Channel enhancement-mode power MOSFETs are
manufactured using the latest manufacturing process
technology. This process, which uses feature sizes
approaching those of LSI circuits, gives optimum utilization
of silicon, resulting in outstanding performance. They were
designed for use in applications such as switching
regulators, switching converters, motor drivers and relay
drivers. These transistors can be operated directly from
integrated circuits.
• r = 0.107Ω
DS(ON)
®
• Temperature Compensating PSPICE Model
• Peak Current vs Pulse Width Curve
• UIS Rating Curve
• Related Literature
- TB334 “Guidelines for Soldering Surface Mount
Components to PC Boards”
Formerly developmental type TA49158.
Symbol
D
Ordering Information
PART NUMBER
PACKAGE
TO-251AA
TO-252AA
BRAND
F3055L
F3055L
RFD3055LE
G
RFD3055LESM9A
S
Packaging
JEDEC TO-251AA
JEDEC TO-252AA
DRAIN (FLANGE)
SOURCE
DRAIN
GATE
GATE
DRAIN (FLANGE)
SOURCE
©2002 Fairchild Semiconductor Corporation
RFD3055LE, RFD3055LESM Rev. C0
RFD3055LE, RFD3055LESM
o
Absolute Maximum Ratings T = 25 C, Unless Otherwise Specified
C
RFD3055LE,
RFD3055LESM9A
UNITS
Drain to Source Voltage (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . V
60
60
16
11
V
V
V
A
DSS
Drain to Gate Voltage (R
= 20kΩ) (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . V
GS
DGR
Gate to Source Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .V
Continuous Drain Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I
GS
D
Pulsed Drain Current (Note 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I
Refer to Peak Current Curve
DM
Single Pulse Avalanche Rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .E
Refer to UIS Curve
AS
Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .P
38
0.25
W
D
o
o
Derate Above 25 C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
W/ C
o
Operating and Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . T , T
-55 to 175
C
J
STG
Maximum Temperature for Soldering
Leads at 0.063in (1.6mm) from Case for 10s. . . . . . . . . . . . . . . . . . . . . . . . . . . . T
Package Body for 10s, See Techbrief 334 . . . . . . . . . . . . . . . . . . . . . . . . . . . . T
o
o
300
260
C
C
L
pkg
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE:
o
o
1. T = 25 C to 150 C.
J
o
Electrical Specifications
T
= 25 C, Unless Otherwise Specified
C
PARAMETER
SYMBOL
TEST CONDITIONS
= 250µA, V = 0V
MIN
TYP
MAX UNITS
Drain to Source Breakdown Voltage
Gate Threshold Voltage
BV
I
60
1
-
-
-
3
V
DSS
D
GS
= V , I = 250µA
V
V
V
V
V
-
-
V
GS(TH)
GS
DS
DS
GS
DS D
Zero Gate Voltage Drain Current
I
= 55V, V
= 50V, V
= 0V
1
µA
µA
nA
Ω
DSS
GSS
GS
GS
o
= 0V, T = 150 C
-
-
250
100
0.107
170
-
C
Gate to Source Leakage Current
I
=
16V
-
-
Drain to Source On Resistance (Note 2)
Turn-On Time
r
I
= 8A, V
= 5V (Figure 11)
-
-
DS(ON)
D
GS
t
V
V
≈ 30V, I = 8A,
-
-
ns
ON
DD
GS
D
= 4.5V, R
= 32Ω
GS
Turn-On Delay Time
Rise Time
t
-
8
ns
d(ON)
(Figures 10, 18, 19)
t
-
105
22
39
-
-
ns
r
Turn-Off Delay Time
Fall Time
t
-
-
ns
d(OFF)
t
-
-
ns
f
Turn-Off Time
t
-
92
11.3
6.2
0.43
-
ns
OFF
Total Gate Charge
Q
V
V
V
V
= 0V to 10V
= 0V to 5V
= 0V to 1V
V
= 30V, I = 8A,
= 1.0mA
-
9.4
5.2
0.36
350
105
23
-
nC
nC
nC
pF
pF
pF
C/W
C/W
C/W
g(TOT)
GS
GS
GS
DS
DD
D
I
g(REF)
Gate Charge at 5V
Q
-
g(5)
(Figures 20, 21)
= 0V, f = 1MHz
GS
Threshold Gate Charge
Input Capacitance
Q
-
g(TH)
C
= 25V, V
-
ISS
OSS
RSS
(Figure 14)
Output Capacitance
C
C
-
-
Reverse Transfer Capacitance
Thermal Resistance Junction to Case
Thermal Resistance Junction to Ambient
-
-
o
o
o
R
-
3.94
62
100
θJC
θJA
R
TO-220AB
-
-
TO-251AA, TO-252AA
-
-
Source to Drain Diode Specifications
PARAMETER
Source to Drain Diode Voltage
Diode Reverse Recovery Time
NOTES:
SYMBOL
TEST CONDITIONS
MIN
TYP MAX UNITS
V
I
I
= 8A
-
-
1.25
66
V
SD
SD
SD
t
= 8A, dI /dt = 100A/µs
SD
ns
rr
2. Pulse Test: Pulse Width ≤ 300ms, Duty Cycle ≤ 2%.
3. Repetitive Rating: Pulse Width limited by max junction temperature. See Transient Thermal Impedance Curve (Figure 3) and Peak Current
Capability Curve (Figure 5).
©2002 Fairchild Semiconductor Corporation
RFD3055LE, RFD3055LESM Rev. C0
RFD3055LE, RFD3055LESM
Typical Performance Curves Unless Otherwise Specified
1.2
1.0
0.8
0.6
0.4
0.2
0
15
V
= 10V
GS
10
V
= 4.5V
GS
5
0
125
o
0
25
50
75
100
175
25
50
75
100
125
150
175
150
o
T
, CASE TEMPERATURE ( C)
C
T , CASE TEMPERATURE ( C)
C
FIGURE 1. NORMALIZED POWER DISSIPATION vs CASE
TEMPERATURE
FIGURE 2. MAXIMUM CONTINUOUS DRAIN CURRENT vs
CASE TEMPERATURE
2
DUTY CYCLE - DESCENDING ORDER
0.5
1
0.2
0.1
0.05
0.02
0.01
P
DM
0.1
t
1
t
2
NOTES:
DUTY FACTOR: D = t /t
1
2
SINGLE PULSE
PEAK T = P
x Z
x R + T
J
DM
θJC
θJC C
0.01
-5
-4
10
-3
10
-2
10
-1
10
0
1
10
10
10
t, RECTANGULAR PULSE DURATION (s)
FIGURE 3. NORMALIZED TRANSIENT THERMAL IMPEDANCE
200
100
10
o
= 25 C
T
C
FOR TEMPERATURES
o
ABOVE 25 C DERATE PEAK
CURRENT AS FOLLOWS:
100
100µs
175 - T
150
C
I = I
25
OPERATION IN THIS
AREA MAY BE
LIMITED BY r
1ms
1
DS(ON)
10ms
V
= 5V
GS
SINGLE PULSE
J
o
TRANSCONDUCTANCE
MAY LIMIT CURRENT
IN THIS REGION
T
= MAX RATED T = 25 C
C
0.1
10
1
10
100
200
-5
-4
10
-3
10
-2
10
-1
10
0
1
10
10
10
V
, DRAIN TO SOURCE VOLTAGE (V)
DS
t, PULSE WIDTH (s)
FIGURE 4. FORWARD BIAS SAFE OPERATING AREA
FIGURE 5. PEAK CURRENT CAPABILITY
©2002 Fairchild Semiconductor Corporation
RFD3055LE, RFD3055LESM Rev. C0
RFD3055LE, RFD3055LESM
Typical Performance Curves Unless Otherwise Specified (Continued)
100
10
1
15
12
9
If R = 0
= (L)(I )/(1.3*RATED BV
V
= 10V
= 5V
GS
t
- V )
DD
AV
If R ≠ 0
= (L/R)ln[(I *R)/(1.3*RATED BV
AS
DSS
V
GS
V
= 4V
GS
t
AV
- V ) +1]
DD
AS DSS
o
STARTING T = 25 C
J
V
= 3.5V
GS
o
6
STARTING T = 150 C
J
PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX
3
V
= 3V
o
GS
T
= 25 C
C
0
0.001
0.01
0.1
1
10
0
1
2
3
4
t
,TIME IN AVALANCHE (ms)
V
, DRAIN TO SOURCE VOLTAGE (V)
AV
DS
NOTE: Refer to Fairchild Application Notes AN9321 and AN9322
FIGURE 7. SATURATION CHARACTERISTICS
FIGURE 6. UNCLAMPED INDUCTIVE SWITCHING
15
150
120
90
PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX
DD
PULSE DURATION = 80µs
I
= 11A
I
= 3A
D
D
DUTY CYCLE = 0.5% MAX
o
V
= 15V
T
= 25 C
C
12
9
I
= 5A
D
o
6
T
= 25 C
J
3
0
o
T
= 175 C
J
o
T
= -55 C
J
60
2
3
4
5
2
4
6
8
10
V
, GATE TO SOURCE VOLTAGE (V)
V
, GATE TO SOURCE VOLTAGE (V)
GS
GS
FIGURE 8. TRANSFER CHARACTERISTICS
FIGURE 9. DRAINTO SOURCE ON RESISTANCE vs GATE
VOLTAGE AND DRAIN CURRENT
150
100
50
2.5
PULSE DURATION = 80µs
V
= 4.5V, V
DD
= 30V, I = 8A
D
GS
DUTY CYCLE = 0.5% MAX
t
r
2.0
1.5
1.0
t
f
t
d(OFF)
V
= 10V, I = 11A
D
GS
t
d(ON)
0.5
-80
0
-40
0
40
80
120
160
200
0
10
20
30
40
50
o
R
, GATE TO SOURCE RESISTANCE (Ω)
T , JUNCTION TEMPERATURE ( C)
GS
J
FIGURE 10. SWITCHING TIME vs GATE RESISTANCE
FIGURE 11. NORMALIZED DRAINTO SOURCE ON
RESISTANCE vs JUNCTION TEMPERATURE
©2002 Fairchild Semiconductor Corporation
RFD3055LE, RFD3055LESM Rev. C0
RFD3055LE, RFD3055LESM
Typical Performance Curves Unless Otherwise Specified (Continued)
1.2
1.2
1.1
1.0
0.9
I
= 250µA
D
V
= V , I = 250µA
DS
GS
D
1.0
0.8
0.6
-80
-40
0
40
80
120
160
200
-80
-40
0
40
80
120
160
200
o
o
T , JUNCTION TEMPERATURE ( C)
T , JUNCTION TEMPERATURE ( C)
J
J
FIGURE 12. NORMALIZED GATETHRESHOLDVOLTAGE vs
JUNCTION TEMPERATURE
FIGURE 13. NORMALIZED DRAIN TO SOURCE BREAKDOWN
VOLTAGE vs JUNCTION TEMPERATURE
10
1000
V
= 30V
DD
C
= C
+ C
ISS
GS GD
8
6
4
2
0
C
≅ C
DS
+ C
GD
OSS
100
WAVEFORMS IN
DESCENDING ORDER:
I
I
I
= 11A
= 5A
= 3A
D
D
D
V
= 0V, f = 1MHz
1
GS
C
= C
GD
RSS
10
0
2
4
6
8
10
60
0.1
10
Q , GATE CHARGE (nC)
g
V
, DRAIN TO SOURCE VOLTAGE (V)
DS
NOTE: Refer to Fairchild Application Notes AN7254 and AN7260.
FIGURE 15. NORMALIZED SWITCHINGWAVEFORMS FOR
CONSTANT GATE CURRENT
FIGURE 14. CAPACITANCE vs DRAIN TO SOURCE VOLTAGE
Test Circuits and Waveforms
V
DS
BV
DSS
L
t
P
V
DS
I
VARY t TO OBTAIN
P
AS
+
-
V
DD
R
REQUIRED PEAK I
G
AS
V
DD
V
GS
DUT
t
P
I
AS
0V
0
0.01Ω
t
AV
FIGURE 16. UNCLAMPED ENERGY TEST CIRCUIT
FIGURE 17. UNCLAMPED ENERGY WAVEFORMS
©2002 Fairchild Semiconductor Corporation
RFD3055LE, RFD3055LESM Rev. C0
RFD3055LE, RFD3055LESM
Test Circuits and Waveforms (Continued)
t
t
ON
OFF
t
d(OFF)
t
d(ON)
V
DS
t
t
f
r
V
DS
90%
90%
R
L
V
GS
+
10%
10%
0
V
DD
-
DUT
90%
50%
R
GS
V
GS
50%
PULSE WIDTH
10%
V
GS
0
FIGURE 18. SWITCHING TEST CIRCUIT
FIGURE 19. RESISTIVE SWITCHING WAVEFORMS
V
DS
V
Q
R
DD
g(TOT)
L
V
DS
V
= 20V
GS
V
L
= 10V FOR
Q
OR Q
GS
DEVICES
g(10)
g(5)
V
GS
2
+
-
V
DD
V
= 10V
GS
V
GS
V
= 5V FOR
GS
2
L
DEVICES
DUT
V
= 2V
V
= 1V FOR
GS
GS
2
I
L DEVICES
0
g(REF)
Q
g(TH)
I
g(REF)
0
FIGURE 20. GATE CHARGE TEST CIRCUIT
FIGURE 21. GATE CHARGE WAVEFORMS
©2002 Fairchild Semiconductor Corporation
RFD3055LE, RFD3055LESM Rev. C0
RFD3055LE, RFD3055LESM
PSPICE Electrical Model
.SUBCKT RFD3055LE 2 1 3 ;
rev 1/30/95
CA 12 8 3.9e-9
CB 15 14 4.9e-9
CIN 6 8 3.25e-10
DBODY 7 5 DBODYMOD
DBREAK 5 11 DBREAKMOD
DPLCAP 10 5 DPLCAPMOD
LDRAIN
DPLCAP
DRAIN
2
5
10
RLDRAIN
RSLC1
51
EBREAK 11 7 17 18 67.8
EDS 14 8 5 8 1
EGS 13 8 6 8 1
ESG 6 10 6 8 1
EVTHRES 6 21 19 8 1
EVTEMP 20 6 18 22 1
DBREAK
+
RSLC2
5
ESLC
11
51
-
50
+
-
17
18
-
DBODY
RDRAIN
6
8
EBREAK
ESG
IT 8 17 1
EVTHRES
+
+
16
21
-
19
8
MWEAK
LDRAIN 2 5 1.0e-9
LGATE 1 9 5.42e-9
LSOURCE 3 7 2.57e-9
LGATE
EVTEMP
+
RGATE
GATE
1
6
-
18
22
MMED
9
20
MSTRO
8
RLGATE
MMED 16 6 8 8 MMEDMOD
MSTRO 16 6 8 8 MSTROMOD
MWEAK 16 21 8 8 MWEAKMOD
LSOURCE
CIN
SOURCE
3
7
RSOURCE
RBREAK 17 18 RBREAKMOD 1
RDRAIN 50 16 RDRAINMOD 3.7e-2
RGATE 9 20 3.37
RLDRAIN 2 5 10
RLGATE 1 9 54.2
RLSOURCE
S1A
S2A
RBREAK
12
15
13
8
14
13
17
18
RLSOURCE 3 7 25.7
RSLC1 5 51 RSLCMOD 1e-6
RSLC2 5 50 1e3
RSOURCE 8 7 RSOURCEMOD 2.50e-2
RVTHRES 22 8 RVTHRESMOD 1
RVTEMP 18 19 RVTEMPMOD 1
RVTEMP
19
S1B
S2B
13
CB
CA
IT
14
-
+
+
VBAT
6
8
5
8
EGS
EDS
+
-
-
8
S1A 6 12 13 8 S1AMOD
S1B 13 12 13 8 S1BMOD
S2A 6 15 14 13 S2AMOD
S2B 13 15 14 13 S2BMOD
22
RVTHRES
VBAT 22 19 DC 1
ESLC 51 50 VALUE={(V(5,51)/ABS(V(5,51)))*(PWR(V(5,51)/(1e-6*30),3))}
.MODEL DBODYMOD D (IS = 1.75e-13 RS = 1.75e-2 TRS1 = 1e-4 TRS2 = 5e-6 CJO = 5.9e-10 TT = 5.45e-8 N = 1.03 M = 0.6)
.MODEL DBREAKMOD D (RS = 6.50e-1 TRS1 = 1.25e-4 TRS2 = 1.34e-6)
.MODEL DPLCAPMOD D (CJO = 3.21e-10 IS = 1e-30 N = 10 M = 0.81)
.MODEL MMEDMOD NMOS (VTO = 2.02 KP = .83 IS = 1e-30 N = 10 TOX = 1 L = 1u W = 1u RG = 3.37)
.MODEL MSTROMOD NMOS (VTO = 2.39 KP = 14 IS = 1e-30 N = 10 TOX = 1 L = 1u W = 1u)
.MODEL MWEAKMOD NMOS (VTO = 1.78 KP = 0.02 IS = 1e-30 N = 10 TOX = 1 L = 1u W = 1u RG = 33.7 RS = 0.1)
.MODEL RBREAKMOD RES (TC1 = 1.06e-3 TC2 = 0)
.MODEL RDRAINMOD RES (TC1 = 1.23e-2 TC2 = 2.58e-5)
.MODEL RSLCMOD RES (TC1 = 0 TC2 = 0)
.MODEL RSOURCEMOD RES (TC1 = 1e-3 TC2 = 0)
.MODEL RVTHRESMOD RES (TC1 = -2.19e-3 TC2 = -4.97e-6)
.MODEL RVTEMPMOD RES (TC1 = -1.6e-3 TC2 = 1e-7)
.MODEL S1AMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON = -4 VOFF= -2.5)
.MODEL S1BMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON = -2.5 VOFF= -4)
.MODEL S2AMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON = -0.5 VOFF= 0)
.MODEL S2BMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON = 0 VOFF= -0.5)
.ENDS
For further discussion of the PSPICE model, consult A New PSPICE Sub-Circuit for the Power MOSFET Featuring Global
Temperature Options; IEEE Power Electronics Specialist Conference Records, 1991, written by William J. Hepp and C. Frank
Wheatley.
©2002 Fairchild Semiconductor Corporation
RFD3055LE, RFD3055LESM Rev. C0
RFD3055LE, RFD3055LESM
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PowerXS™
Programmable Active Droop™
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QS™
Quiet Series™
RapidConfigure™
™
®
TinyBoost
TinyBuck
®
®
Green FPS™ e-Series™
Gmax™
GTO™
TinyCalc™
®
TinyLogic
TINYOPTO™
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Fairchild
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Fairchild Semiconductor
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®
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Not In Production
Rev. I66
©2002 Fairchild Semiconductor Corporation
RFD3055LE, RFD3055LESM Rev. C0
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