RFP12N10L [ONSEMI]
N 沟道，逻辑电平，功率 MOSFET，100V，12A，200mΩ;
| 型号： | RFP12N10L |
| 厂家： | 
ONSEMI |
| 描述： | N 沟道，逻辑电平，功率 MOSFET，100V，12A，200mΩ 局域网 开关 脉冲 晶体管 |
| 文件： | 总8页 (文件大小：535K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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RFP12N10L
Data Sheet
October 2013
N-Channel Logic Level Power MOSFET
100 V, 12 A, 200 mΩ
Features
• 12A, 100V
These are N-Channel enhancement mode silicon gate
power field effect transistors specifically designed for use
with logic level (5V) driving sources in applications such as
programmable controllers, automotive switching and
solenoid drivers. This performance is accomplished
through a special gate oxide design which provides full
rated conduction at gate biases in the 3V to 5V range,
thereby facilitating true on-off power control directly from
logic circuit supply voltages.
• r
= 0.200Ω
DS(ON)
• Design Optimized for 5V Gate Drives
• Can be Driven Directly from QMOS, NMOS,
TTL Circuits
• Compatible with Automotive Drive Requirements
• SOA is Power-Dissipation Limited
• Nanosecond Switching Speeds
• Linear Transfer Characteristics
• High Input Impedance
Formerly developmental type TA09526.
Ordering Information
• Majority Carrier Device
PART NUMBER
PACKAGE
BRAND
F12N10L
• Related Literature
RFP12N10L
TO-220AB
- TB334 “Guidelines for Soldering Surface Mount
Components to PC Boards
Symbol
D
G
S
Packaging
JEDEC TO-220AB
SOURCE
DRAIN
GATE
DRAIN
(TAB)
©2005 Fairchild Semiconductor Corporation
RFP12N10L Rev. C0
RFP12N10L
o
Absolute Maximum Ratings
T = 25 C, Unless Otherwise Specified
C
RFP12N10L
UNITS
Drain to Source Voltage (Note 1). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .V
100
100
V
V
DS
Drain to Gate Voltage (R
= 1MΩ) (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . V
DGR
GS
Continuous Drain Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I
12
A
D
Pulsed Drain Current (Note 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I
30
A
DM
Gate to Source Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .V
GS
±10
V
Maximum Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .P
o
60
W
D
o
Above T = 25 C, Derate Linearly. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
0.48
-55 to 150
W/ C
C
o
Operating and Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . T
T
C
J, STG
Maximum Temperature for Soldering
Leads at 0.063in (1.6mm) from Case for 10s. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . T
Package Body for 10s, See Techbrief 334 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . T
o
300
260
C
C
L
o
pkg
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE:
o
o
1. T = 25 C to 125 C.
J
o
Electrical Specifications
T
= 25 C, Unless Otherwise Specified
C
PARAMETER
SYMBOL
TEST CONDITIONS
= 250µA, V = 0V
MIN
TYP
MAX
-
UNITS
V
Drain to Source Breakdown Voltage
Gate to Threshold Voltage
BV
I
100
-
DSS
D
GS
V
V
V
V
V
= V , I = 250µA (Figure 7)
1
-
-
-
-
-
-
-
-
-
-
-
-
2
V
GS(TH)
GS
DS
GS
GS
DS D
= 80V
-
-
1
µA
µA
nA
Ω
Zero Gate Voltage Drain Current
Gate to Source Leakage Current
I
DSS
o
= 0V
T
= 125 C
50
C
I
= 10V, V
DS
= 0V
-
100
0.200
900
325
170
50
GSS
Drain to Source On Resistance (Note 2)
Input Capacitance
r
I
= 12A, V
D GS
= 5V (Figures 5, 6)
= 25V, f = 1MHz
-
DS(ON)
C
V
= 0V, V
DS
-
pF
pF
pF
ns
ISS
GS
(Figure 8)
Output Capacitance
C
C
-
OSS
Reverse-Transfer Capacitance
Turn-On Delay Time
-
RSS
t
I
V
= 6A, V
DD
= 50V, R = 6.25Ω,
15
70
100
80
d(ON)
D
G
= 5V
GS
(Figures 9, 10, 11)
Rise Time
t
150
130
150
2.083
ns
r
Turn-Off Delay Time
t
ns
d(OFF)
Fall Time
t
ns
f
Thermal Resistance Junction to Case
R
TO-220
oC/W
JC
θ
Source to Drain Diode Specifications
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
TYP
-
MAX
1.4
-
UNITS
V
Source to Drain Diode Voltage (Note 2)
Diode Reverse Recovery Time
V
I
I
= 6A
-
-
SD
SD
SD
t
= 4A, dI /dt = 50A/µs
SD
150
ns
rr
NOTES:
2. Pulsed: pulse duration = 80µs max, duty cycle = 2%.
3. Repetitive rating: pulse width limited by maximum junction temperature.
©2005 Fairchild Semiconductor Corporation
RFP12N10L Rev. C0
RFP12N10L
Typical Performance Curves Unless Otherwise Specified
1.2
1.0
0.8
0.6
0.4
0.2
0
100
10
o
OPERATION IN THIS
REGION IS LIMITED
T
= 25 C
C
TJ = MAX RATED
BY r
DS(ON)
I (MAX) CONTINUOUS
D
DC OPERATION
1
60W
0.1
0
50
100
o
150
1
10
100
1000
T , CASE TEMPERATURE ( C)
V
DS
, DRAIN TO SOURCE VOLTAGE (V)
C
FIGURE 1. NORMALIZED POWER DISSIPATION vs CASE
TEMPERATURE
FIGURE 2. FORWARD BIAS OPERATING AREA
40
20
15
PULSE DURATION = 80µs
V
= 10V
DS
DUTY CYCLE ≤0.5%
PULSE DURATION = 80µs
DUTY CYCLE ≤0.5%
o
T
= 25 C
C
o
30
-40 C
o
25 C
20
10
0
10
4V
3V
o
125 C
5
0
o
2V
4
125 C
o
-40 C
0
1
2
3
4
5
0
1
2
3
5
V
DRAIN TO SOURCE VOLTAGE (V)
V
, GATE TO SOURCE VOLTAGE (V)
DS,
GS
FIGURE 3. SATURATION CHARACTERISTICS
FIGURE 4. TRANSFER CHARACTERISTICS
2.0
0.3
0.2
0.1
0
V
= 5V, I = 12A
D
GS
o
125 C
PULSE DURATION = 80µs
DUTY CYCLE ≤0.5%
1.5
1.0
o
25 C
o
-40 C
0.5
0
V
= 5V
GS
PULSE DURATION = 80µs
DUTY CYCLE ≤0.5%
0
5
10
15
20
25
30
-50
0
50
100
o
150
I
DRAIN CURRENT (A)
T , JUNCTION TEMPERATURE ( C)
D,
J
FIGURE 5. DRAIN TO SOURCE ON RESISTANCE vs DRAIN
CURRENT
FIGURE 6. NORMALIZED DRAIN TO SOURCE ON
RESISTANCE vs JUNCTION TEMPERATURE
©2005 Fairchild Semiconductor Corporation
RFP12N10L Rev. C0
RFP12N10L
Typical Performance Curves Unless Otherwise Specified (Continued)
1.3
1.2
800
600
400
V
I
= V
GS
V
= 0V, f = 1MHz
DS
= 250µA
GS
C
C
C
= C
+ C
GD
ISS
GS
D
= C
RSS
OSS
GD
≈
C
+ C
1.1
1.0
DS GD
C
ISS
0.9
0.8
C
OSS
200
0
0.7
C
RSS
0.6
0.5
-50
0
50
100
o
150
0
10
20
30
40
50
T , JUNCTION TEMPERATURE ( C)
V
DS,
DRAIN TO SOURCE VOLTAGE (V)
J
FIGURE 7. NORMALIZED GATE THRESHOLD VOLTAGE vs
JUNCTION TEMPERATURE
FIGURE 8. CAPACITANCE vs DRAIN TO SOURCE VOLTAGE
10
8
100
BV
DSS
R
= 8.33Ω
= 0.56mA
L
I
G (REF)
V
= 5V
75
GS
GATE
SOURCE
VOLTAGE
6
V
= BV
DD
DSS
V
= BV
DSS
DD
50
25
0
4
0.75BV
0.50BV
0.25BV
DSS
DSS
DSS
2
0
DRAIN SOURCE
VOLTAGE
I
(REF)
I
(REF)
I (ACT)
G
G
G
20
80
t, TIME (µs)
I
(ACT)
G
NOTE: Refer to Fairchild Applications Notes AN7254 and AN7260
FIGURE 9. NORMALIZED SWITCHING WAVEFORMS FOR CONSTANT GATE CURRENT
Test Circuits and Waveforms
t
t
ON
OFF
t
d(OFF)
t
d(ON)
t
t
f
r
R
V
L
DS
90%
90%
+
V
DD
10%
10%
0
-
DUT
90%
50%
R
GS
V
GS
50%
PULSE WIDTH
10%
V
GS
0
FIGURE 10. SWITCHING TIME TEST CIRCUIT
FIGURE 11. RESISTIVE SWITCHING WAVEFORMS
©2005 Fairchild Semiconductor Corporation
RFP12N10L Rev. C0
RFP12N10L
Test Circuits and Waveforms (Continued)
V
DS
V
Q
R
DD
g(TOT)
L
V
DS
V
= 10V
GS
V
GS
Q
+
-
g(5)
V
DD
V
= 5V
V
GS
GS
DUT
V
= 1V
GS
I
0
G(REF)
Q
g(TH)
I
G(REF)
0
FIGURE 12. GATE CHARGE TEST CIRCUIT
FIGURE 13. GATE CHARGE WAVEFORMS
©2005 Fairchild Semiconductor Corporation
RFP12N10L Rev. C0
RFP12N10L
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Datasheet contains the design specifications for product development. Specifications
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Datasheet contains preliminary data; supplementary data will be published at a later
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Full Production
Datasheet contains specifications on a product that is discontinued by Fairchild
Semiconductor. The datasheet is for reference information only.
Not In Production
Rev. I66
©2005 Fairchild Semiconductor Corporation
RFP12N10L Rev. C0
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are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.
ON Semiconductor owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of ON Semiconductor’s product/patent
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ON Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
Buyer is responsible for its products and applications using ON Semiconductor products, including compliance with all laws, regulations and safety requirements or standards,
regardless of any support or applications information provided by ON Semiconductor. “Typical” parameters which may be provided in ON Semiconductor data sheets and/or
specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer
application by customer’s technical experts. ON Semiconductor does not convey any license under its patent rights nor the rights of others. ON Semiconductor products are not
designed, intended, or authorized for use as a critical component in life support systems or any FDA Class 3 medical devices or medical devices with a same or similar classification
in a foreign jurisdiction or any devices intended for implantation in the human body. Should Buyer purchase or use ON Semiconductor products for any such unintended or unauthorized
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expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such
claim alleges that ON Semiconductor was negligent regarding the design or manufacture of the part. ON Semiconductor is an Equal Opportunity/Affirmative Action Employer. This
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相关型号：
RFP14N05L_NL
Power Field-Effect Transistor, 14A I(D), 50V, 0.1ohm, 1-Element, N-Channel, Silicon, Metal-oxide Semiconductor FET, TO-220AB, LEAD FREE PACKAGE-3
FAIRCHILD
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