RV4141AMT [ONSEMI]
接地故障断路器 (GFCI) 控制器,低功耗;型号: | RV4141AMT |
厂家: | ONSEMI |
描述: | 接地故障断路器 (GFCI) 控制器,低功耗 PC 控制器 光电二极管 断路器 |
文件: | 总11页 (文件大小:748K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
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2011 年 12 月
RV4141A
低功率,接地故障中断器
特性
说明
RV4141A 是交流电源插座接地故障电路中断器的低功率
控制器。此类器件检测接地和地线与零线之间故障的危险
电流路径。在发生有害或致命冲击前,电路中断器将负载
从线路断开。
.
.
.
.
.
.
.
.
.
.
由交流线路供电
内置整流器
直接连接至 SCR
500μA 静态电流
精密感应放大器
可调延时
RV4141A 内部包含一个二极管整流器、电压调节器、精
密感应放大器、参考电流、延时电路和 SCR 驱动器。
两个感应变压器、SCR、电磁阀、三个电阻和四个电容
完成了基本电路中断器的设计。简单布局和最少的元件数
目确保了应用简便和长期可靠。其他 GFCI 控制器所没有
的功能包括一个低失调电压感应放大器,无需在感应变压
器和感应放大器间增加一个耦合电容,还包含一个内部整
流器来消除对高压整流二极管的需求。
最少的外部组件
满足 UL 943 要求
兼容 110V 或 220V 系统
提供 8 引脚 SOIC 封装
RV4141A 仅在线路电压的正向半个期间供电,但始终能
够感应电流默认值,与其相对于线路电压的相位无关。
SCR 的栅极仅在线路电压的正半周期期间驱动。
订购信息
器件编号
RV4141AN
工作温度范围
-35 至 +80°C
-35 至 +80°C
封装
8 引线,塑料双列直插封装 (DIP)
8 引线,塑料小外形集成电路 (SOIC)
包装方法
轨道
RV4141AMT
卷带
© 2003 飞兆半导体公司
www.fairchildsemi.com
RV4141A • Rev. 1.0.8
框图
图 1. 框图
引脚布局
图 2. 引脚分配
引脚定义
引脚号
名称
说明
1
2
3
4
5
6
7
8
放大器输出 感测放大器输出– 到 VFB 的外部电阻设置 IFAULT 阈值
VFB
VREF
感测放大器反向输入
感测放大器同向输入 – +VS/2 内部偏置
接地
GND
Line
内部二极管阳极连接到电源电压
RV4141A 电路的电源输入
+VS
SCR 触发
延迟电容
检测到故障时触发外部 SCR 的输出
一种连接到接地的外部电容,设置触发 SCR 前出现接地故障的延迟时间
© 2003 飞兆半导体公司
www.fairchildsemi.com
RV4141A • Rev. 1.0.8
2
绝对最大额定值
应力超过绝对最大额定值,可能会损坏器件。在超出推荐的工作条件的情况下,该器件可能无法正常工作,所以不建议
让器件在这些条件下长期工作。此外,过度暴露在高于推荐的工作条件下,会影响器件的可靠性。绝对最大额定值仅是
应力规格值。
符号
VCC
PD
参数
最小值 最大值 单位
电源
10
mA
mW
°C
内部功耗
存储温度范围
工作温度范围
结温
500
TSTG
TA
-65
-35
+150
+80
°C
TJ
+125
+260
+300
°C
10 秒,SOIC
60 秒,DIP
TL
引脚焊接温度
°C
热性能
符号
参数
典型值 最大值 单位
SOIC
DIP
240
热阻
°C/W
160
JA
© 2003 飞兆半导体公司
www.fairchildsemi.com
RV4141A • Rev. 1.0.8
3
电气特性
ILINE = 1.5mA 且 TA = +25°C,RSET= 650k。
符号
参数
工作条件
最小值 典型值 最大值
单位
电压调节器(引脚 5 至 4)
I2-3 = 11µA
25
25
27
27
29
29
VREG
调节后电压
V
ILINE = 750µA, I2-3 = 9µA
V5-4 = 24V
IQ
静态电流
500
µA
感测放大器(引脚 2 至 3)
VOFF
GBW
tSK
失调电压
增益带宽
压摆率
-200
0
3
200
100
µV
MHz
V/µS
nA
设计值
设计值
设计值
1
IBIAS
输入偏置电流
30
SCR 触发(引脚 7 至 4)
ROUT
VOUT
IOUT
输出电阻
输出电压
输出电流
V7-4 = 开, I2-3 = µA
I2-3 = 9µA
I2-3 = 11µA
3.8
0
4.7
0.1
3.8
600
5.6
10.0
4.5
k
mV
V
3.0
400
µA
V7-4 = 0V, I2-3 = 11µA
参考电压(引脚 3 至 4)
VREF
参考电压
延迟定时器(引脚 8 至 4)
放电/充电比率
延迟时间(1)
延迟电流
ILINE = 750µA
12
13
14
V
1.8
30
2.5
2
3.0
50
µA/µA
ms
I2-3 = 0/11µA
tDLY
IDLY
注意:
C8-4 = 12nF
40
µA
I2-3 = 11µA
1. 延迟时间定义为当瞬时感测电流 (I2-3) 超过 6.5V/RSET 到 SCR 触发电压 V7-6 升到高电平的时间。
© 2003 飞兆半导体公司
www.fairchildsemi.com
RV4141A • Rev. 1.0.8
4
电路工作
(请参阅图 1 和图 3。)
GFCI 应用
连接到引脚 1 到 3 的精度运算放大器感测到感测变压器
的次级中的故障电流流动,将其转换为引脚 1 处的电
压。次级电流与输出电压的比率与反馈电阻成正比,
(请参阅图 3)
GFCI 通过感测火线和零线中电流的差异来检测接地故
障。电流中的差异被假定为故障电流,它会形成从火线到
地的潜在危险路径。因为火线和零线通过感测变压器的中
央,所以仅有差模初级端电流被传输到次级。假定匝数比
是 1:1000,则次级电流为故障电流的 1/1000。RV4141A
的感测放大器将次级电流转换为电压,与两个窗口检测器
中任何一个的参考电压相比。如果故障电流超出了编程时
间延迟期间的设计值,则 RV4141A 会给 SCR 的栅极发
送电流脉冲。
RSET
。
RSET 将感测变压器次级电流转换为引脚 1 处的电压。由
于虚拟接地是由其负反馈环在感测放大器输入端创建的,
所以感测变压器的负担等于 RIN 的值。从变压器角度来
看,RIN 的理想值是 0Ω。这使它像一个电流互感器,误
差极小。然而,使 RIN 等于零会在引脚 1 处形成较大的失
调电压,因为感测放大器的直流增益非常高。应将 RIN 选
择得尽可能高,以便变压器的运行保持得像真正的电流互
感器。RIN 的典型值在 200 和 1000Ω 之间。
检测地线与零线间故障更为困难。RB 表示正常接地故障
电阻。RN 是负荷/零线和接地之间电路的导线电阻。RG
如等式 (1) 所示,最大化 RIN 将使感测放大器输出端处的
直流失调误差最小。引脚 1 处的直流失调电压对跳变电
流误差有直接影响。引脚 1 处的失调电压为:
表示地线与零线间故障条件。根据 UL 943,当 RN
=
0.4Ω,RG = 1.6Ω 时,GFCI 必须跳变,且正常接地故障
为 6mA。
VOS RSET /(RIN RSEC
)
(1)
假定接地故障电流为 5mA,则 1mA 和 4mA 分别通过
RG 和 RN,导致有效的 1mA 故障电流。此电流被感测变
压器检测到,并被感测放大器放大。地线与零线和感测变
压器被 RG、RN,以及零线接地环路相互耦合,在感测放
大器周围产生正反馈环路。这个新建立的反馈回路导致感
测放大器以一定频率震荡,该频率由地线/零线变压器次
级电感和 C4 决定,在 8KHz 时发生。
其中:
VOS = 感测放大器的输入失调电压;
RSET = 反馈电阻;
RIN = 输入电阻;
RSEC = 变压器次级绕组电阻。
感测放大器有 200μV 的指定最大失调电压,以便最小化
跳变电流误差。连接到感测放大器输出端的两个比较器配
置为窗口检测器,其参考值为 -6.5V 和 +6.5V,以引脚 3
为参考。当感测变压器次级 RMS 电流超过 4.6/RSET 时,
窗口检测器的输出启动延迟电路。如果次级电流超出预先
确定的跳变电流的时间大于延迟时间,则会在引脚 7 处
出现电流脉冲,触发 SCR。
C2 用于编程在 SCR 被触发前,显示故障要经过的时
间。有关如何计算 C2 值,请参阅等式 (2)。对于 2ms 延
迟,其典型值是 12nF。RSET 用于设置 GFCI 跳变时的故
障电流。与 1:1000 感测变压器一同使用时,对于设计为
在 5mA 时跳变的 GFCI,其典型值是 1MΩ。
RIN 应该是可能的最高值,以确保从感测变压器流出的可
预测的次级电流。如果 RIN 设置得过高,则变压器磁导率
的正常生产变差会导致次级电流出现器件间的变差。如果
它太低,则在引脚 1 处会出现较大的失调电压误差。此
电压反过来会形成与感测放大器的输入偏置电压成比例的
SCR 阳极直接连接到电磁阀或继电器线圈。SCR 只能在
其阳极比其阴极电压大时触发。
电源电流要求
跳变电流误差。例如,如果 RIN 为 500Ω,RSET
为
RV4141A 通过一个串联限流电阻(称为 RLINE)从线路
直接获得电源;其值在 24k和 91k之间。
1M,RSEC 为 45,且感测放大器的 VOS 为其最大值
200μV;跳变电流误差为 ±5.6%。
控制器 IC 有内置的二极管整流器,因此无需外部功率二
极管。RLINE的推荐值是 24k到 47k, 对于 110V 系
统,以及 47k到 91k,对于 220V 系统。当RLINE是
47k时,电压调节器电流限定为3.6mA。推荐的最大峰
值线路电流(通过 RLINE)是 10mA。
© 2003 飞兆半导体公司
www.fairchildsemi.com
RV4141A • Rev. 1.0.8
5
SCR 阳极直接连接到电磁阀或继电器线圈。它仅能在其
阳极比其阴极更正时跳变。它必须有较高的 dV/dt 额定
值,以确保线路噪音(由会发出电噪音的设备产生)不会
错误触发它。SCR 还必须有小于 200μA 的栅极驱动要
求。C3 是一种噪声滤波器,它可防止高频线路脉冲触发
SCR。继电器电磁阀的响应时间应小于等于 3ms,以满
足 UL 943 的定时要求。
计算 RSET 和 C2 的值
确定标称接地故障跳变电流要求。在北美通常为 5mA,
(117VAC) 在英国和欧洲通常为 22mA (220VAC)。确定防
止误触发所需的最小延迟,一般是 1 到 2ms。提供所需
延迟时间所必需的 C2 的值 :
(2)
C2 6t
其中:
感测变压器和磁芯
C2 单位为 Nf,而 t 是所需的延迟时间,单位 ms。
感测和接地/零线变压器磁芯通常使用高磁导率的层叠钢
环制造。它们的单圈初级由通过其磁芯中心的火线和零线
产生。次级线圈通常是 200 到 1500 圈。可以使用
Magnetic Metals, Inc.生产的变压器,
满足标称接地故障跳变电流规格的 RSET 的值是:
4.6 N
IFAULT COS180(t/P)
RSET
(3)
(www.magmet.com)。
其中:
RSET 以 k
为单位,t 是延迟时间,单位 ms;
P 是线路频率的时间,单位 ms;
I
FAULT 是所需的接地故障跳变电流,单位 mA RMS;
N 是感测变压器次级圈的数量。
注:
2. 此公式假定使用的是理想感测变压器。使用非理想变
压器时,RSET 的计算值可能需要改变,最多达
30%。
图 3. GFI 应用电路
© 2003 飞兆半导体公司
www.fairchildsemi.com
RV4141A • Rev. 1.0.8
6
物理尺寸
.400 10.15
A
.373 9.46
[ ]
.036 [0.9 TYP]
(.092) [Ø2.337]
(.032) [R0.813]
PIN #1
PIN #1
.250±.005 [6.35±0.13]
B
TOP VIEW
OPTION 1
TOP VIEW
OPTION 2
.070 1.78
.310±.010 [7.87±0.25]
.045 1.14
[ ]
.130±.005 [3.3±0.13]
.210 MAX
[5.33]
7° TYP
7° TYP
C
.015 MIN
[0.38]
.021 0.53
.015 0.37
.300
[7.62]
[ ]
.140 3.55
.125
3.17
[ ]
.001[.025]
C
.100
[2.54]
.430 MAX
[10.92]
.060 MAX
[1.52]
NOTES:
A. CONFORMS TO JEDEC REGISTRATION MS-001,
VARIATIONS BA
B. CONTROLING DIMENSIONS ARE IN INCHES
REFERENCE DIMENSIONS ARE IN MILLIMETERS
+.005
-.000
+0.127
-0.000
.010
0.254
[
]
C. DOES NOT INCLUDE MOLD FLASH OR PROTRUSIONS.
MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED
.010 INCHES OR 0.25MM.
D. DOES NOT INCLUDE DAMBAR PROTRUSIONS.
DAMBAR PROTRUSIONS SHALL NOT EXCEED
.010 INCHES OR 0.25MM.
E. DIMENSIONING AND TOLERANCING
PER ASME Y14.5M-1994.
N08EREVG
图 4. 8 引线,塑料双列直插封装 (DIP)
封装图纸是作为一项服务而提供给考虑选用飞兆半导体产品的客户。具体参数可能会有变化,且不会做出相应通知。请注意图纸上的
版本和/或日期,并联系飞兆半导体代表核实或获得最新版本。封装规格并不超出飞兆公司全球范围内的条款与条件,尤其指保修,保修
涵盖飞兆半导体的全部产品。
随时访问飞兆半导体在线封装网页,可以获得最新的封装图:
http://www.fairchildsemi.com/packaging/。
© 2003 飞兆半导体公司
www.fairchildsemi.com
RV4141A • Rev. 1.0.8
7
物理尺寸
5.00
4.80
A
0.65
3.81
8
5
B
1.75
6.20
5.80
4.00
3.80
5.60
1
4
PIN ONE
INDICATOR
1.27
1.27
(0.33)
M
0.25
C B A
LAND PATTERN RECOMMENDATION
SEE DETAIL A
0.25
0.10
0.25
0.19
C
1.75 MAX
0.10
C
0.51
0.33
OPTION A - BEVEL EDGE
0.50
0.25
x 45°
GAGE PLANE
R0.10
R0.10
OPTION B - NO BEVEL EDGE
0.36
NOTES: UNLESS OTHERWISE SPECIFIED
8°
0°
0.90
A) THIS PACKAGE CONFORMS TO JEDEC
MS-012, VARIATION AA, ISSUE C,
B) ALL DIMENSIONS ARE IN MILLIMETERS.
C) DIMENSIONS DO NOT INCLUDE MOLD
FLASH OR BURRS.
SEATING PLANE
(1.04)
0.406
DETAIL A
D) LANDPATTERN STANDARD: SOIC127P600X175-8M.
E) DRAWING FILENAME: M08AREV13
SCALE: 2:1
图 5. 8 引线,塑料小外形集成电路 (SOIC)
封装图纸是作为一项服务而提供给考虑选用飞兆半导体产品的客户。具体参数可能会有变化,且不会做出相应通知。请注意图纸上的
版本和/或日期,并联系飞兆半导体代表核实或获得最新版本。封装规格并不超出飞兆公司全球范围内的条款与条件,尤其指保修,保修
涵盖飞兆半导体的全部产品。
随时访问飞兆半导体在线封装网页,可以获得最新的封装图:
http://www.fairchildsemi.com/packaging/。
© 2003 飞兆半导体公司
www.fairchildsemi.com
RV4141A • Rev. 1.0.8
8
© 2003 飞兆半导体公司
www.fairchildsemi.com
RV4141A • Rev. 1.0.8
9
ON Semiconductor and
are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.
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