SA571_技术文档

SA571

Compandor

The SA571 is a versatile low cost dual gain control circuit in which

either channel may be used as a dynamic range compressor or

expandor. Each channel has a full−wave rectifier to detect the average

value of the signal, a linerarized temperature−compensated variable

gain cell, and an operational amplifier.

The SA571 is well suited for use in cellular radio and radio

communications systems, modems, telephone, and satellite

broadcast/receive audio systems.

http://onsemi.com

MARKING

DIAGRAMS

Features

16

• Complete Compressor and Expandor in one IChip

• Temperature Compensated

• Greater than 110 dB Dynamic Range

• Operates Down to 6.0 VDC

• System Levels Adjustable with External Components

• Distortion may be Trimmed Out

16

1

SA571D

AWLYYWWG

SOIC−16 WB

D SUFFIX

CASE 751G

1

• Dynamic Noise Reduction Systems

• Voltage Controlled Amplifier

16

1

• Pb−Free Packages are Available*

16

SA571N

AWLYYWWG

1

Applications

PDIP−16

N SUFFIX

CASE 648

• Cellular Radio

• High Level Limiter

• Low Level Expandor − Noise Gate

• Dynamic Filters

A

= Assembly Location

= Wafer Lot

= Year

= Work Week

= Pb−Free Package

WL

YY

WW

G

• CD Player

PIN CONNECTIONS

D, and N Packages*

1

2

3

4

5

6

7

8

16

15

14

13

12

11

10

9

RECT CAP 1

RECT IN 1

RECT CAP 2

RECT IN 2

DG CELL IN 2

DG CELL IN 1

V

CC

GND

INV. IN 2

INV. IN 1

RES. R 1

RES. R 2

3

OUTPUT 1

OUTPUT 2

THD TRIM 1

THD TRIM 2

TOP VIEW

*SOL − Released in Large SO Package Only.

ORDERING INFORMATION

See detailed ordering and shipping information in the package

dimensions section on page 9 of this data sheet.

*For additional information on our Pb−Free strategy and soldering details, please

download the ON Semiconductor Soldering and Mounting Techniques

Reference Manual, SOLDERRM/D.

©

Semiconductor Components Industries, LLC, 2006

1

Publication Order Number:

March, 2006 − Rev. 4

SA571/D

SA571

THD TRIM

INVERTER IN

R

3

R 20kW

3

DG IN

R 20kW

2

VARIABLE

GAIN

−

+

OUTPUT

V

REF

R 30kW

4

1.8V

RECT IN

R 10kW

1

RECTIFIER

RECT CAP

Figure 1. Block Diagram

MAXIMUM RATINGS

Rating

Symbol

Value

18

Unit

VDC

°C

Maximum Operating Voltage

V

CC

Operating Ambient Temperature Range

Operating Junction Temperature

Power Dissipation

T

A

−40 to +85

150

T

°C

J

P

400

mW

°C/W

D

Thermal Resistance, Junction−to−Ambient

R

q

JA

N Package

D Package

75

105

Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the

Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect

device reliability.

http://onsemi.com

2

SA571

ELECTRICAL CHARACTERISTICS (V = +15 V, T = 25°C, unless otherwise noted)

CC

A

Characteristic

Supply Voltage

Symbol

Test Conditions

Min

6.0

−

Typ

−

Max

18

4.8

−

Unit

V

−

CC

Supply Current

I

No Signal

4.2

−

mA

V/ms

%

Output Current Capability

Output Slew Rate

I

−

20

−

OUT

SR

.5

−

Gain Cell Distortion (Note 2)

Untrimmed

Trimmed

−

0.5

0.1

2.0

Resistor Tolerance

−

1.65

−

5

1.8

90

15

1.95

150

60

%

V

Internal Reference Voltage

Output DC Shift (Note 3)

Expandor Output Noise

Untrimmed

mV

No Signal, 15 Hz−20 kHz

(Note 1)

−

20

Unity Gain Level (Note 5)

Gain Change (Notes 2 and 4)

Reference Drift (Note 4)

Resistor Drift (Note 4)

1.0 kHz

−1.5

−

0

+1.5

dBm

dB

−

0.1

−

+20, −50

−

+2.0, −25

+10, −12

mV

%

−40°C to +85°C

Rectifier Input,

−

Tracking Error

−

dB

(Measured Relative to Value at Unity Gain)

V

= +6.0 V

CC

Equals [V − V (unity gain)] dB − V dBm

V = +6.0 dBm, V = 0 dB

V = −30 dBm, V = 0 dB

+0.2

O

2

1

−1.0, +1.5

−

Channel Separation

1. Input to V and V grounded.

−

60

dB

1

2

2. Measured at 0 dBm, 1.0 kHz.

3. Expandor AC input change from no signal to 0 dBm.

4. Relative to value at T = 25°C.

A

5. 0 dBm = 775 mV

.

RMS

http://onsemi.com

3

SA571

Circuit Description

as brought out externally. A resistor, R , is brought out from

3

The SA571 compandor building blocks, as shown in the

block diagram, are a full−wave rectifier, a variable gain cell,

an operational amplifier and a bias system. The arrangement

of these blocks in the IC result in a circuit which can perform

well with few external components, yet can be adapted to

many diverse applications.

the summing node and allows compressor or expander gain

to be determined only by internal components.

The output stage is capable of 20 mA output current.

This allows a +13 dBm (3.5 V ) output into a 300 W load

RMS

which, with a series resistor and proper transformer, can

result in +13 dBm with a 600 W output impedance.

A bandgap reference provides the reference voltage for all

summing nodes, a regulated supply voltage for the rectifier

and DG cell, and a bias current for the DG cell. The low

tempco of this type of reference provides very stable biasing

over a wide temperature range.

The typical performance characteristics illustration

shows the basic input−output transfer curve for basic

compressor or expander circuits.

The full−wave rectifier rectifies the input current which

flows from the rectifier input, to an internal summing node

which is biased at V . The rectified current is averaged on

REF

an external filter capacitor tied to the C

terminal, and

RECT

the average value of the input current controls the gain of the

variable gain cell. The gain will thus be proportional to the

average value of the input signal for capacitively−coupled

voltage inputs as shown in the following equation. Note that

for capacitively−coupled inputs there is no offset voltage

capable of producing a gain error. The only error will come

from the bias current of the rectifier (supplied internally)

which is less than 0.1 mA.

+20

+10

0

|V_IN* V_REF| avg

−10

−20

−30

−40

−50

−60

−70

−80

G T

R₁

or

| V_IN| avg

G T

R₁

The speed with which gain changes to follow changes in

input signal levels is determined by the rectifier filter

capacitor. A small capacitor will yield rapid response but

will not fully filter low frequency signals. Any ripple on the

gain control signal will modulate the signal passing through

the variable gain cell. In an expander or compressor

application, this would lead to third harmonic distortion, so

there is a trade−off to be made between fast attack and decay

times and distortion. For step changes in amplitude, the

change in gain with time is shown by this equation.

−40 −30 −20 −10

0

+10

COMPRESSOR OUTPUT LEVEL

OR

EXPANDOR INPUT LEVEL (dBm)

Figure 2. Basic Input−Output Transfer Curve

G(t) + (G_initial* G_final) e^*t) G_final

t

V

= 15V

CC

t + 10kW C_RECT

10mF

20kW

0.1mF

The variable gain cell is a current−in, current−out device

13

with the ratio I

/I controlled by the rectifier. I is the

OUT IN

IN

6, 11

7, 10

current which flows from the DG input to an internal

summing node biased at V . The following equation

REF

2.2mF

20kW

applies for capacitively−coupled inputs. The output current,

DG

V

−

+

1

V

O

I

, is fed to the summing node of the op amp.

OUT

3, 14

V_IN* V_REF

V_IN

R₂

I_IN

+

V

R₂

REF

2.2mF

10kW

A compensation scheme built into the DG cell

V

2

compensates for temperature and cancels out odd harmonic

distortion. The only distortion which remains is even

harmonics, and they exist only because of internal offset

voltages. The THD trim terminal provides a means for

nulling the internal offsets for low distortion operation.

The operational amplifier (which is internally

2, 15

30kW

5, 12

8.2kW

4

1, 16

8, 9

200pF

2.2mF

compensated) has the non−inverting input tied to V , and

the inverting input connected to the DG cell output as well

REF

Figure 3. Typical Test Circuit

http://onsemi.com

4

SA571

INTRODUCTION

Much interest has been expressed in high performance

electronic gain control circuits. For non−critical

requires a simple full−wave averaging rectifier with good

accuracy, since the rectifier accuracy determines the (input)

output level tracking accuracy. The gain cell determines the

distortion and noise characteristics, and the phone system

specifications here are very loose. These specs could have

been met with a simple Operational Transconductance

Multiplier, or OTA, but the gain of an OTA is proportional

to temperature and this is very undesirable. Therefore, a

linearized transconductance multiplier was designed which

is insensitive to temperature and offers low noise and low

distortion performance. These features make the circuit

useful in audio and data systems as well as in

telecommunications systems.

applications,

an

integrated

circuit

operational

transconductance amplifier can be used, but when

high−performance is required, one has to resort to complex

discrete circuitry with many expensive, well−matched

components. This paper describes an inexpensive integrated

circuit, the SA571 Compandor, which offers a pair of high

performance gain control circuits featuring low distortion

(<0.1%), high signal−to−noise ratio (90 dB), and wide

dynamic range (110 dB).

Circuit Background

The SA571 Compandor was originally designed to satisfy

the requirements of the telephone system. When several

telephone channels are multiplexed onto a common line, the

resulting signal−to−noise ratio is poor and companding is

used to allow a wider dynamic range to be passed through

the channel. Figure 4 graphically shows what a compandor

can do for the signal−to−noise ratio of a restricted dynamic

range channel. The input level range of +20 to −80 dB is

shown undergoing a 2−to−1 compression where a 2.0 dB

input level change is compressed into a 1.0 dB output level

change by the compressor. The original 100 dB of dynamic

range is thus compressed to a 50 dB range for transmission

Basic Hook−up and Operation

Figure 5 shows the block diagram of one half of the chip,

(there are two identical channels on the IC). The full−wave

averaging rectifier provides a gain control current, I , for the

G

variable gain (DG) cell. The output of theDG cell is a current

which is fed to the summing node of the operational

amplifier. Resistors are provided to establish circuit gain and

set the output DC bias.

The circuit is intended for use in single power supply

systems, so the internal summing nodes must be biased at

some voltage above ground. An internal band gap voltage

reference provides a very stable, low noise 1.8 V reference

through

a

restricted dynamic range channel.

A

denoted V . The non−inverting input of the op amp is tied

REF

complementary expansion on the receiving end restores the

original signal levels and reduces the channel noise by as

much as 45 dB.

to V , and the summing nodes of the rectifier and DG cell

REF

(located at the right of R and R ) have the same potential.

1

2

The THD trim pin is also at the V

potential.

REF

The significant circuits in a compressor or expander are

the rectifier and the gain control element. The phone system

THD TRIM

R

3

INV

IN

8,9

5,12

OUTPUT

LEVEL

INPUT

LEVEL

+20

6,11

R

3

G

IN

20kW

R

−20

0dB

2

OUTPUT

7,10

DG

−

0dB

3,14

RECT

V

20kW

R

REF

+

1.8V

4

IG

30kW

IN

R

1

−40

−80

−40

−80

V

PIN 13

CC

NOISE

10kW

2,15

1,16

GND PIN 4

C

RECT

Figure 4. Restricted Dynamic Range Channel

Figure 5. Chip Block Diagram (1 of 2 Channels)

http://onsemi.com

5

SA571

R

2

Figure 6 shows how the circuit is hooked up to realize an

DG

expandor. The input signal, V , is applied to the inputs of

IN

both the rectifier and the DG cell. When the input signal

drops by 6.0 dB, the gain control current will drop by a factor

of 2, and so the gain will drop 6.0 dB. The output level at

R

1

*

C

*

C

RECT

F

*

R

DC

R

V

OUT

will thus drop 12 dB, giving us the desired 2−to−1

DC

expansion.

*

C

DC

C

IN

R

3

V

OUT

−

R

3

V

IN

+

V

REF

R

4

*C

IN1

R

2

1

2

DG

−

+

R₁R₂I_B

V

NOTE: GAIN + ǒ Ǔ

OUT

V

IN

2R₃V_INavg

R

4

I

= 140mA

B

*C

IN2

V

REF

R

1

*EXTERNAL COMPONENTS

Figure 7. Basic Compressor

*C

RECT

Circuit Details − Rectifier

Figure 8 shows the concept behind the full−wave

averaging rectifier. The input current to the summing node

2

2 R₃V_IN(avg)

R₁R₂I_B

NOTE:

_{GAIN +}ǒ

Ǔ

I

= 140mA

of the op amp, V /R , is supplied by the output of the op

B

IN 1

amp. If we can mirror the op amp output current into a

unipolar current, we will have an ideal rectifier. The output

*EXTERNAL COMPONENTS

Figure 6. Basic Expander

current is averaged by R , CR, which set the averaging time

5

constant, and then mirrored with a gain of 2 to become I ,

the gain control current.

G

Figure 7 shows the hook−up for a compressor. This is

essentially an expandor placed in the feedback loop of the op

amp. The DG cell is setup to provide AC feedback only, so

V+

I = V / R

IN

1

a separate DC feedback loop is provided by the two R and

DC

C

. The values of R will determine the DC bias at the

DC

R

1

output of the op amp. The output will bias to:

−

+

V

R_DC1) R_DC2

IN

_{DC +}ǒ_{1 )}

Ǔ

V_OUT

V_REF

R

10kW

5

R₄

C

R

I

G

R_DCTOT

_{DC +}ǒ_{1 )}Ǔ_1.8V

V_OUT

30kW

The output of the expander will bias up to:

R₃

R₄

_{DC +}ǒ_{1 )}Ǔ

V_OUT

V_REF

Figure 8. Rectifier Concept

20kW

30kW

_{DC +}ǒ_{1 )}Ǔ_{1.8V + 3.0V}

V_OUT

The output will bias to 3.0 V when the internal resistors are

used. External resistors may be placed in series with R ,

3

(which will affect the gain), or in parallel with R to raise the

4

DC bias to any desired value.

http://onsemi.com

6

SA571

Figure 9 shows the rectifier circuit in more detail. The op

amp is a one−stage op amp, biased so that only one output

device is on at a time. The non−inverting input, (the base of

the error of the input bias current. For highest accuracy, the

rectifier should be coupled capacitively. At high input levels

the b of the PNP Q will begin to suffer, and there will be an

6

Q ), which is shown grounded, is actually tied to the internal

increasing error until the circuit saturates. Saturation can be

avoided by limiting the current into the rectifier input to

250 mA. If necessary, an external resistor may be placed in

1

1.8 V, V . The inverting input is tied to the op amp output,

REF

(the emitters of Q and Q ), and the input summing resistor

5

6

R . The single diode between the bases of Q and Q assures

series with R to limit the current to this value. Figure 10

1

5

6

1

that only one device is on at a time. To detect the output

current of the op amp, we simply use the collector currents

shows the rectifier accuracy vs. input level at a frequency of

1.0 kHz.

of the output devices Q and Q . Q will conduct when the

5

6

+1

0

input swings positive and Q conducts when the input

5

swings negative. The collector currents will be in error by

the a of Q or Q on negative or positive signal swings,

5

6

respectively. ICs such as this have typical NPN b’s of 200

and PNP b’s of 40. The a’s of 0.995 and 0.975 will produce

errors of 0.5% on negative swings and 2.5% on positive

swings. The 1.5% average of these errors yields a mere 0.13

dB gain error.

−1

−40

−20

0

RECTIFIER INPUT dBm

V+

Figure 10. Rectifier Accuracy

Q

3

7

At very high frequencies, the response of the rectifier will

fall off. The roll−off will be more pronounced at lower input

levels due to the increasing amount of gain required to

Q

4

Q

5

R

10kW

1

D

1

switch between Q or Q conducting. The rectifier

5

6

V

Q Q

1

IN

2

frequency response for input levels of 0 dBm, −20 dBm, and

−40 dBm is shown in Figure 11. The response at all three

levels is flat to well above the audio range.

R

S

10kW

Q

6

Q

8

Q

I

9

1

2

C

R

V−

INPUT = 0dBm

0

V

_INavg

R 1

−20dBm

NOTE:

I_G+ 2

3

−40dBm

Figure 9. Simplified Rectifier Schematic

At very low input signal levels the bias current of Q ,

(typically 50 nA), will become significant as it must be

2

10k

1MEG

FREQUENCY (Hz)

supplied by Q . Another low level error can be caused by DC

5

coupling into the rectifier. If an offset voltage exists between

Figure 11. Rectifier Frequency Response vs.

Input Level

the V input pin and the base of Q , an error current of

IN

2

V

OS

/R will be generated. A mere 1.0 mV of offset will

1

cause an input current of 100 nA which will produce twice

http://onsemi.com

7

SA571

Variable Gain Cell

Figure 12 is a diagram of the variable gain cell. This is a

This equation is linear and temperature−insensitive, but it

assumes ideal transistors.

linearized two−quadrant transconductance multiplier. Q ,

If the transistors are not perfectly matched, a parabolic,

non−linearity is generated, which results in second

harmonic distortion. Figure 13 gives an indication of the

magnitude of the distortion caused by a given input level and

offset voltage. The distortion is linearly proportional to the

magnitude of the offset and the input level. Saturation of the

gain cell occurs at a +8 dBm level. At a nominal operating

level of 0 dBm, a 1.0 mV offset will yield 0.34% of second

harmonic distortion. Most circuits are somewhat better than

this, which means our overall offsets are typically about mV.

The distortion is not affected by the magnitude of the gain

control current, and it does not increase as the gain is

changed. This second harmonic distortion could be

eliminated by making perfect transistors, but since that

would be difficult, we have had to resort to other methods.

A trim pin has been provided to allow trimming of the

internal offsets to zero, which effectively eliminated second

harmonic distortion. Figure 14 shows the simple trim

network required.

1

Q and the op amp provide a predistorted drive signal for the

2

gain control pair, Q and Q . The gain is controlled by I and

3

4

G

a current mirror provides the output current.

V+

I

1

140mA

−

+

R

2

20k

Q

1

2

4

3

V

IN

I

IN

I (= 2I )

280mA

I

2

1

G

V−

I_IN

4

I_G

I₁

I_GV_IN

I₂R₂

I_OUT

+

NOTE:

3

4mV

Figure 12. Simplified DG Cell Schematic

3mV

2mV

1mV

2

The op amp maintains the base and collector of Q at

1

ground potential (V ) by controlling the base of Q . The

REF

2

.34

input current I (= V /R ) is thus forced to flow through

IN

2

−6

0

+6

Q along with the current I , so I = I + I . Since I has

1

C1

1

IN

2

INPUT LEVEL (dBm)

been set at twice the value of I , the current through Q is:

1

2

Figure 13. DG Cell Distortion vs. Offset Voltage

I₂− (I₁+ I_IN) = I₁− I_IN= I_C2

.

The op amp has thus forced a linear current swing between

Q and Q by providing the proper drive to the base of Q .

This drive signal will be linear for small signals, but very

non−linear for large signals, since it is compensating for the

1

2

V

CC

non−linearity of the differential pair, Q and Q , under large

1

2

R

signal conditions.

The key to the circuit is that this same predistorted drive

signal is applied to the gain control pair, Q and Q . When

3.6V

6.2kW

3

4

20kW

two differential pairs of transistors have the same signal

applied, their collector current ratios will be identical

regardless of the magnitude of the currents. This gives us:

To THD Trim

≈200pF

I_C1

I_C2

I_C4

I_C3

I₁) I_IN

I₁* I_IN

+

Figure 14. THD Trim Network

plus the relationships I = I + I and I

= I − I will

C4 C3

G

C3

C4

OUT

yield the multiplier transfer function,

I_G

I₁

I_G

V_IN

I_OUT

+

I_IN+

R₂I₁

http://onsemi.com

8

SA571

V

Figure 15 shows the noise performance of the DG cell.

CC

The maximum output level before clipping occurs in the

gain cell is plotted along with the output noise in a 20 kHz

bandwidth. Note that the noise drops as the gain is reduced

for the first 20 dB of gain reduction. At high gains, the signal

to noise ratio is 90 dB, and the total dynamic range from

maximum signal to minimum noise is 110 dB.

R−SELECT FOR

3.6V

100kW

TO PIN 3 OR 14

470kW

+20

0

Figure 16. Control Signal Feedthrough

MAXIMUM

SIGNAL LEVEL

−20

−40

90dB

Operation Amplifier

110dB

The main op amp shown in the chip block diagram is

equivalent to a 741 with a 1.0 MHz bandwidth. Figure 17

shows the basic circuit. Split collectors are used in the input

−60

pair to reduce g , so that a small compensation capacitor of

M

−80

just 10 pF may be used. The output stage, although capable

of output currents in excess of 20 mA, is biased for a low

quiescent current to conserve power. When driving heavy

loads, this leads to a small amount of crossover distortion.

NOISE IN

20kHz BW

−100

−40

−20

VCA GAIN (0dB)

0

Figure 15. Dynamic Range

I

2

1

Q

6

Control signal feedthrough is generated in the gain cell by

imperfect device matching and mismatches in the current

D

1

Q

2

1

+IN

−IN

OUT

2

sources, I and I . When no input signal is present, changing

1

2

C

I

will cause a small output signal. The distortion trim is

G

Q

2

effective in nulling out any control signal feedthrough, but

in general, the null for minimum feedthrough will be

different than the null in distortion. The control signal

feedthrough can be trimmed independently of distortion by

tying a current source to the DG input pin. This effectively

Q

4

Q

3

Figure 17. Operational Amplifier

trims I . Figure 16 shows such a trim network.

1

ORDERING INFORMATION

†

Device

SA571D

Description

Temperature Range

−40 to +85°C

Shipping

16−Pin Plastic Small Outline (SO−16 WB) Package

47 Units / Rail

SA571DG

16−Pin Plastic Small Outline (SO−16 WB) Package

(Pb−Free)

−40 to +85°C

SA571DR2

16−Pin Plastic Small Outline (SO−16 WB) Package

−40 to +85°C

1000 / Tape & Reel

SA571DR2G

16−Pin Plastic Small Outline (SO−16 WB) Package

(Pb−Free)

SA571N

16−Pin Plastic Dual In−Line Package (PDIP−16)

−40 to +85°C

25 Units / Rail

SA571NG

16−Pin Plastic Dual In−Line Package (PDIP−16)

(Pb−Free)

†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging

Specifications Brochure, BRD8011/D.

http://onsemi.com

9

SA571

PACKAGE DIMENSIONS5

SOIC−16 WB

D SUFFIX

CASE 751G−03

ISSUE C

NOTES:

1. DIMENSIONS ARE IN MILLIMETERS.

2. INTERPRET DIMENSIONS AND TOLERANCES

PER ASME Y14.5M, 1994.

3. DIMENSIONS D AND E DO NOT INLCUDE

MOLD PROTRUSION.

A

D

q

16

9

4. MAXIMUM MOLD PROTRUSION 0.15 PER SIDE.

5. DIMENSION B DOES NOT INCLUDE DAMBAR

PROTRUSION. ALLOWABLE DAMBAR

PROTRUSION SHALL BE 0.13 TOTAL IN

EXCESS OF THE B DIMENSION AT MAXIMUM

MATERIAL CONDITION.

MILLIMETERS

DIM MIN

2.35

A1 0.10

MAX

2.65

0.25

0.49

0.32

A

1

8

B

C

D

E

e

H

h

L

q

0.35

0.23

10.15 10.45

7.40 7.60

1.27 BSC

10.05 10.55

B

16X B

M

S

0.25

T A

B

0.25

0.50

0

0.75

0.90

7

_

SEATING

PLANE

14X

e

C

T

PDIP−16

N SUFFIX

CASE 648−08

ISSUE T

NOTES:

−A−

1. DIMENSIONING AND TOLERANCING PER

ANSI Y14.5M, 1982.

2. CONTROLLING DIMENSION: INCH.

3. DIMENSION L TO CENTER OF LEADS

WHEN FORMED PARALLEL.

4. DIMENSION B DOES NOT INCLUDE

MOLD FLASH.

16

1

9

B

S

8

5. ROUNDED CORNERS OPTIONAL.

INCHES

DIM MIN MAX

0.740 0.770 18.80 19.55

MILLIMETERS

F

C

L

MIN MAX

A

B

C

D

F

0.250 0.270

0.145 0.175

0.015 0.021

6.35

3.69

0.39

1.02

6.85

4.44

0.53

1.77

SEATING

PLANE

−T−

0.040

0.70

G

H

J

K

L

0.100 BSC

2.54 BSC

1.27 BSC

K

M

0.050 BSC

0.008 0.015

0.110 0.130

0.295 0.305

H

J

0.21

0.38

3.30

7.74

10

G

2.80

7.50

0

D 16 PL

M

0.25 (0.010)

T A

M

S

0

10

_

0.020 0.040

0.51

1.01

http://onsemi.com

10

SA571

ON Semiconductor and

are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice

to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability

arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.

“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All

operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights

nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications

intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer

purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates,

and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death

associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal

Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.

PUBLICATION ORDERING INFORMATION

LITERATURE FULFILLMENT:

N. American Technical Support: 800−282−9855 Toll Free

USA/Canada

ON Semiconductor Website: http://onsemi.com

Order Literature: http://www.onsemi.com/litorder

Literature Distribution Center for ON Semiconductor

P.O. Box 61312, Phoenix, Arizona 85082−1312 USA

Phone: 480−829−7710 or 800−344−3860 Toll Free USA/Canada

Fax: 480−829−7709 or 800−344−3867 Toll Free USA/Canada

Email: orderlit@onsemi.com

Japan: ON Semiconductor, Japan Customer Focus Center

2−9−1 Kamimeguro, Meguro−ku, Tokyo, Japan 153−0051

Phone: 81−3−5773−3850

For additional information, please contact your

local Sales Representative.

SA571/D

http://onsemi.com

11


型号：	SA571
厂家：	ONSEMI
描述：	Compandor 扩
文件：	总11页 (文件大小：105K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

SA571 [ONSEMI]

相关型号：

SA5711

SA5711

SA5711B

SA571D

SA571D

SA571D

SA571D-T

SA571D-T

SA571DG

SA571DR2

SA571DR2G

SA571F