SA572N [ONSEMI]
可编程模拟扩展器;
| 型号： | SA572N |
| 厂家： | 
ONSEMI |
| 描述： | 可编程模拟扩展器 光电二极管 信号电路 模拟计算功能 |
| 文件： | 总12页 (文件大小：218K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
SA572
Programmable Analog
Compandor
The SA572 is a dual-channel, high-performance gain control
circuit in which either channel may be used for dynamic range
compression or expansion. Each channel has a full-wave rectifier to
detect the average value of input signal, a linearized, temperature-
compensated variable gain cell (ꢀG) and a dynamic time constant
buffer. The buffer permits independent control of dynamic attack and
recovery time with minimum external components and improved low
frequency gain control ripple distortion over previous compandors.
The SA572 is intended for noise reduction in high-performance
audio systems. It can also be used in a wide range of communication
systems and video recording applications.
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MARKING DIAGRAMS
16
16
SA572D
1
AWLYYWWG
SOIC−16 WB
D SUFFIX
Features
CASE 751G
1
• Independent Control of Attack and Recovery Time
• Improved Low Frequency Gain Control Ripple
• Complementary Gain Compression and Expansion with
External Op Amp
16
1
SA572N
AWLYYWWG
16
16
• Wide Dynamic Range − Greater than 110 dB
• Temperature-Compensated Gain Control
• Low Distortion Gain Cell
1
PDIP−16
N SUFFIX
CASE 648
16
• Low Noise − 6.0 ꢁ V Typical
• Wide Supply Voltage Range − 6.0 V-22 V
• System Level Adjustable with External Components
• Pb−Free Packages are Available*
SA
572
ALYW G
1
G
TSSOP−16
DTB SUFFIX
CASE 948F
Applications
1
• Dynamic Noise Reduction System
• Voltage Control Amplifier
• Stereo Expandor
• Automatic Level Control
• High-Level Limiter
• Low-Level Noise Gate
• State Variable Filter
A
= Assembly Location
= Wafer Lot
= Year
WL
YY
WW
= Work Week
G or G = Pb−Free Package
(Note: Microdot may be in either location)
PIN CONNECTIONS
D, N, DTB Packages*
16
15
14
13
12
V
TRACK TRIM A
RECOV. CAP A
1
2
CC
TRACK TRIM B
RECT. IN A
ATTACK CAP A
ꢀG OUT A
3
4
RECOV. CAP B
RECT. IN B
5
6
ATTACK CAP B
THD TRIM A
11 ꢀG OUT B
ꢀ
G
I
N
A
7
8
10 THD TRIM B
9
ꢀ
G
I
N
B
GND
*D package released in large SO (SOL) package only.
*For additional information on our Pb−Free strategy and soldering details, please
downloadthe ON Semiconductor Soldering and Mounting Techniques Reference
Manual, SOLDERRM/D.
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 10 of this data sheet.
©
Semiconductor Components Industries, LLC, 2006
1
Publication Order Number:
March, 2006 − Rev. 2
SA572/D
SA572
R
1
(5,11)
(7,9)
6.8k
ꢂ
ꢀG
(6,10)
500
Ω
GAIN CELL
(1,15)
−
−
(3,13)
+
+
10k
ꢂ
BUFFER
270
10k
ꢂ
RECTIFIER
Ω
(16)
P.S.
(8)
(4,12)
(2,14)
Figure 1. Block Diagram
PIN FUNCTION DESCRIPTION
Pin
Symbol
TRACK TRIM A
RECOV. CAP A
RECT. IN A
ATTACK CAP A
ꢀG OUT A
Description
1
Tracking Trim A
2
Recovery Capacitor A
Rectifier A Input
3
4
Attack Capacitor A
5
Variable Gain Cell A Output
Total Harmonic Distortion Trim A
Variable Gain Cell A Input
Ground
6
THD TRIM A
ꢀG IN A
7
8
GND
9
ꢀ
G
I
N
B
Variable Gain Cell B Input
Total Harmonic Distortion Trim B
Variable Gain Cell B Output
Attack Capacitor B
10
11
12
13
14
15
16
THD TRIM B
ꢀG OUT B
ATTACK CAP B
RECT. IN B
RECOV. CAP B
TRACK TRIM B
Rectifier B Input
Recovery Capacitor B
Tracking Trim B
V
CC
Positive Power Supply
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2
SA572
MAXIMUM RATINGS
Rating
Symbol
Value
22
Unit
Supply Voltage
V
CC
V
DC
Operating Temperature Range
Operating Junction Temperature
Power Dissipation
T
−40 to +85
150
°C
A
T
°C
J
P
D
500
mW
°C/W
Thermal Resistance, Junction−to−Ambient
N Package
R
ꢃ
75
105
133
JA
D Package
DTB Package
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
RecommendedOperating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
DC ELECTRICAL CHARACTERISTICS Standard test conditions, V = 15 V, T = 25°C; Expandor mode (see Test Circuit). Input
CC
A
signals at unity gain level (0 dB) = 100 mV
at 1.0 kHz; V = V ; R = 3.3 kꢂ; R = 17.3 kꢂ ꢄ unless otherwise noted.
RMS
1 2 2 3
Characteristic
Symbol
Test Conditions
Min
6.0
−
Typ
−
Max
22
Unit
Supply Voltage
V
−
No Signal
−
V
DC
CC
CC
Supply Current
I
−
6.3
2.7
mA
Internal Voltage Reference
V
R
2.3
2.5
V
DC
Total Harmonic Distortion (Untrimmed)
Total Harmonic Distortion (Trimmed)
Total Harmonic Distortion (Trimmed)
THD
THD
THD
1.0 kHz, C = 1.0 ꢁ F
−
−
−
0.2
0.05
0.25
1.0
−
−
%
%
%
A
1.0 kHz, C = 10 ꢁ F
R
100 Hz
No Signal Output Noise
Input to V and V
−
6.0
25
ꢁ
V
1
2
grounded (20−20 kHz)
DC Level Shift (Untrimmed)
Input change from no
−
"20
"50
mV
signal to 100 mV
RMS
Unity Gain Level
Large-Signal Distortion
Tracking Error
−
−1.5
0
+1.5
3.0
dB
%
V = V = 400 mV
−
0.7
1
2
Rectifier Input
V = +6.0 dB, V = 0 dB
V = −30 dB, V = 0 dB
(Measured relative to value at unity gain) =
[V −V (unity gain)] dB−V dB
−
−
"0.2
"0.5
dB
dB
2
2
1
1
−2.5, +1.6
O
O
2
Channel Crosstalk
200 mV
channel A, measured
output on channel B
into
60
−
−
dB
RMS
Power Supply Rejection Ratio
PSRR
120 Hz
−
70
−
dB
100
ꢂ
1
ꢁ
F
−15V
22ꢁF
+
1%
2.2ꢁF
6.8k
ꢂ
R
3
(7,9)
(5,11)
ꢀ
G
V
1
17.3k
ꢂ
82k
ꢂ
−
5
ꢂ
270pF
(2,14)
(4,12)
NE5234
V
0
2.2k
(6,10)
C
C
= 10ꢁF
= 1ꢁF
R
+
BUFFER
1k
ꢂ
+
2.2ꢁF
(8)
A
(1,15)
2.2ꢁF
3.3k
R
ꢂ
(3,13)
+15V
V
RECTIFIER
2
(16)
+
2
22ꢁF
0.1ꢁF
1%
Figure 2. Test Circuit
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3
SA572
Audio Signal Processing IC Combines VCA and
Fast Attack/Slow Recovery Level Sensor
The novel level sensor which provides gain control
current for the VCA gives lower gain control ripple and
independent control of fast attack, slow recovery dynamic
In high-performance audio gain control applications, it
is desirable to independently control the attack and
recovery time of the gain control signal. This is true, for
example, in compandor applications for noise reduction. In
high end systems the input signal is usually split into two
or more frequency bands to optimize the dynamic behavior
for each band. This reduces low frequency distortion due
to control signal ripple, phase distortion, high frequency
channel overload and noise modulation. Because of the
expense in hardware, multiple band signal processing up to
now was limited to professional audio applications.
With the introduction of the SA572 this high-
performance noise reduction concept becomes feasible for
consumer hi fi applications. The SA572 is a dual channel
response. An attack capacitor C with an internal 10 k
ꢂ
A
resistor R defines the attack time ꢅ . The recovery time
A
A
ꢅ of a tone burst is defined by a recovery capacitor C and
R
R
an internal 10 kꢂ resistor R . Typical attack time of 4.0 ms
R
for the high-frequency spectrum and 40 ms for the low
frequency band can be obtained with 0.1 ꢁ F and 1.0 ꢁ F
attack capacitors, respectively. Recovery time of 200 ms
can be obtained with a 4.7 ꢁ F recovery capacitor for a
100 Hz signal, the third harmonic distortion is improved by
more than 10 dB over the simple RC ripple filter with a
single 1.0 ꢁ F attack and recovery capacitor, while the
attack time remains the same.
The SA572 is assembled in a standard 16-pin dual in-line
plastic package and in oversized SOL package. It operates
over a wide supply range from 6.0 V to 22 V. Supply
current is less than 6.0 mA. The SA572 is designed for
applications from −40°C to +85°C.
gain control IC. Each channel has
a linearized,
temperature-compensated gain cell and an improved level
sensor. In conjunction with an external low noise op amp
for current-to-voltage conversion, the VCA features low
distortion, low noise and wide dynamic range.
BASIC APPLICATIONS
Description
1
2
1
2
1 IG ) 1 IO
IG
*
IO
2
2
The SA572 consists of two linearized, temperature-
compensated gain cells (ꢀG), each with a full-wave
rectifier and a buffer amplifier as shown in the block
diagram. The two channels share a 2.5 V common bias
reference derived from the power supply but otherwise
operate independently. Because of inherent low distortion,
low noise and the capability to linearize large signals, a
wide dynamic range can be obtained. The buffer amplifiers
are provided to permit control of attack time and recovery
time independent of each other. Partitioned as shown in the
block diagram, the IC allows flexibility in the design of
system levels that optimize DC shift, ripple distortion,
tracking accuracy and noise floor for a wide range of
application requirements.
V In ǒ Ǔ* V I
ǒ Ǔ
n
T
T
IS
IS
(eq. 1)
I
2 * I1 * IIN
I1 ) IIN
ǒ Ǔ
IS
ǒ
Ǔ
+ VTIn
* VTIn
IS
VIN
+
where IIN
R1
R1 = 6.8 kꢂ
I1 = 140 ꢁA
I2 = 280 ꢁA
I is the differential output current of the gain cell and I
is the gain control current of the gain cell.
If all transistors Q through Q are of the same size,
O
G
1
4
equation 1 can be simplified to:
Gain Cell
Figure 3 shows the circuit configuration of the gain cell.
2
I2
1
I2
ǒ
Ǔ
(eq. 2)
IO
+
@ IIN @ IG
*
I2 * 2I1 @ IG
Bases of the differential pairs Q -Q and Q -Q are both
1
2
3
4
tied to the output and inputs of OPA A . The negative
The first term of equation 2 shows the multiplier
relationship of a linearized two quadrant transconductance
amplifier. The second term is the gain control feedthrough
due to the mismatch of devices. In the design, this has been
minimized by large matched devices and careful layout.
Offset voltage is caused by the device mismatch and it leads
to even harmonic distortion. The offset voltage can be
trimmed out by feeding a current source within "25 ꢁ A
into the THD trim pin.
1
feedback through Q holds the V of Q -Q and the V
1
BE
1
2
BE
of Q -Q equal. The following relationship can be derived
3
4
from the transistor model equation in the forward active
region.
ꢀ
V
+ ꢀ BE
Q1Q2
B
E
Q3Q4
(VBE = VT IIN IC/IS)
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4
SA572
The residual distortion is third harmonic distortion and
is only 6.0 ꢁ V in the audio spectrum (10 Hz-20 kHz). The
is caused by gain control ripple. In a compandor system,
available control of fast attack and slow recovery improve
ripple distortion significantly. At the unity gain level of
100 mV, the gain cell gives THD (total harmonic
distortion) of 0.17% typ. Output noise with no input signals
output current I must feed the virtual ground input of an
operational amplifier with a resistor from output to
inverting input. The non-inverting input of the operational
O
amplifier has to be biased at V
is DC coupled.
if the output current I
REF
O
V+
1
2
1
2
I
)
I
G
O
I
1
140ꢁA
A1
I
O
−
+
Q
Q
Q
1
2
Q
3
4
R
1
6.8k
ꢂ
I
2
I
G
280ꢁA
V
REF
THD
TRIM
V
IN
Figure 3. Basic Gain Cell Schematic
V
* V
Rectifier
IN
REF
V+
I
+
R
R
2
The rectifier is a full-wave design as shown in Figure 4.
The input voltage is converted to current through the input
resistor R and turns on either Q or Q depending on the
2
5
6
signal polarity. Deadband of the voltage to current
converter is reduced by the loop gain of the gain block A .
If AC coupling is used, the rectifier error comes only from
2
V
+
REF
A2
input bias current of gain block A . The input bias current
is typically about 70 nA. Frequency response of the gain
2
−
Q
5
block A also causes second-order error at high frequency.
2
The collector current of Q is mirrored and summed at the
6
D
collector of Q to form the full wave rectified output
7
5
current I . The rectifier transfer function is:
R
Q
6
VIN * VREF
(eq. 3)
IR
+
R
2
R2
V
IN
If V is AC-coupled, then the equation will be reduced
IN
to:
VIN(AVG)
R2
IRAC
+
The internal bias scheme limits the maximum output
current I to be around 300 ꢁ A. Within a "1.0 dB error
R
band the input range of the rectifier is about 52 dB.
Figure 4. Simplified Rectifier Schematic
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5
SA572
*t
Buffer Amplifier
ꢅ
Ga(t) + (GaINT * GaFNL) e A ) GaFNL
In audio systems, it is desirable to have fast attack time
and slow recovery time for a tone burst input. The fast
attack time reduces transient channel overload but also
causes low-frequency ripple distortion. The low-frequency
ripple distortion can be improved with the slow recovery
time. If different attack times are implemented in
corresponding frequency spectrums in a split band audio
system, high quality performance can be achieved. The
buffer amplifier is designed to make this feature available
with minimum external components. Referring to
Figure 5, the rectifier output current is mirrored into the
GaINT = Initial Gain
GaFNL = Final Gain
ꢅA = RA • CA = 10 kꢂ • CA
where
ꢅ is the attack time constant and R is a 10 kꢂ
A A
internal resistor. Diode D opens the feedback loop of A
for a negative-going signal if the value of capacitor C is
larger than capacitor C . The recovery time depends only
15
3
R
A
on C • R . If the diode impedance is assumed negligible,
R
R
the dynamic gain G (t) for ꢀG is expressed as follows:
R
*t
ꢅ
GR(t) + (GRINT * GRFNL) e R ) GRFNL
input and output of the unipolar buffer amplifier A through
3
Q , Q and Q . Diodes D and D improve tracking
8
9
10
11
12
*t
ꢅ
GR(t) + (GRINT * GRFNL) e R ) GRFNL
accuracy and provide common-mode bias for A . For a
3
positive-going input signal, the buffer amplifier acts like a
ꢅ
R
= R • C = 10 kꢂ • C
R R R
voltage-follower. Therefore, the output impedance of A
3
where ꢅ is the recovery time constant and R is a 10 k
ꢂ
R
R
makes the contribution of capacitor C to attack time
R
internal resistor. The gain control current is mirrored to the
gain cell through Q . The low level gain errors due to input
insignificant. Neglecting diode impedance, the gain Ga(t)
for ꢀG can be expressed as follows:
14
bias current of A and A can be trimmed through the
2
3
tracking trim pin into A with a current source of "3.0 ꢁ A.
3
V+
Q
8
Q
9
Q
10
I
= 2IR
2
Q
Q
17
IR
2
X2
Q
16
10k
ꢂ
V
IN
I
+
R
R
−
D
15
D
13
A3
+
10k
ꢂ
IR
1
X2
Q
14
Q
18
D
11
D
12
C
R
C
A
TRACKING
TRIM
Figure 5. Buffer Amplifier Schematic
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6
SA572
Basic Expandor
buffer A may be necessary if the input is voltage driven
1
Figure 6 shows an application of the circuit as a simple
expandor. The gain expression of the system is given by:
with large source impedance.
The gain cell output current feeds the summing node of
the external OPA A . R and A convert the gain cell output
current to the output voltage. In high-performance
2
3
2
2
R3 @ VIN(AVG)
R2 @ R1
VOUT
VIN
2
I1
(eq. 4)
+ ǒ
Ǔ
@
applications, A has to be low-noise, high-speed and wide
2
band so that the high-performance output of the gain cell
(I1 = 140 ꢁA)
will not be degraded. The non-inverting input of A can be
biased at the low noise internal reference Pin 6 or 10.
2
Both the resistors R and R are tied to internal summing
1
2
nodes. R is a 6.8 kꢂ internal resistor. The maximum input
1
Resistor R is used to bias up the output DC level of A for
4
2
current into the gain cell can be as large as 140 ꢁ A. This
corresponds to a voltage level of 140 ꢁ A•6.8 kꢂ = 952 mV
peak. The input peak current into the rectifier is limited to
300 ꢁ A by the internal bias system. Note that the value of
maximum swing. The output DC level of A is given by:
2
R3
ǒ1 ) Ǔ
R4
R3
R4
(eq. 5)
VOUT DC + VREF
* VB
R can be increased to accommodate higher input level. R
1
2
V
B
can be tied to a regulated power supply for a dual
and R are external resistors. It is easy to adjust the ratio of
3
supply system and be grounded for a single supply system.
sets the attack time constant and C sets the recovery
R /R for desirable system voltage and current levels. A
3
2
C
A
R
small R results in higher gain control current and smaller
2
time constant.
static and dynamic tracking error. However, an impedance
R
4
R
3
+VB
17.3k
ꢂ
−
C
R
1
IN2
(5,11)
(6,10)
A1
ꢀ
G
C
IN1
(7,9)
2.2ꢁF
6.8k
ꢂ
V
V
OUT
+
IN
A2
R
6
2.2ꢁF
V
REF
1k
ꢂ
(2,14)
(4,12)
R
100k
C
1
2.2ꢁF
5
ꢂ
BUFFER
C
2.2ꢁF
IN3
R
2
3.3k
ꢂ
C
A
C
R
1
ꢁF 10ꢁF
(3,13)
(8)
(16)
+V
CC
Figure 6. Basic Expandor Schematic
Basic Compressor
R
, R
, and CDC form a DC feedback for A . The
DC1 DC2 1
Figure 7 shows the hook-up of the circuit as a
compressor. The IC is put in the feedback loop of the OPA
output DC level of A is given by:
1
RDC1 ) RDC2
ǒ1 )
VOUT DC + VREF
Ǔ
(eq. 7)
A . The system gain expression is as follows:
1
R4
1
2
VOUT
VIN
RDC1 ) RDC2
I1
2
R2 @ R1
R3 @ VIN(AVG)
(eq. 6)
+ ǒ
Ǔ
* V @ ǒ
Ǔ
@
B
R4
The zener diodes D and D are used for channel
1
2
(I1 = 140 ꢁA)
overload protection.
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7
SA572
R
DC1
R
DC2
R
4
9.1k
ꢂ
9.1kꢂ
C
DC
10ꢁF
C
2
.1ꢁF
C
IN1
2.2ꢁF
D
1
D
2
V
IN
−
V
OUT
R
17.3k
3
A1
ꢂ
+
C
1
1k
ꢂ
R
5
(6,10)
V
REF
R
1
(7,9)
ꢀ
G
6.8k
ꢂ
C
IN2
2.2ꢁF
(5,11)
(2,14)
(4,12)
C
IN3
2.2ꢁF
BUFFER
C
A
C
R
1
ꢁF
10ꢁF
3.3k
2
ꢂ
R
(3,13)
(8)
(16)
V
CC
Figure 7. Basic Compressor Schematic
Basic Compandor System
pre-emphasis, de-emphasis and equalization are easy to
incorporate. The IC is a versatile functional block to
achieve a high performance audio system. Figure 8 shows
the system level diagram for reference.
The above basic compressor and expandor can be
applied to systems such as tape/disc noise reduction, digital
audio, bucket brigade delay lines. Additional system
design techniques such as bandlimiting, band splitting,
1
2
2
REL LEVEL
dB
ABS LEVEL
dBM
V
RMS
COMPRESSION
IN
EXPANDOR
OUT
3.0 V
+29.54
+11.76
547.6 mV
400 mV
+14.77
+12.0
−3.00
−5.78
100 mV
10 mV
1 mV
0.0
−17.78
−37.78
−20
−40
−60
−57.78
−77.78
100 ꢁV
10 ꢁV
−80
−97.78
Figure 8. SA572 System Level
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8
SA572
C
1
R
1
+
3, 13
2.2 ꢁ F
3.3k
R
X
ATTACK
CAP
RECOVERY
CAP
4, 12
2, 14
7, 9
BUFFER
6.8k
+
+
1 ꢁ F
10 ꢁ F
C
A
C
R
C
2
+
5, 11
R
ꢀ
R
2
2.2 ꢁ F
G
R
R
4
DC1
DC2
9.1k
9.1k
DC
10 ꢁ F
+
100k
C
V+
R
17.3k
3
C
3
+
2
V
IN
−
V
OUT
+
1
DC
2.2 ꢁ F
TO THD
TRIM PIN
OF 572
5532
V
OUT
R
5
3
2.2 ꢁ F
+
+
1k
22 ꢁ F
C
5
V−
PINS 6, 10
Figure 9. Automatic Level Control
Automatic Level Control (ALC)
The output level is calculated using the following
equation:
In the ALC configuration, the variable gain cell is placed
in the feedback loop of the operational amplifier and the
rectifier is connected to the input. As the input amplitude
increases above the crossover point, the overall system
gain decreases proportionally, holding the output
amplitude constant. As the input amplitude decreases
below the crossover point, the overall system gain
increases proportionally, holding the output amplitude at
the same constant level.
R R I
2 1
V
IN
IN
1
ǒV (avg)Ǔ
V
+
OUT_LEVEL
2 R
3
where:
R = 6.8 kꢂ (Internal)
1
R = 3.3 k
ꢂ
2
R = 17.3 k
3
ꢂ
I = 140 ꢁ A
1
V
ꢆ
IN
+
+ 1.11 (for sine waves)
Ǹ
V
(avg)
IN
2 2
R R I
1
2 1
Gain +
2 R V (avg)
IN
3
Note that for very low input levels, ALC may not be
desired and to limit the maximum gain, resistor R has
been added.
X
where:
R = 6.8 kꢂ (Internal)
1
R = 3.3 k
ꢂ
2
R
)R
x
REF
R = 17.3 k
3
ꢂ
1
ǒ V Ǔ · R · I
2
B
I = 140 ꢁ A
1
Gain max. +
2 R
3
The output DC level can be set using the following
equation:
R ^ ((desired max gain) 26 kꢂ) * 10 kꢂ
x
RDC1 ) RDC2
DC + ǒ1 )
Ǔ
VOUT
VREF
R4
where:
R = 100 k
4
ꢂ
R
= R
= 9.1 kꢂ
DC1
DC2
V
REF
= 2.5 V
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9
SA572
ORDERING INFORMATION
Device
Description
Package
TemperatureRange
Shipping†
SA572D
16−Pin Plastic Small Outline Package
SO−16 WB
−40 to +85°C
47 Units / Rail
SA572DG
16−Pin Plastic Small Outline Package
(Pb−Free)
SO−16 WB
−40 to +85°C
47 Units / Rail
SA572DR2
16−Pin Plastic Small Outline Package
SO−16 WB
SO−16 WB
−40 to +85°C
−40 to +85°C
1000 / Tape & Reel
1000 / Tape & Reel
SA572DR2G
16−Pin Plastic Small Outline Package
(Pb−Free)
SA572DTB
16−Pin Thin Shrink Small Outline Package
16−Pin Thin Shrink Small Outline Package
16−Pin Thin Shrink Small Outline Package
16−Pin Thin Shrink Small Outline Package
16−Pin Plastic Dual In−Line Package
TSSOP−16*
TSSOP−16*
TSSOP−16*
TSSOP−16*
PDIP−16
−40 to +85°C
−40 to +85°C
−40 to +85°C
−40 to +85°C
−40 to +85°C
−40 to +85°C
96 Units / Rail
96 Units / Tube
2500 / Tape & Reel
2500 / Tape & Reel
25 Units / Rail
SA572DTBG
SA572DTBR2
SA572DTBR2G
SA572NG
SA572NG
16−Pin Plastic Dual In−Line Package
(Pb−Free)
PDIP−16
25 Units / Rail
†For information on / Tape and reel specifications, including part orientation and / Tape sizes, please refer to our / Tape and Reel Packaging
SpecificationBrochure, BRD8011/D.
*This package is inherently Pb−Free.
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10
SA572
PACKAGE DIMENSIONS
SOIC−16 WB
D SUFFIX
CASE 751G−03
ISSUE C
A
D
NOTES:
q
1. DIMENSIONS ARE IN MILLIMETERS.
2. INTERPRET DIMENSIONS AND TOLERANCES
PER ASME Y14.5M, 1994.
16
9
3. DIMENSIONS D AND E DO NOT INLCUDE
MOLD PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 PER SIDE.
5. DIMENSION B DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.13 TOTAL IN
EXCESS OF THE B DIMENSION AT MAXIMUM
MATERIAL CONDITION.
MILLIMETERS
1
8
DIM MIN
2.35
A1 0.10
MAX
2.65
0.25
0.49
0.32
A
B
16X B
B
C
D
E
e
H
h
L
q
0.35
0.23
10.15 10.45
7.40 7.60
1.27 BSC
10.05 10.55
M
S
S
B
0.25
T
A
0.25
0.50
0
0.75
0.90
7
_
_
SEATING
PLANE
14X
e
C
T
PDIP−16
CASE 648−08
ISSUE T
NOTES:
−A−
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
3. DIMENSION L TO CENTER OF LEADS
WHEN FORMED PARALLEL.
4. DIMENSION B DOES NOT INCLUDE
MOLD FLASH.
5. ROUNDED CORNERS OPTIONAL.
16
1
9
8
B
S
INCHES
DIM MIN MAX
0.740 0.770 18.80 19.55
MILLIMETERS
F
C
L
MIN MAX
A
B
C
D
F
0.250 0.270
0.145 0.175
0.015 0.021
6.35
3.69
0.39
1.02
6.85
4.44
0.53
1.77
SEATING
PLANE
−T−
0.040
0.70
G
H
J
K
L
M
S
0.100 BSC
2.54 BSC
1.27 BSC
K
M
0.050 BSC
0.008 0.015
0.110 0.130
0.295 0.305
H
J
0.21
0.38
3.30
7.74
10
G
2.80
7.50
0
D 16 PL
M
M
0.25 (0.010)
T A
0
10
_
_
_
_
0.020 0.040
0.51
1.01
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11
SA572
PACKAGE DIMENSIONS
TSSOP−16
CASE 948F−01
ISSUE A
NOTES:
16X K REF
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
M
S
S
V
0.10 (0.004)
T
U
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A DOES NOT INCLUDE MOLD
FLASH. PROTRUSIONS OR GATE BURRS.
MOLD FLASH OR GATE BURRS SHALL NOT
EXCEED 0.15 (0.006) PER SIDE.
S
U
0.15 (0.006) T
K
K1
4. DIMENSION B DOES NOT INCLUDE
INTERLEAD FLASH OR PROTRUSION.
INTERLEAD FLASH OR PROTRUSION SHALL
NOT EXCEED 0.25 (0.010) PER SIDE.
5. DIMENSION K DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.08 (0.003) TOTAL
IN EXCESS OF THE K DIMENSION AT
MAXIMUM MATERIAL CONDITION.
6. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
16
9
2X L/2
J1
B
−U−
SECTION N−N
L
J
PIN 1
IDENT.
8
1
7. DIMENSION A AND B ARE TO BE
DETERMINED AT DATUM PLANE −W−.
N
0.25 (0.010)
MILLIMETERS
DIM MIN MAX
INCHES
MIN MAX
S
0.15 (0.006) T
U
A
−V−
M
A
B
C
D
F
4.90
4.30
−−−
0.05
0.50
5.10 0.193 0.200
4.50 0.169 0.177
1.20
−−− 0.047
N
0.15 0.002 0.006
0.75 0.020 0.030
F
G
H
J
J1
K
K1
L
0.65 BSC
0.026 BSC
0.18
0.09
0.09
0.19
0.19
0.28 0.007 0.011
DETAIL E
0.20 0.004 0.008
0.16 0.004 0.006
0.30 0.007 0.012
0.25 0.007 0.010
6.40 BSC
0.252 BSC
−W−
C
M
0
8
0
8
_
_
_
_
0.10 (0.004)
H
DETAIL E
SEATING
PLANE
−T−
D
G
ON Semiconductor and
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any
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damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over
time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under
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SA572/D
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