SCV431ASN1T1G [ONSEMI]
Low Voltage Precision Adjustable Shunt Regulator;
| 型号： | SCV431ASN1T1G |
| 厂家： | 
ONSEMI |
| 描述： | Low Voltage Precision Adjustable Shunt Regulator |
| 文件： | 总19页 (文件大小：394K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Low Voltage Precision
Adjustable Shunt Regulator
TLV431, NCV431, SCV431
The TLV431A, B and C series are precision low voltage shunt
regulators that are programmable over a wide voltage range of 1.24 V to
16 V. The TLV431A series features a guaranteed reference accuracy of
1.0% at 25°C and 2.0% over the entire industrial temperature range of
−40°C to 85°C. The TLV431B series features higher reference accuracy
of 0.5% and 1.0% respectively. For the TLV431C series, the accuracy
is even higher. It is 0.2% and 1.0% respectively. These devices exhibit
a sharp low current turn−on characteristic with a low dynamic impedance
of 0.20 W over an operating current range of 100 mA to 20 mA. This
combination of features makes this series an excellent replacement for
zener diodes in numerous applications circuits that require a precise
reference voltage. When combined with an optocoupler, the
TLV431A/B/C can be used as an error amplifier for controlling the
feedback loop in isolated low output voltage (3.0 V to 3.3 V) switching
power supplies. These devices are available in economical TO−92−3 and
micro size TSOP−5 and SOT−23−3 packages.
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Pin 1. Reference
2. Anode
1
3. Cathode
1
2
2
3
3
STRAIGHT LEAD
BULK PACK
BENT LEAD
TAPE & REEL
AMMO PACK
TO−92
TO−92
LP SUFFIX
CASE 29−11
LPRA, LPRE, LPRM,
LPRP SUFFIX
CASE 29−11
Features
• Programmable Output Voltage Range of 1.24 V to 16 V
• Voltage Reference Tolerance 1.0% for A Series, 0.5% for B Series
4
and 0.2% for C Series
Pin 1. NC
2. NC
TSOP−5
SN SUFFIX
CASE 483
5
• Sharp Low Current Turn−On Characteristic
• Low Dynamic Output Impedance of 0.20 W from 100 mA to 20 mA
• Wide Operating Current Range of 50 mA to 20 mA
• Micro Miniature TSOP−5, SOT−23−3 and TO−92−3 Packages
• NCV and SCV Prefix for Automotive and Other Applications
Requiring Unique Site and Control Change Requirements;
AEC−Q100 Qualified and PPAP Capable
3
3. Cathode
4. Reference
5. Anode
2
3
1
SOT−23
SN1 SUFFIX
CASE 318
Pin 1. Reference
2. Cathode
1
3. Anode
2
• These are Pb−Free and Halide−Free Devices
Applications
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 14 of this data sheet.
• Low Output Voltage (3.0 V to 3.3 V) Switching Power Supply
Error Amplifier
• Adjustable Voltage or Current Linear and Switching Power Supplies
• Voltage Monitoring
DEVICE MARKING INFORMATION
AND PIN CONNECTIONS
See general marking information in the device marking
section on page 13 of this data sheet.
• Current Source and Sink Circuits
• Analog and Digital Circuits Requiring Precision References
• Low Voltage Zener Diode Replacements
Cathode (K)
Reference (R)
+
-
1.24 V
ref
Anode (A)
Figure 1. Representative Block Diagram
© Semiconductor Components Industries, LLC, 2000
1
Publication Order Number:
January, 2020 − Rev. 26
TLV431A/D
TLV431, NCV431, SCV431
Cathode (K)
Reference (R)
Cathode (K)
Reference (R)
Anode (A)
Device Symbol
Anode (A)
The device contains 13 active transistors.
Figure 2. Representative Device Symbol and Schematic Diagram
MAXIMUM RATINGS (Full operating ambient temperature range applies, unless otherwise noted)
Rating Symbol
Value
18
Unit
V
Cathode to Anode Voltage
V
KA
Cathode Current Range, Continuous
I
−20 to 25
*0.05 to 10
mA
mA
°C/W
K
Reference Input Current Range, Continuous
I
ref
Thermal Characteristics
LP Suffix Package, TO−92−3 Package
Thermal Resistance, Junction−to−Ambient
Thermal Resistance, Junction−to−Case
SN Suffix Package, TSOP−5 Package
Thermal Resistance, Junction−to−Ambient
SN1 Suffix Package, SOT−23−3 Package
Thermal Resistance, Junction−to−Ambient
R
R
178
83
q
JA
q
JC
226
R
R
q
JA
491
150
q
JA
J
Operating Junction Temperature
T
°C
°C
Operating Ambient Temperature Range
TLV431
NCV431, SCV431
T
A
*40 to 85
*40 to 125
Storage Temperature Range
T
stg
*65 to 150
°C
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
NOTE: This device series contains ESD protection and exceeds the following tests:
Human Body Model 2000 V per JEDEC JESD22−A114F, Machine Model Method 200 V per JEDEC JESD22−A115C,
Charged Device Method 1000 V per JEDEC JESD22−C101E. This device contains latch−up protection and exceeds 100 mA per
JEDEC standard JESD78.
T
* T
J(max)
R
A
P
+
D
qJA
RECOMMENDED OPERATING CONDITIONS
Condition
Symbol
Min
Max
16
Unit
V
Cathode to Anode Voltage
Cathode Current
V
KA
V
ref
I
K
0.1
20
mA
Functional operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses beyond
the Recommended Operating Ranges limits may affect device reliability.
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2
TLV431, NCV431, SCV431
ELECTRICAL CHARACTERISTICS (T = 25°C unless otherwise noted)
A
TLV431A
Typ
TLV431B
Typ Max
Min
Max
Min
Characteristic
Reference Voltage (Figure 3)
Symbol
Unit
V
ref
V
1.228 1.240 1.252 1.234 1.240 1.246
(V = V , I = 10 mA, T = 25°C)
KA
ref
K
A
1.215
−
1.265 1.228
−
1.252
(T = T
to T , Note 1)
A
low
high
Reference Input Voltage Deviation Over Temperature (Figure 3)
(V = V , I = 10 mA, T = T to T , Notes 1, 2, 3)
DV
mV
ref
−
7.2
20
−
7.2
20
KA
ref
K
A
low
high
Ration of Reference Input Voltage Change to Cathode Voltage
Change (Figure 4)
DVref
DVKA
mV
V
−
−
−0.6
−1.5
−
−
−0.6
−1.5
(V = V to 16 V, I = 10 mA)
KA
ref
K
Reference Terminal Current (Figure 4)
(I = 10 mA, R1 = 10 kW, R2 = open)
K
I
ref
mA
mA
0.15
0.3
0.15
0.3
Reference Input Current Deviation Over Temperature (Figure 4)
DI
ref
−
−
0.04
30
0.08
80
−
−
0.04
30
0.08
80
(I = 10 mA, R1 = 10 kW, R2 = open, Notes 1, 2, 3)
K
Minimum Cathode Current for Regulation (Figure 3)
I
)
mA
mA
K(min
Off−State Cathode Current (Figure 5)
I
K(off)
−
−
0.01
0.012 0.05
0.04
−
−
0.01
0.012 0.05
0.04
(V = 6.0 V, V = 0)
KA
ref
(V = 16 V, V = 0)
KA
ref
Dynamic Impedance (Figure 3)
(V = V , I =0.1 mA to 20 mA, f ≤ 1.0 kHz, Note 4)
|Z
|
W
KA
−
0.25
0.4
−
0.25
0.4
KA
ref
K
1. Ambient temperature range: T = *40°C, T
= 85°C.
low
high
2. Guaranteed but not tested.
3. The deviation parameters DV and DI are defined as the difference between the maximum value and minimum value obtained over the
ref
ref
full operating ambient temperature range that applied.
V
ref
Max
DV = V Max − V Min
ref
ref
ref
DT = T − T
1
V
ref
Min
A
2
T
1
Ambient Temperature
T
2
The average temperature coefficient of the reference input voltage, aV is defined as:
ref
(DV
ref
)
106
ǒ
Ǔ
V
(T + 25°C)
A
ref
ppm
ref ǒ Ǔ+
°C
αV
DT
A
aV can be positive or negative depending on whether V Min or V Max occurs at the lower ambient temperature, refer to Figure 8.
ref
ref
ref
Example: DV = 7.2 mV and the slope is positive,
ref
Example: V @ 25°C = 1.241 V
ref
Example: DT = 125°C
A
106
0.0072
1.241
ppm
°C
ref ǒ Ǔ+
αV
+ 46 ppmń°C
125
4. The dynamic impedance Z is defined as:
KA
DV
KA
DIK
⏐Z ⏐ +
KA
When the device is operating with two external resistors, R1 and R2, (refer to Figure 4) the total dynamic impedance of the circuit is given by:
R1
⏐ ǒ1 )
Ǔ
⏐Z ′⏐ + ⏐Z
KA
KA
R2
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3
TLV431, NCV431, SCV431
ELECTRICAL CHARACTERISTICS (T = 25°C unless otherwise noted)
A
TLV431C
Typ
Min
Max
Characteristic
Symbol
Unit
Reference Voltage (Figure 3)
V
ref
V
(V = V , I = 10 mA, T = 25°C)
1.237 1.240 1.243
KA
ref
K
A
(T = T
to T
, Note 5)
1.228
−
1.252
A
low
high
Reference Input Voltage Deviation Over Temperature (Figure 3)
(V = V , I = 10 mA, T = T to T , Notes 5, 6, 7)
DV
mV
ref
−
7.2
20
KA
ref
K
A
low
high
Ration of Reference Input Voltage Change to Cathode Voltage Change (Figure 4)
(V = V to 16 V, I = 10 mA)
DVref
DVKA
mV
V
−
−
−0.6
−1.5
KA
ref
K
Reference Terminal Current (Figure 4)
(I = 10 mA, R1 = 10 kW, R2 = open)
K
I
ref
mA
0.15
0.3
Reference Input Current Deviation Over Temperature (Figure 4)
(I = 10 mA, R1 = 10 kW, R2 = open, Notes 5, 6, 7)
K
DI
ref
mA
−
−
0.04
30
0.08
80
Minimum Cathode Current for Regulation (Figure 3)
I
)
mA
mA
K(min
Off−State Cathode Current (Figure 5)
I
K(off)
−
−
0.01
0.012 0.05
0.04
(V = 6.0 V, V = 0)
KA
ref
(V = 16 V, V = 0)
KA
ref
Dynamic Impedance (Figure 3)
(V = V , I = 0.1 mA to 20 mA, f ≤ 1.0 kHz, Note 8)
|Z
|
W
KA
−
0.25
0.4
KA
ref
K
5. Ambient temperature range: T = *40°C, T
= 85°C.
low
high
6. Guaranteed but not tested.
7. The deviation parameters DV and DI are defined as the difference between the maximum value and minimum value obtained over the
ref
ref
full operating ambient temperature range that applied.
V
ref
Max
DV = V Max − V Min
ref
ref
ref
DT = T − T
1
V
ref
Min
A
2
T
1
Ambient Temperature
T
2
The average temperature coefficient of the reference input voltage, aV is defined as:
ref
(DV
ref
)
106
ǒ
Ǔ
V
(T + 25°C)
A
ref
ppm
ref ǒ Ǔ+
°C
αV
DT
A
aV can be positive or negative depending on whether V Min or V Max occurs at the lower ambient temperature, refer to Figure 8.
ref
ref
ref
Example: DV = 7.2 mV and the slope is positive,
ref
Example: V @ 25°C = 1.241 V
ref
Example: DT = 125°C
A
106
0.0072
1.241
ppm
°C
ref ǒ Ǔ+
αV
+ 46 ppmń°C
125
8. The dynamic impedance Z is defined as:
KA
DV
KA
DIK
⏐Z ⏐ +
KA
When the device is operating with two external resistors, R1 and R2, (refer to Figure 4) the total dynamic impedance of the circuit is given by:
R1
⏐ ǒ1 )
Ǔ
⏐Z ′⏐ + ⏐Z
KA
KA
R2
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4
TLV431, NCV431, SCV431
ELECTRICAL CHARACTERISTICS (T = 25°C unless otherwise noted. NCV prefix indicates TSOP package device. SCV prefix
A
indicates SOT−23 package device.)
NCV431A, SCV431A
Min
Typ
Max
Characteristic
Symbol
Unit
Reference Voltage (Figure 3)
(V = V , I = 10 mA, T = 25°C)
V
ref
V
1.228 1.240 1.252
KA
ref
K
A
1.215
1.211
−
−
1.265
1.265
(T = *40°C to 85°C)
A
(T = *40°C to 125°C)
A
Reference Input Voltage Deviation Over Temperature (Figure 3)
(V = V , I = 10 mA, T = *40°C to 85°C, Notes 9, 10)
DV
mV
ref
−
−
7.2
7.2
20
24
KA
ref
K
A
(V = V , I = 10 mA, T = *40°C to 125°C, Notes 9, 10)
KA
ref
K
A
Ration of Reference Input Voltage Change to Cathode Voltage Change (Figure 4)
(V = V to 16 V, I = 10 mA)
DVref
DVKA
mV
V
−
−
−0.6
−1.5
KA
ref
K
Reference Terminal Current (Figure 4)
(I = 10 mA, R1 = 10 kW, R2 = open)
K
I
ref
mA
0.15
0.3
Reference Input Current Deviation Over Temperature (Figure 4)
DI
ref
mA
−
−
0.04
−
0.08
0.10
(I = 10 mA, R1 = 10 kW, R2 = open, T = *40°C to 85°C, Notes 9, 10)
K
A
(I = 10 mA, R1 = 10 kW, R2 = open, T = *40°C to 125°C, Notes 9, 10)
K
A
Minimum Cathode Current for Regulation (Figure 3)
I
)
−
30
80
mA
mA
K(min
Off−State Cathode Current (Figure 5)
I
K(off)
−
−
0.01
0.012 0.05
0.04
(V = 6.0 V, V = 0)
KA
ref
(V = 16 V, V = 0)
KA
ref
Dynamic Impedance (Figure 3)
(V = V , I =0.1 mA to 20 mA, f ≤ 1.0 kHz, Note 11)
|Z
|
W
KA
−
0.25
0.4
KA
ref
K
9. Guaranteed but not tested.
10.The deviation parameters DV and DI are defined as the difference between the maximum value and minimum value obtained over the
ref
ref
full operating ambient temperature range that applied.
V
ref
Max
DV = V Max − V Min
ref
ref
ref
DT = T − T
1
V
ref
Min
A
2
T
1
Ambient Temperature
T
2
The average temperature coefficient of the reference input voltage, aV is defined as:
ref
(DV
ref
)
106
ǒ
Ǔ
V
(T + 25°C)
A
ref
ppm
ref ǒ Ǔ+
°C
αV
DT
A
aV can be positive or negative depending on whether V Min or V Max occurs at the lower ambient temperature, refer to Figure 8.
ref
ref
ref
Example: DV = 7.2 mV and the slope is positive,
ref
Example: V @ 25°C = 1.241 V
ref
Example: DT = 125°C
A
106
0.0072
1.241
ppm
°C
ref ǒ Ǔ+
αV
+ 46 ppmń°C
125
11. The dynamic impedance Z is defined as:
KA
DV
KA
DIK
⏐Z ⏐ +
KA
When the device is operating with two external resistors, R1 and R2, (refer to Figure 4) the total dynamic impedance of the circuit is given by:
R1
⏐ ǒ1 )
Ǔ
⏐Z ′⏐ + ⏐Z
KA
KA
R2
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5
TLV431, NCV431, SCV431
ELECTRICAL CHARACTERISTICS (T = 25°C unless otherwise noted. NCV prefix indicates TSOP package device. SCV prefix
A
indicates SOT−23 package device.)
NCV431B, SCV431B
Min
Typ
Max
Characteristic
Symbol
Unit
Reference Voltage (Figure 3)
(V = V , I = 10 mA, T = 25°C)
V
ref
V
1.234 1.240 1.246
KA
ref
K
A
1.228
1.224
−
−
1.252
1.252
(T = *40°C to 85°C)
A
(T = *40°C to 125°C)
A
Reference Input Voltage Deviation Over Temperature (Figure 3)
(V = V , I = 10 mA, T = *40°C to 85°C, Notes 9, 10)
DV
mV
ref
−
−
7.2
7.2
20
24
KA
ref
K
A
(V = V , I = 10 mA, T = *40°C to 125°C, Notes 9, 10)
KA
ref
K
A
Ration of Reference Input Voltage Change to Cathode Voltage Change (Figure 4)
(V = V to 16 V, I = 10 mA)
DVref
DVKA
mV
V
−
−
−0.6
−1.5
KA
ref
K
Reference Terminal Current (Figure 4)
(I = 10 mA, R1 = 10 kW, R2 = open)
K
I
ref
mA
0.15
0.3
Reference Input Current Deviation Over Temperature (Figure 4)
DI
ref
mA
−
−
0.04
−
0.08
0.10
(I = 10 mA, R1 = 10 kW, R2 = open, T = *40°C to 85°C, Notes 12, 13)
K
A
(I = 10 mA, R1 = 10 kW, R2 = open, T = *40°C to 125°C, Notes 12, 13)
K
A
Minimum Cathode Current for Regulation (Figure 3)
I
)
−
30
80
mA
mA
K(min
Off−State Cathode Current (Figure 5)
I
K(off)
−
−
0.01
0.012 0.05
0.04
(V = 6.0 V, V = 0)
KA
ref
(V = 16 V, V = 0)
KA
ref
Dynamic Impedance (Figure 3)
(V = V , I =0.1 mA to 20 mA, f ≤ 1.0 kHz, Note 14)
|Z
|
W
KA
−
0.25
0.4
KA
ref
K
12.Guaranteed but not tested.
13.The deviation parameters DV and DI are defined as the difference between the maximum value and minimum value obtained over the
ref
ref
full operating ambient temperature range that applied.
V
ref
Max
DV = V Max − V Min
ref
ref
ref
DT = T − T
1
V
ref
Min
A
2
T
1
Ambient Temperature
T
2
The average temperature coefficient of the reference input voltage, aV is defined as:
ref
(DV
ref
)
106
ǒ
Ǔ
V
(T + 25°C)
A
ref
ppm
ref ǒ Ǔ+
°C
αV
DT
A
aV can be positive or negative depending on whether V Min or V Max occurs at the lower ambient temperature, refer to Figure 8.
ref
ref
ref
Example: DV = 7.2 mV and the slope is positive,
ref
Example: V @ 25°C = 1.241 V
ref
Example: DT = 125°C
A
106
0.0072
1.241
ppm
°C
ref ǒ Ǔ+
αV
+ 46 ppmń°C
125
14.The dynamic impedance Z is defined as:
KA
DV
KA
DIK
⏐Z ⏐ +
KA
When the device is operating with two external resistors, R1 and R2, (refer to Figure 4) the total dynamic impedance of the circuit is given by:
R1
⏐ ǒ1 )
Ǔ
⏐Z ′⏐ + ⏐Z
KA
KA
R2
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TLV431, NCV431, SCV431
Input
V
KA
Input
V
KA
Input
V
KA
I
K
I
K
I
K(off)
I
R1
R2
ref
V
ref
V
ref
R1
R2
ꢀǒꢀ1 ) ꢀǓ) I
V
+ V
ꢀSꢀR1
KA
ref
ref
Figure 3. Test Circuit
for VKA = Vref
Figure 4. Test Circuit
Figure 5. Test Circuit
for IK(off)
for VKA u Vref
110
90
70
50
30
10
30
Input
V
KA
I
K
Input
V
KA
20
10
I
K
I
K(min)
V
= V
KA
ref
T
A
= 25°C
V
= V
ref
KA
T
A
= 25°C
0
−10
−30
−10
−1.0
−0.5
0
0.5
1.0
1.5
2.0
0
0.2
0.4
0.6
0.8
1.0
1.2
1.4
V
KA
, CATHODE VOLTAGE (V)
V
KA
, CATHODE VOLTAGE (V)
Figure 6. Cathode Current vs. Cathode Voltage
Figure 7. Cathode Current vs. Cathode Voltage
0.15
0.14
1.25
1.24
Vref
(max)
Input
10 k
V
KA
I
K
I
ref
Vref
(typ)
I
K
= 10 mA
1.23
1.22
0.13
0.12
Input
V
K
KA
Vref
(min)
I
V
= V
ref
KA
I
K
= 10 mA
TLV431A Typ.
60
−40
−15
10
35
85
−40
−15
10
35
60
85
T , AMBIENT TEMPERATURE (°C)
A
T , AMBIENT TEMPERATURE (°C)
A
Figure 8. Reference Input Voltage versus
Ambient Temperature
Figure 9. Reference Input Current versus
Ambient Temperature
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TLV431, NCV431, SCV431
4.0
0
−2.0
−4.0
−6.0
Input
V
KA
I
= 10 mA
K
I
off
V
KA
V
ref
= 16 V
= 0 V
T = 25°C
A
3.0
2.0
Input
V
KA
I
K
R1
R2
1.0
0
V
ref
T = 25°C
A
−8.0
−10
0
4.0
8.0
12
16
0
4.0
8.0
12
16
20
V
KA
, CATHODE VOLTAGE (V)
V
KA
, CATHODE VOLTAGE (V)
Figure 10. Reference Input Voltage Change
versus Cathode Voltage
Figure 11. Off−State Cathode Current
versus Cathode Voltage
0.4
0.3
0.2
10
Output
I
K
Input
V
KA
50
I
off
V
= 16 V
= 0 V
KA
−
V
ref
+
1.0
0.1
0.1
0
I
K
= 0.1 mA to 20 mA
T = 25°C
A
−40
−15
10
35
60
85
1.0 k
10 k
100 k
f, FREQUENCY (Hz)
1.0 M
10 M
T , AMBIENT TEMPERATURE (°C)
A
Figure 12. Off−State Cathode Current versus
Figure 13. Dynamic Impedance versus
Frequency
Ambient Temperature
0.24
0.23
0.22
0.21
60
50
40
30
20
Output
I
= 0.1 mA to 20 mA
K
f = 1.0 kHz
Output
15 k
I
K
I
K
9 m F
230
50
−
−
8.25 k
+
+
I
= 10 mA
K
T = 25°C
A
0.20
0.19
10
0
−40
−15
10
35
60
85
100
1.0 k
10 k
f, FREQUENCY (Hz)
100 k
1.0 M
T , AMBIENT TEMPERATURE (°C)
A
Figure 14. Dynamic Impedance versus
Ambient Temperature
Figure 15. Open−Loop Voltage Gain
versus Frequency
www.onsemi.com
8
TLV431, NCV431, SCV431
350
Output
1.8 kW
Input
Input
Output
I
K
I
ref
1.5
1.0
0.5
0
325
300
V
I
T
A
= V
ref
= 10 mA
= 25°C
KA
50
Output
Input
K
T
A
= 25°C
2.0
0
275
250
10
100
1.0 k
f, FREQUENCY (Hz)
10 k
100 k
0
1.0 2.0 3.0 4.0 5.0 6.0 7.0 8.0 9.0 10.0
t, TIME (ms)
Figure 16. Spectral Noise Density
Figure 17. Pulse Response
1.0 k
25
20
15
T = 25°C
A
I
K
R1
R2
A
Stable
V+
C
L
C
B
Stable
10
5.0
0
Stable
Unstable
Regions
V
(V)
R1
(kW)
R2
(kW)
KA
D
10
100
pF
1.0
nF
0.01
mF
0.1
mF
1.0
mF
10
mF
100
mF
A, C
B, D
V
0
∞
ref
pF
5.0
30.4
10
C , LOAD CAPACITANCE
L
Figure 18. Stability Boundary Conditions
Figure 19. Test Circuit for Figure 18
Stability
Figures 18 and 19 show the stability boundaries and
circuit configurations for the worst case conditions with the
load capacitance mounted as close as possible to the device.
The required load capacitance for stable operation can vary
depending on the operating temperature and capacitor
equivalent series resistance (ESR). Ceramic or tantalum
surface mount capacitors are recommended for both
temperature and ESR. The application circuit stability
should be verified over the anticipated operating current and
temperature ranges.
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9
TLV431, NCV431, SCV431
TYPICAL APPLICATIONS
V
in
V
out
V
in
V
out
R1
R2
R1
R2
R1
R1
+ ǒ1 ) ǓV
V
+ ǒ1 ) ǓV
V
out
ref
R2
out
ref
R2
Figure 20. Shunt Regulator
Figure 21. High Current Shunt Regulator
V
in
V
out
MC7805
V
in
Out
Common
In
V
out
R1
R2
R1
R2
R1
R1
+ ǒ1 ) ǓV
+ ǒ1 ) ǓV
out(min)
V
V
out
out
ref
ref
R2
R2
V
+ V ) 5.0 V
V
+ V ) V
ref
out
in(min)
V
be
+ V
out(min)
ref
Figure 22. Output Control for a Three Terminal
Fixed Regulator
Figure 23. Series Pass Regulator
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10
TLV431, NCV431, SCV431
I
V
in
sink
V
ref
I
+
sink
R
S
I
out
R
CL
V
in
V
out
R
S
V
R
ref
I
+
out
CL
Figure 24. Constant Current Source
Figure 25. Constant Current Sink
V
in
V
in
V
out
V
out
R1
R1
R2
R2
R1
R1
+ ǒ1 ) ǓV
+ ǒ1 ) ǓV
V
V
out(trip)
ref
out(trip)
ref
R2
R2
Figure 26. TRIAC Crowbar
Figure 27. SCR Crowbar
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11
TLV431, NCV431, SCV431
25 V
V
in
2.0 mA
1N5305
R1
R2
R3
LED
5 k
1%
50 k
1%
1.0 M
1%
500 k
1%
10 k
Calibrate
10 kW
V
100 kW
V
R4
1.0 kW
1.0 MW
V
V
25 V
-
+
L.E.D. indicator is ‘ON’ when V is
between the upper and lower limits,
in
V
out
Range
R1
Lower limit + ǒ1 ) ǓVref
−5.0 V
R
x
R2
R3
W
V
Upper limit + ǒ1 ) ǓVref
R
+ V ꢀDꢀꢀ ꢀ Range
x
R4
out
Figure 28. Voltage Monitor
Figure 29. Linear Ohmmeter
38 V
T1 = 330 W to 8.0 W
330
T1
+
470 mF
8.0 W
360 k
1.0 mF
Volume
47 k
*
0.05 mF
25 k
*Thermalloy
*THM 6024
*Heatsink on
*LP Package.
56 k
Tone
10 k
Figure 30. Simple 400 mW Phono Amplifier
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12
TLV431, NCV431, SCV431
AC Input
DC Output
3.3 V
Gate Drive
100
V
CC
Controller
R1
3.0 k
V
FB
C1
0.1 mF
Current
Sense
R2
1.8 k
GND
Figure 31. Isolated Output Line Powered Switching Power Supply
The above circuit shows the TLV431A/B/C as a compensated amplifier controlling the feedback loop of an isolated output line
powered switching regulator. The output voltage is programmed to 3.3 V by the resistors values selected for R1 and R2. The
minimum output voltage that can be programmed with this circuit is 2.64 V, and is limited by the sum of the reference voltage
(1.24 V) and the forward drop of the optocoupler light emitting diode (1.4 V). Capacitor C1 provides loop compensation.
PIN CONNECTIONS AND DEVICE MARKING
TO−92
TSOP−5
SOT−23−3
TLV43
1XXX
ALYWG
G
1
5
4
Anode
NC
NC
1
Reference
Cathode
2
3
Anode
3
Reference
Cathode
2
1. Reference
2. Anode
3. Cathode
(Top View)
(Top View)
XXX
A
Y
= Specific Device Code
= Assembly Location
= Year
XXX
M
= Specific Device Code
= Date Code
= Pb−Free Package
1
2 3
G
L
= Wafer Lot
(Note: Microdot may be in either location)
W
G
= Work Week
= Pb−Free Package
(Note: Microdot may be in either location)
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13
TLV431, NCV431, SCV431
ORDERING INFORMATION
Device
†
Device Code
Package
Shipping
TLV431ALPG
ALP
TO−92−3
(Pb−Free)
6000 / Box
TLV431ALPRAG
TLV431ALPREG
TLV431ALPRMG
TLV431ALPRPG
TLV431ASNT1G
TLV431ASN1T1G
TLV431BLPG
ALP
ALP
ALP
ALP
RAA
RAF
BLP
BLP
BLP
BLP
BLP
RAH
RAG
AAN
RAE
RAC
ACH
AD6
TO−92−3
(Pb−Free)
2000 / Tape & Reel
2000 / Tape & Reel
2000 / Ammo Pack
2000 / Ammo Pack
3000 / Tape & Reel
3000 / Tape & Reel
6000 / Box
TO−92−3
(Pb−Free)
TO−92−3
(Pb−Free)
TO−92−3
(Pb−Free)
TSOP−5
(Pb−Free, Halide−Free)
SOT−23−3
(Pb−Free, Halide−Free)
TO−92−3
(Pb−Free)
TLV431BLPRAG
TLV431BLPREG
TLV431BLPRMG
TLV431BLPRPG
TLV431BSNT1G
TLV431BSN1T1G
TLV431CSN1T1G
SCV431ASN1T1G*
SCV431BSN1T1G*
NCV431ASNT1G*
NCV431BSNT1G*
TO−92−3
(Pb−Free)
2000 / Tape & Reel
2000 / Tape & Reel
2000 / Ammo Pack
2000 / Ammo Pack
3000 / Tape & Reel
3000 / Tape & Reel
3000 / Tape & Reel
3000 / Tape & Reel
3000 / Tape & Reel
3000 / Tape & Reel
3000 / Tape & Reel
TO−92−3
(Pb−Free)
TO−92−3
(Pb−Free)
TO−92−3
(Pb−Free)
TSOP−5
(Pb−Free, Halide−Free)
SOT−23−3
(Pb−Free, Halide−Free)
SOT−23−3
(Pb−Free, Halide−Free)
SOT−23−3
(Pb−Free, Halide−Free)
SOT−23−3
(Pb−Free, Halide−Free)
TSOP−5
(Pb−Free, Halide−Free)
TSOP−5
(Pb−Free, Halide−Free)
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
*SCV, NCV Prefix for Automotive and Other Applications Requiring Unique Site and Control Change Requirements; AEC−Q100 Qualified and
PPAP Capable.
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14
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
TO−92 (TO−226) 1 WATT
CASE 29−10
SCALE 1:1
ISSUE A
DATE 08 MAY 2012
1
1
2
2
3
STRAIGHT LEAD
3
BENT LEAD
A
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1994.
STRAIGHT LEAD
2. CONTROLLING DIMENSION: INCHES.
3. CONTOUR OF PACKAGE BEYOND DIMENSION R IS
UNCONTROLLED.
B
R
4. DIMENSION F APPLIES BETWEEN DIMENSIONS P
AND L. DIMENSIONS D AND J APPLY BETWEEN DI
MENSIONS L AND K MINIMUM. THE LEAD
DIMENSIONS ARE UNCONTROLLED IN DIMENSION
P AND BEYOND DIMENSION K MINIMUM.
P
L
F
K
INCHES
DIM MIN MAX
MILLIMETERS
MIN
4.44
7.37
3.18
0.46
0.41
1.15
2.42
0.46
12.70
6.35
2.04
---
MAX
5.21
7.87
4.19
0.53
0.48
1.39
2.66
0.61
---
A
B
C
D
F
0.175
0.290
0.125
0.018
0.016
0.045
0.095
0.018
0.500
0.250
0.080
---
0.205
0.310
0.165
0.021
0.019
0.055
0.105
0.024
---
D
X X
G
J
H
V
G
H
J
C
K
L
SECTION X−X
---
---
1
N
N
P
R
V
0.105
0.100
---
2.66
2.54
---
N
0.135
0.135
3.43
3.43
---
---
A
NOTES:
1. DIMENSIONING AND TOLERANCING PER ASME
Y14.5M, 1994.
BENT LEAD
R
2. CONTROLLING DIMENSION: INCHES.
3. CONTOUR OF PACKAGE BEYOND DIMENSION R IS
UNCONTROLLED.
B
4. DIMENSION F APPLIES BETWEEN DIMENSIONS P
AND L. DIMENSIONS D AND J APPLY BETWEEN
DIMENSIONS L AND K MINIMUM. THE LEAD
DIMENSIONS ARE UNCONTROLLED IN DIMENSION
P AND BEYOND DIMENSION K MINIMUM.
P
T
SEATING
PLANE
K
INCHES
DIM MIN MAX
MILLIMETERS
MIN
4.44
7.37
3.18
0.46
2.40
0.46
12.70
2.04
---
MAX
5.21
7.87
4.19
0.53
2.80
0.61
---
A
B
C
D
G
J
0.175
0.290
0.125
0.018
0.094
0.018
0.500
0.080
---
0.205
0.310
0.165
0.021
0.102
0.024
---
D
X X
G
J
K
N
P
R
V
V
C
0.105
0.100
---
2.66
2.54
---
SECTION X−X
0.135
0.135
3.43
3.43
1
N
---
---
STYLES ON PAGE 2
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
DOCUMENT NUMBER:
DESCRIPTION:
98AON52857E
TO−92 (TO−226) 1 WATT
PAGE 1 OF 2
ON Semiconductor and
are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.
ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding
the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically
disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the
rights of others.
© Semiconductor Components Industries, LLC, 2019
www.onsemi.com
TO−92 (TO−226) 1 WATT
CASE 29−10
ISSUE A
DATE 08 MAY 2012
STYLE 2:
PIN 1. BASE
2. EMITTER
3. COLLECTOR
STYLE 3:
STYLE 4:
PIN 1. CATHODE
STYLE 5:
STYLE 1:
PIN 1. EMITTER
2. BASE
PIN 1. ANODE
2. ANODE
3. CATHODE
PIN 1. DRAIN
2. SOURCE
3. GATE
2. CATHODE
3. ANODE
3. COLLECTOR
STYLE 8:
PIN 1. DRAIN
2. GATE
STYLE 9:
STYLE 10:
STYLE 7:
STYLE 6:
PIN 1. GATE
PIN 1. BASE 1
2. EMITTER
3. BASE 2
PIN 1. CATHODE
2. GATE
3. ANODE
PIN 1. SOURCE
2. DRAIN
3. GATE
2. SOURCE & SUBSTRATE
3. DRAIN
3. SOURCE & SUBSTRATE
STYLE 13:
STYLE 14:
STYLE 15:
STYLE 12:
STYLE 11:
PIN 1. ANODE
PIN 1. ANODE 1
2. GATE
3. CATHODE 2
PIN 1. EMITTER
2. COLLECTOR
3. BASE
PIN 1. ANODE 1
2. CATHODE
3. ANODE 2
PIN 1. MAIN TERMINAL 1
2. GATE
3. MAIN TERMINAL 2
2. CATHODE & ANODE
3. CATHODE
STYLE 18:
STYLE 19:
STYLE 20:
STYLE 17:
STYLE 16:
PIN 1. ANODE
2. GATE
PIN 1. ANODE
2. CATHODE
3. NOT CONNECTED
PIN 1. GATE
2. ANODE
3. CATHODE
PIN 1. NOT CONNECTED
2. CATHODE
3. ANODE
PIN 1. COLLECTOR
2. BASE
3. EMITTER
3. CATHODE
STYLE 23:
PIN 1. GATE
2. SOURCE
3. DRAIN
STYLE 24:
STYLE 25:
PIN 1. MT 1
2. GATE
3. MT 2
STYLE 22:
STYLE 21:
PIN 1. EMITTER
2. COLLECTOR/ANODE
3. CATHODE
PIN 1. SOURCE
2. GATE
3. DRAIN
PIN 1. COLLECTOR
2. EMITTER
3. BASE
STYLE 28:
STYLE 29:
STYLE 30:
STYLE 27:
PIN 1. MT
2. SUBSTRATE
3. MT
STYLE 26:
PIN 1.
PIN 1. CATHODE
2. ANODE
3. GATE
PIN 1. NOT CONNECTED
2. ANODE
3. CATHODE
PIN 1. DRAIN
2. GATE
3. SOURCE
V
CC
2. GROUND 2
3. OUTPUT
STYLE 33:
STYLE 34:
STYLE 35:
STYLE 32:
PIN 1. BASE
2. COLLECTOR
STYLE 31:
PIN 1. GATE
2. DRAIN
PIN 1. RETURN
2. INPUT
3. OUTPUT
PIN 1. INPUT
2. GROUND
3. LOGIC
PIN 1. GATE
2. COLLECTOR
3. EMITTER
3. EMITTER
3. SOURCE
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
DOCUMENT NUMBER:
DESCRIPTION:
98AON52857E
TO−92 (TO−226) 1 WATT
PAGE 2 OF 2
ON Semiconductor and
are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.
ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding
the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically
disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the
rights of others.
© Semiconductor Components Industries, LLC, 2019
www.onsemi.com
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
SOT−23 (TO−236)
CASE 318−08
ISSUE AS
DATE 30 JAN 2018
SCALE 4:1
NOTES:
D
1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS.
3. MAXIMUM LEAD THICKNESS INCLUDES LEAD FINISH.
MINIMUM LEAD THICKNESS IS THE MINIMUM THICKNESS OF
THE BASE MATERIAL.
0.25
3
4. DIMENSIONS D AND E DO NOT INCLUDE MOLD FLASH,
PROTRUSIONS, OR GATE BURRS.
T
H
E
E
1
2
MILLIMETERS
INCHES
DIM
A
A1
b
c
D
E
e
L
MIN
0.89
0.01
0.37
0.08
2.80
1.20
1.78
0.30
0.35
2.10
0°
NOM
1.00
0.06
0.44
0.14
2.90
1.30
1.90
0.43
0.54
2.40
−−−
MAX
MIN
0.035
0.000
0.015
0.003
0.110
0.047
0.070
0.012
0.014
0.083
0°
NOM
0.039
0.002
0.017
0.006
0.114
0.051
0.075
0.017
0.021
0.094
−−−
MAX
0.044
0.004
0.020
0.008
0.120
0.055
0.080
0.022
0.027
0.104
10°
L
1.11
0.10
0.50
0.20
3.04
1.40
2.04
0.55
0.69
2.64
10°
3X
b
L1
VIEW C
e
TOP VIEW
L1
A
H
E
T
c
A1
SEE VIEW C
SIDE VIEW
GENERIC
MARKING DIAGRAM*
END VIEW
RECOMMENDED
SOLDERING FOOTPRINT
XXXMG
G
1
3X
0.90
XXX = Specific Device Code
2.90
M
= Date Code
G
= Pb−Free Package
*This information is generic. Please refer to
device data sheet for actual part marking.
Pb−Free indicator, “G” or microdot “ G”,
may or may not be present.
3X
0.95
0.80
PITCH
DIMENSIONS: MILLIMETERS
STYLE 1 THRU 5:
CANCELLED
STYLE 6:
STYLE 7:
PIN 1. EMITTER
2. BASE
STYLE 8:
PIN 1. BASE
2. EMITTER
3. COLLECTOR
PIN 1. ANODE
2. NO CONNECTION
3. CATHODE
3. COLLECTOR
STYLE 9:
PIN 1. ANODE
2. ANODE
STYLE 10:
STYLE 11:
STYLE 12:
STYLE 13:
PIN 1. SOURCE
2. DRAIN
STYLE 14:
PIN 1. CATHODE
2. GATE
PIN 1. DRAIN
2. SOURCE
3. GATE
PIN 1. ANODE
PIN 1. CATHODE
2. CATHODE
3. ANODE
2. CATHODE
3. CATHODE−ANODE
3. CATHODE
3. GATE
3. ANODE
STYLE 15:
STYLE 16:
STYLE 17:
PIN 1. NO CONNECTION
2. ANODE
STYLE 18:
STYLE 19:
STYLE 20:
PIN 1. GATE
2. CATHODE
3. ANODE
PIN 1. ANODE
2. CATHODE
3. CATHODE
PIN 1. NO CONNECTION PIN 1. CATHODE
PIN 1. CATHODE
2. ANODE
3. GATE
2. CATHODE
3. ANODE
2. ANODE
3. CATHODE−ANODE
3. CATHODE
STYLE 21:
STYLE 22:
STYLE 23:
PIN 1. ANODE
2. ANODE
STYLE 24:
STYLE 25:
STYLE 26:
PIN 1. GATE
2. SOURCE
3. DRAIN
PIN 1. RETURN
2. OUTPUT
3. INPUT
PIN 1. GATE
2. DRAIN
PIN 1. ANODE
2. CATHODE
3. GATE
PIN 1. CATHODE
2. ANODE
3. SOURCE
3. NO CONNECTION
3. CATHODE
STYLE 27:
STYLE 28:
PIN 1. CATHODE
2. CATHODE
3. CATHODE
PIN 1. ANODE
2. ANODE
3. ANODE
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
DOCUMENT NUMBER:
DESCRIPTION:
98ASB42226B
SOT−23 (TO−236)
PAGE 1 OF 1
ON Semiconductor and
are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.
ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding
the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically
disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the
rights of others.
© Semiconductor Components Industries, LLC, 2019
www.onsemi.com
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
TSOP−5
CASE 483
ISSUE N
5
1
DATE 12 AUG 2020
SCALE 2:1
NOTES:
1. DIMENSIONING AND TOLERANCING PER ASME
Y14.5M, 1994.
NOTE 5
5X
D
2. CONTROLLING DIMENSION: MILLIMETERS.
3. MAXIMUM LEAD THICKNESS INCLUDES LEAD FINISH
THICKNESS. MINIMUM LEAD THICKNESS IS THE
MINIMUM THICKNESS OF BASE MATERIAL.
4. DIMENSIONS A AND B DO NOT INCLUDE MOLD
FLASH, PROTRUSIONS, OR GATE BURRS. MOLD
FLASH, PROTRUSIONS, OR GATE BURRS SHALL NOT
EXCEED 0.15 PER SIDE. DIMENSION A.
5. OPTIONAL CONSTRUCTION: AN ADDITIONAL
TRIMMED LEAD IS ALLOWED IN THIS LOCATION.
TRIMMED LEAD NOT TO EXTEND MORE THAN 0.2
FROM BODY.
0.20 C A B
2X
0.10
T
M
5
4
3
2X
0.20
T
B
S
1
2
K
B
A
DETAIL Z
G
A
MILLIMETERS
TOP VIEW
DIM
A
B
C
D
MIN
2.85
1.35
0.90
0.25
MAX
3.15
1.65
1.10
0.50
DETAIL Z
J
G
H
J
K
M
S
0.95 BSC
C
0.01
0.10
0.20
0
0.10
0.26
0.60
10
3.00
0.05
H
SEATING
PLANE
END VIEW
C
_
_
SIDE VIEW
2.50
GENERIC
MARKING DIAGRAM*
SOLDERING FOOTPRINT*
1.9
5
1
5
0.074
0.95
XXXAYWG
XXX MG
0.037
G
G
1
Analog
Discrete/Logic
2.4
0.094
XXX = Specific Device Code XXX = Specific Device Code
A
Y
W
G
= Assembly Location
= Year
= Work Week
M
G
= Date Code
= Pb−Free Package
1.0
0.039
= Pb−Free Package
(Note: Microdot may be in either location)
0.7
0.028
*This information is generic. Please refer to
device data sheet for actual part marking.
Pb−Free indicator, “G” or microdot “ G”,
may or may not be present.
mm
inches
ǒ
Ǔ
SCALE 10:1
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
DOCUMENT NUMBER:
DESCRIPTION:
98ARB18753C
TSOP−5
PAGE 1 OF 1
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