SN54LS160J [ONSEMI]
BCD DECADE COUNTERS/ 4-BIT BINARY COUNTERS; BCD十进制计数器/ 4位二进制计数器
| 型号： | SN54LS160J |
| 厂家： | 
ONSEMI |
| 描述： | BCD DECADE COUNTERS/ 4-BIT BINARY COUNTERS |
| 文件： | 总6页 (文件大小：84K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
SN54/74LS160A
SN54/74LS161A
SN54/74LS162A
SN54/74LS163A
BCD DECADE COUNTERS/
4-BIT BINARY COUNTERS
The LS160A/161A/162A/163A are high-speed 4-bit synchronous count-
ers. They are edge-triggered, synchronously presettable, and cascadable
MSI building blocks for counting, memory addressing, frequency division and
other applications. The LS160A and LS162A count modulo 10 (BCD). The
LS161A and LS163A count modulo 16 (binary.)
BCD DECADE COUNTERS/
4-BIT BINARY COUNTERS
The LS160A and LS161A have an asynchronous Master Reset (Clear)
input that overrides, and is independent of, the clock and all other control
inputs. TheLS162AandLS163AhaveaSynchronousReset(Clear)inputthat
overrides all other control inputs, but is active only during the rising clock
edge.
LOW POWER SCHOTTKY
BCD (Modulo 10)
LS160A
Binary (Modulo 16)
LS161A
J SUFFIX
CERAMIC
CASE 620-09
Asynchronous Reset
Synchronous Reset
LS162A
LS163A
16
1
• Synchronous Counting and Loading
• Two Count Enable Inputs for High Speed Synchronous Expansion
• Terminal Count Fully Decoded
• Edge-Triggered Operation
• Typical Count Rate of 35 MHz
• ESD > 3500 Volts
N SUFFIX
PLASTIC
CASE 648-08
16
1
CONNECTION DIAGRAM DIP (TOP VIEW)
V
TC
15
Q
Q
Q
Q
3
CET
10
PE
9
CC
0
1
2
D SUFFIX
16
14
13
12
11
SOIC
CASE 751B-03
NOTE:
16
The Flatpak version
has the same pinouts
(Connection Diagram) as
the Dual In-Line Package.
1
ORDERING INFORMATION
*MR for LS160A and LS161A
*SR for LS162A and LS163A
SN54LSXXXJ Ceramic
SN74LSXXXN Plastic
SN74LSXXXD SOIC
1
2
3
4
5
6
8
7
*R
CP
P
P
P
P
3
CEP GND
0
1
2
PIN NAMES
LOADING (Note a)
LOGIC SYMBOL
HIGH
LOW
9
3
4
5
6
PE
Parallel Enable (Active LOW) Input
Parallel Inputs
Count Enable Parallel Input
Count Enable Trickle Input
Clock (Active HIGH Going Edge) Input
Master Reset (Active LOW) Input
Synchronous Reset (Active LOW) Input
Parallel Outputs (Note b)
1.0 U.L.
0.5 U.L.
0.5 U.L.
1.0 U.L.
0.5 U.L.
0.5 U.L.
1.0 U.L.
10 U.L.
10 U.L.
0.5 U.L.
0.25 U.L.
0.25 U.L.
0.5 U.L.
0.25 U.L.
0.25 U.L.
0.5 U.L.
P –P
0
3
PE
CEP
P
P
P
P
CEP
CET
CP
0
1
2
3
7
TC
15
CET
CP
10
2
MR
SR
*R
Q
Q
Q
Q
2 3
0
1
Q –Q
5 (2.5) U.L.
5 (2.5) U.L.
0
3
TC
Terminal Count Output (Note b)
1
14 13 12 11
= PIN 16
NOTES:
a) 1 TTL Unit Load (U.L.) = 40 µA HIGH/1.6 mA LOW.
b) The Output LOW drive factor is 2.5 U.L. for Military (54) and 5 U.L. for Commercial (74)
Temperature Ranges.
V
CC
GND = PIN 8
*MR for LS160A and LS161A
*SR for LS162A and LS163A
FAST AND LS TTL DATA
5-1
SN54/74LS160A • SN54/74LS161A
SN54/74LS162A • SN54/74LS163A
STATE DIAGRAM
LS160A • LS162A
LS161A • LS163A
LOGIC EQUATIONS
0
1
2
3
4
5
6
7
8
0
1
2
3
4
5
6
7
8
Count Enable = CEP • CET • PE
TC for LS160A & LS162A = CET • Q • Q • Q • Q
TC for LS161A & LS163A = CET • Q • Q • Q • Q
Preset = PE • CP + (rising clock edge)
Reset = MR (LS160A & LS161A)
Reset = SR • CP + (rising clock edge)
Reset = (LS162A & LS163A)
0
0
1
1
2
2
3
3
15
14
13
12
15
14
13
12
NOTE:
The LS160A and LS162A can be preset to any state,
but will not count beyond 9. If preset to state 10, 11,
12, 13, 14, or 15, it will return to its normal sequence
within two clock pulses.
11
10
9
11
10
9
FUNCTIONAL DESCRIPTION
The LS160A/161A/162A/163A are 4-bit synchronous
counters with a synchronous Parallel Enable (Load) feature.
The counters consist of four edge-triggered D flip-flops with
the appropriate data routing networks feeding the D inputs. All
changes of the Q outputs (except due to the asynchronous
Master Reset in the LS160A and LS161A) occur as a result of,
and synchronous with, the LOW to HIGH transition of the
Clock input (CP). As long as the set-up time requirements are
met, there are no special timing or activity constraints on any
of the mode control or data inputs.
Three control inputs — Parallel Enable (PE), Count Enable
Parallel (CEP) and Count Enable Trickle (CET) — select the
mode of operation as shown in the tables below. The Count
ModeisenabledwhentheCEP, CET, andPEinputsareHIGH.
When the PE is LOW, the counters will synchronously load the
data from the parallel inputs into the flip-flops on the LOW to
HIGH transition of the clock. Either the CEP or CET can be
used to inhibit the count sequence. With the PE held HIGH, a
LOW on either the CEP or CET inputs at least one set-up time
prior to the LOW to HIGH clock transition will cause the
existing output states to be retained. The AND feature of the
two Count Enable inputs (CET• CEP) allows synchronous
cascading without external gating and without delay accu-
mulation over any practical number of bits or digits.
the Binary counters). Note that TC is fully decoded and will,
therefore, be HIGH only for one count state.
The LS160A and LS162A count modulo 10 following a
binary coded decimal (BCD) sequence. They generate a TC
outputwhentheCETinputisHIGHwhilethecounterisinstate
9 (HLLH). From this state they increment to state 0 (LLLL). If
loaded with a code in excess of 9 they return to their legitimate
sequence within two counts, as explained in the state
diagram. States 10 through 15 do not generate a TC output.
The LS161A and LS163A count modulo 16 following a
binary sequence. They generate a TC when the CET input is
HIGH while the counter is in state 15 (HHHH). From this state
they increment to state 0 (LLLL).
The Master Reset (MR) of the LS160A and LS161A is
asynchronous. When the MR is LOW, it overrides all other
inputconditions and sets the outputs LOW. The MR pin should
never be left open. If not used, the MR pin should be tied
through a resistor to V , or to a gate output which is
CC
permanently set to a HIGH logic level.
The active LOW Synchronous Reset (SR) input of the
LS162A and LS163A acts as an edge-triggered control input,
overriding CET, CEP and PE, and resetting the four counter
flip-flops on the LOW to HIGH transition of the clock. This
simplifies the design from race-free logic controlled reset
circuits, e.g., to reset the counter synchronously after
reaching a predetermined value.
The Terminal Count (TC) output is HIGH when the Count
Enable Trickle (CET) input is HIGH while the counter is in its
maximum count state (HLLH for the BCD counters, HHHH for
MODE SELECT TABLE
*SR
PE
CET
CEP Action on the Rising Clock Edge (
)
L
X
L
H
H
H
X
X
H
L
X
X
H
X
L
RESET (Clear)
*For the LS162A and
*LS163A only.
H
H
H
H
LOAD (P → Q )
n
n
COUNT (Increment)
NO CHANGE (Hold)
NO CHANGE (Hold)
H = HIGH Voltage Level
L = LOW Voltage Level
X = Don’t Care
X
FAST AND LS TTL DATA
5-2
SN54/74LS160A • SN54/74LS161A
SN54/74LS162A • SN54/74LS163A
GUARANTEED OPERATING RANGES
Symbol
Parameter
Min
Typ
Max
Unit
V
CC
Supply Voltage
54
74
4.5
4.75
5.0
5.0
5.5
5.25
V
T
A
Operating Ambient Temperature Range
54
74
–55
0
25
25
125
70
°C
I
I
Output Current — High
Output Current — Low
54, 74
–0.4
mA
mA
OH
54
74
4.0
8.0
OL
LS160A and LS161A
DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified)
Limits
Symbol
Parameter
Input HIGH Voltage
Unit
Test Conditions
Min
Typ
Max
Guaranteed Input HIGH Voltage for
All Inputs
V
2.0
V
IH
54
74
0.7
0.8
Guaranteed Input LOW Voltage for
All Inputs
V
V
V
Input LOW Voltage
V
IL
Input Clamp Diode Voltage
Output HIGH Voltage
–0.65
3.5
–1.5
V
V
V
V
V
= MIN, I = –18 mA
IN
IK
CC
54
74
2.5
2.7
= MIN, I
= MAX, V = V
IN
CC
OH
IH
OH
or V per Truth Table
IL
3.5
V
V
= V
= V or V
IL
MIN,
CC
54, 74
74
0.25
0.35
0.4
0.5
V
V
I
= 4.0 mA
= 8.0 mA
CC
IN
OL
OL
V
OL
Output LOW Voltage
IH
I
per Truth Table
Input HIGH Current
MR, Data, CEP, Clock
PE, CET
20
40
µA
V
= MAX, V = 2.7 V
IN
CC
CC
I
IH
MR, Data, CEP, Clock
PE, CET
0.1
0.2
mA
V
= MAX, V = 7.0 V
IN
Input LOW Current
MR, Data, CEP, Clock
PE, CET
–0.4
–0.8
I
I
I
mA
mA
mA
V
CC
V
CC
V
CC
= MAX, V = 0.4 V
IN
IL
Short Circuit Current (Note 1)
–20
–100
= MAX
= MAX
OS
CC
Power Supply Current
Total, Output HIGH
Total, Output LOW
31
32
Note 1: Not more than one output should be shorted at a time, nor for more than 1 second.
FAST AND LS TTL DATA
5-3
SN54/74LS160A • SN54/74LS161A
SN54/74LS162A • SN54/74LS163A
LS162A and LS163A
DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified)
Limits
Symbol
Parameter
Input HIGH Voltage
Unit
Test Conditions
Min
Typ
Max
Guaranteed Input HIGH Voltage for
All Inputs
V
2.0
V
IH
54
74
0.7
0.8
Guaranteed Input LOW Voltage for
All Inputs
V
V
V
Input LOW Voltage
V
IL
Input Clamp Diode Voltage
Output HIGH Voltage
–0.65
3.5
–1.5
V
V
V
V
V
= MIN, I = –18 mA
IN
IK
CC
54
74
2.5
2.7
= MIN, I
= MAX, V = V
IN
CC
OH
IH
OH
or V per Truth Table
IL
3.5
V
V
= V
= V or V
IL
MIN,
CC
54, 74
74
0.25
0.35
0.4
0.5
V
V
I
= 4.0 mA
= 8.0 mA
CC
IN
OL
OL
V
OL
Output LOW Voltage
IH
I
per Truth Table
Input HIGH Current
Data, CEP, Clock
PE, CET, SR
20
40
µA
V
= MAX, V = 2.7 V
IN
CC
CC
I
IH
Data, CEP, Clock
PE, CET, SR
0.1
0.2
mA
V
= MAX, V = 7.0 V
IN
Input LOW Current
Data, CEP, Clock, PE, SR
CET
–0.4
–0.8
I
I
I
mA
mA
mA
V
CC
V
CC
V
CC
= MAX, V = 0.4 V
IN
IL
Short Circuit Current (Note 1)
–20
–100
= MAX
= MAX
OS
CC
Power Supply Current
Total, Output HIGH
Total, Output LOW
31
32
Note 1: Not more than one output should be shorted at a time, nor for more than 1 second.
AC CHARACTERISTICS (T = 25°C)
A
Limits
Typ
Symbol
Parameter
Unit
Test Conditions
Min
Max
f
Maximum Clock Frequency
25
32
MHz
MAX
t
t
Propagation Delay
Clock to TC
20
18
35
35
PLH
PHL
ns
ns
V
C
= 5.0 V
t
t
Propagation Delay
Clock to Q
13
18
24
27
CC
= 15 pF
PLH
PHL
L
t
t
Propagation Delay
CET to TC
9.0
9.0
14
14
PLH
PHL
ns
ns
t
MR or SR to Q
20
28
PHL
FAST AND LS TTL DATA
5-4
SN54/74LS160A • SN54/74LS161A
SN54/74LS162A • SN54/74LS163A
AC SETUP REQUIREMENTS (T = 25°C)
A
Limits
Typ
Symbol
Parameter
Clock Pulse Width Low
MR or SR Pulse Width
Setup Time, other*
Unit
ns
Test Conditions
Min
25
20
20
25
3
Max
t
t
t
t
t
t
t
CP
W
W
s
ns
ns
V
CC
= 5.0 V
Setup Time PE or SR
Hold Time, data
ns
s
ns
h
Hold Time, other
0
ns
h
Recovery Time MR to CP
15
ns
rec
*CEP, CET or DATA
DEFINITION OF TERMS
SETUP TIME (t ) — is defined as the minimum time required
s
nition. A negative HOLD TIME indicates that the correct logic
level may be released prior to the clock transition from LOW to
HIGH and still be recognized.
for the correct logic level to be present at the logic input prior to
the clock transition from LOW to HIGH in order to be recog-
nized and transferred to the outputs.
RECOVERYTIME(t )—isdefinedastheminimumtimere-
rec
HOLD TIME (t ) — is defined as the minimum time following
h
the clock transition from LOW to HIGH that the logic level must
be maintained at the input in order to ensure continued recog-
quired between the end of the reset pulse and the clock transi-
tion from LOW to HIGH in order to recognize and transfer
HIGH Data to the Q outputs.
AC WAVEFORMS
t
W
t
(H)
t (L)
W
W
MR
CP
1.3 V
t
rec
OTHER CONDITIONS:
PE = L
OTHER CONDITIONS:
PE = MR (SR) = H
CEP = CET = H
1.3 V
t
1.3 V
t
CP
Q
1.3 V
P
= P = P = P = H
0
1 2 3
PLH
PHL
t
PHL
1.3 V
1.3 V
1.3 V
Q
Q
Q
Q
2 3
0
1
Figure 1. Clock to Output Delays, Count
Frequency, and Clock Pulse Width
Figure 2. Master Reset to Output Delay, Master Reset
Pulse Width, and Master Reset Recovery Time
FAST AND LS TTL DATA
5-5
SN54/74LS160A • SN54/74LS161A
SN54/74LS162A • SN54/74LS163A
AC WAVEFORMS (continued)
COUNT ENABLE TRICKLE INPUT
TO TERMINAL COUNT OUTPUT DELAYS
1.3 V
t
1.3 V
t
CET
TC
The positive TC pulse occurs when the outputs are in the
PHL
1.3 V
OTHER CONDITIONS: CP = PE = CEP = MR = H
PLH
(Q • Q • Q • Q ) state for the LS160 and LS162 and the
0
0
1
2
3
(Q • Q • Q • Q ) state for the LS161 and LS163.
1.3 V
1
2
3
Figure 3
CLOCK TO TERMINAL COUNT DELAYS
1.3 V
t
1.3 V
1.3 V
t
CP
TC
The positive TC pulse is coincident with the output state
(Q • Q • Q • Q ) state for the LS161 and LS163 and
PLH
PHL
0
0
1
2
3
(Q • Q • Q • Q ) for the LS161 and LS163.
1.3 V
1.3 V
1
2
3
Figure 4
OTHER CONDITIONS: PE = CEP = CET = MR = H
1.3 V
1.3 V
CP
t (H)
SETUP TIME (t ) AND HOLD TIME (t )
t (L)
s
s
s
h
t (H) = 0
t (L) = 0
h
h
FOR PARALLEL DATA INPUTS
P
• P • P • P
1 2 3
1.3 V
1.3 V
1.3 V
0
The shaded areas indicate when the input is permitted to
change for predictable output performance.
Q
• Q • Q • Q
1 2 3
0
OTHER CONDITIONS: PE = L, MR = H
Figure 5
SETUP TIME (t ) AND HOLD TIME (t ) FOR
s
h
COUNT ENABLE (CEP) AND (CET) AND
PARALLEL ENABLE (PE) INPUTS
The shaded areas indicate when the input is permitted to
change for predictable output performance.
1.3 V
1.3 V
CP
t (L)
1.3 V
1.3 V
1.3 V
CP
t (H)
s
s
t (H)
s
t (L)
s
(L) = 0
t
t (H) = 0
h
h
t (H) = 0
t (L) = 0
h
h
SR or PE
CEP
1.3 V
1.3 V
1.3 V
1.3 V
PARALLEL LOAD
(See Fig. 5)
COUNT MODE
(See Fig. 7)
t (L)
s
t (H)
s
t (H) = 0
t (L) = 0
h
h
Q RESPONSE TO PE
Q RESPONSE TO SR
1.3 V
COUNT
1.3 V
CET 1.3 V
1.3 V
HOLD
COUNT OR LOAD
RESET
HOLD
Q
OTHER CONDITIONS: PE = H, MR = H
Figure 6
Figure 7
FAST AND LS TTL DATA
5-6
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