SN54LS393J [ONSEMI]
DUAL DECADE COUNTER; DUAL 4-STAGE BINARY COUNTER; 双十进制计数器;双路4级二进制计数器
| 型号： | SN54LS393J |
| 厂家： | 
ONSEMI |
| 描述： | DUAL DECADE COUNTER; DUAL 4-STAGE BINARY COUNTER |
| 文件： | 总5页 (文件大小：75K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
SN54/74LS390
SN54/74LS393
DUAL DECADE COUNTER;
DUAL 4-STAGE
BINARY COUNTER
DUAL DECADE COUNTER;
DUAL 4-STAGE
TheSN54/74LS390andSN54/74LS393eachcontainapairofhigh-speed
4-stage ripple counters. Each half of the LS390 is partitioned into a
divide-by-two section and a divide-by five section, with a separate clock input
for each section. The two sections can be connected to count in the 8.4.2.1
BCD codeortheycancountinabiquinarysequencetoprovideasquarewave
(50% duty cycle) at the final output.
BINARY COUNTER
LOW POWER SCHOTTKY
Each half of the LS393 operates as a Modulo-16 binary divider, with the last
three stages triggered in a ripple fashion. In both the LS390 and the LS393,
the flip-flops are triggered by a HIGH-to-LOW transition of their CP inputs.
Each half of each circuit type has a Master Reset input which responds to a
HIGH signal by forcing all four outputs to the LOW state.
J SUFFIX
CERAMIC
CASE 620-09
• Dual Versions of LS290 and LS293
16
1
• LS390 has Separate Clocks Allowing ÷2, ÷2.5, ÷5
• Individual Asynchronous Clear for Each Counter
• Typical Max Count Frequency of 50 MHz
N SUFFIX
PLASTIC
• Input Clamp Diodes Minimize High Speed Termination Effects
CASE 648-08
16
1
CONNECTION DIAGRAM DIP (TOP VIEW)
D SUFFIX
SOIC
CASE 751B-03
SN54/74LS390
16
V
CP
MR
Q
CP
Q
Q
Q
3
1
CC
0
0
1
1
2
16
15
14
13
12
11
10
9
J SUFFIX
CERAMIC
CASE 632-08
14
1
1
2
3
4
CP
5
6
8
7
N SUFFIX
PLASTIC
CP
MR
Q
Q
Q
Q
3
GND
0
0
1
1
2
NOTE:
CASE 646-06
The Flatpak version
has the same pinouts
(Connection Diagram) as
the Dual In-Line Package.
14
SN54/74LS393
1
V
CP
13
MR
Q
Q
Q
Q
3
CC
0
1
2
14
12
11
10
9
8
D SUFFIX
SOIC
CASE 751A-02
14
1
ORDERING INFORMATION
1
2
3
4
5
6
7
SN54LSXXXJ
Ceramic
CP
MR
Q
Q
Q
Q
3
GND
0
1
2
SN74LSXXXN Plastic
SN74LSXXXD SOIC
FAST AND LS TTL DATA
5-1
SN54/74LS390 • SN54/74LS393
PIN NAMES
LOADING (Note a)
HIGH
LOW
CP
CP
CP
Clock (Active LOW going edge)
Input to +16 (LS393)
0.5 U.L.
0.5 U.L.
1.0 U.L.
1.0 U.L.
Clock (Active LOW going edge)
Input to ÷2 (LS390)
0
1
Clock (Active LOW going edge)
Input to ÷5 (LS390)
0.5 U.L.
0.5 U.L.
10 U.L.
1.5 U.L.
0.25 U.L.
5 (2.5) U.L.
MR
Q –Q
0
Master Reset (Active HIGH) Input
Flip-Flop outputs (Note b)
3
NOTES:
a) 1 TTL Unit Load (U.L.) = 40 µA HIGH/1.6 mA LOW.
b) The Output LOW drive factor is 2.5 U.L. for Military (54) and 5 U.L. for Commercial (74)
b) Temperature Ranges.
FUNCTIONAL DESCRIPTION
Each half of the SN54/74LS393 operates in the Modulo 16
binary sequence, as indicated in the ÷16 Truth Table. The first
flip-flop is triggered by HIGH-to-LOW transitions of the CP
input signal. Each of the other flip-flops is triggered by a
HIGH-to-LOW transition of the Q output of the preceding
flip-flop. Thus state changes of the Q outputs do not occur
simultaneously. This means that logic signals derived from
combinations of these outputs will be subject to decoding
spikes and, therefore, should not be used as clocks for other
counters, registers or flip-flops. A HIGH signal on MR forces
all outputs to the LOW state and prevents counting.
section operates in 4.2.1 binary sequence, as shown in the ÷5
Truth Table, with the third stage output exhibiting a 20% duty
cycle when the input frequency is constant. To obtain a ÷10
function having a 50% duty cycle output, connect the input
signal to CP and connect the Q output to the CP input; the
1
3
0
Q output provides the desired 50% duty cycle output. If the
0
input frequency is connected to CP and the Q output is
connected to CP , a decade divider operating in the 8.4.2.1
1
0
0
BCD codeisobtained, asshownintheBCDTruthTable.Since
the flip-flops change state asynchronously, logic signals
derived from combinations of LS390 outputs are also subject
to decoding spikes. A HIGH signal on MR forces all outputs
LOW and prevents counting.
Each half of the LS390 contains a ÷5 section that is
independent except for the common MR function. The ÷5
SN54/74LS390 LOGIC DIAGRAM (one half shown)
CP
1
0
CP
K
CP
J
K
CP
J
K
CP
J
K
CP
J
C
C
C
C
D
D
D
D
Q
Q
Q
Q
MR
Q
Q
Q
Q
3
0
1
2
SN54/74LS393 LOGIC DIAGRAM (one half shown)
CP
K
CP
J
K
CP
J
K
CP
J
K
CP
J
C
C
C
C
D
D
D
D
Q
Q
Q
Q
MR
Q
Q
Q
Q
3
0
1
2
FAST AND LS TTL DATA
5-2
SN54/74LS390 • SN54/74LS393
SN54/74LS390 BCD
TRUTH TABLE
SN54/74LS390 ÷5
TRUTH TABLE
SN54/74LS393
TRUTH TABLE
(Input on CP ; Q CP )
(Input on CP )
0
0
1
1
OUTPUTS
OUTPUTS
OUTPUTS
COUNT
COUNT
COUNT
Q
Q
Q
Q
Q
Q
Q
Q
Q
Q
Q
0
3
2
1
0
3
2
1
3
2
1
0
1
2
L
L
L
L
L
L
L
L
H
L
H
L
0
1
2
3
4
L
L
L
L
H
L
L
H
L
H
L
0
1
2
3
L
L
L
L
H
L
L
H
H
L
L
L
L
L
L
L
L
H
H
H
3
4
5
L
L
L
L
H
H
H
L
L
H
L
H
4
5
6
7
L
L
L
L
H
H
H
H
L
L
H
H
L
H
L
6
7
8
9
L
L
H
H
H
H
L
H
H
L
L
H
L
H
SN54/74LS390 ÷10 (50% @ Q )
0
8
9
10
11
H
H
H
H
L
L
L
L
L
L
H
H
L
H
L
TRUTH TABLE
(Input on CP , Q to CP )
L
L
H
1
3
0
H
OUTPUTS
COUNT
12
13
14
15
H
H
H
H
H
H
H
H
L
L
H
H
L
H
L
Q
Q
Q
Q
0
3
2
1
0
1
2
L
L
L
L
L
H
L
H
L
L
L
L
H
3
4
5
L
H
L
H
L
L
H
L
L
L
L
H
H = HIGH Voltage Level
L = LOW Voltage Level
6
7
8
9
L
L
L
L
H
H
L
H
L
H
L
H
H
H
H
H
GUARANTEED OPERATING RANGES
Symbol
Parameter
Min
Typ
Max
Unit
V
CC
Supply Voltage
54
74
4.5
4.75
5.0
5.0
5.5
5.25
V
T
A
Operating Ambient Temperature Range
54
74
–55
0
25
25
125
70
°C
I
I
Output Current — High
Output Current — Low
54, 74
–0.4
mA
mA
OH
54
74
4.0
8.0
OL
FAST AND LS TTL DATA
5-3
SN54/74LS390 • SN54/74LS393
DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified)
Limits
Min
Typ
Max
Symbol
Parameter
Input HIGH Voltage
Unit
Test Conditions
Guaranteed Input HIGH Voltage for
All Inputs
V
2.0
V
IH
54
74
0.7
0.8
Guaranteed Input LOW Voltage for
All Inputs
V
V
V
Input LOW Voltage
V
IL
Input Clamp Diode Voltage
Output HIGH Voltage
–0.65
3.5
–1.5
V
V
V
V
V
= MIN, I = –18 mA
IN
IK
CC
54
74
2.5
2.7
= MIN, I
= MAX, V = V
IN
CC
OH
IH
OH
or V per Truth Table
IL
3.5
V
V
= V
= V or V
IL
MIN,
CC
54, 74
74
0.25
0.35
0.4
0.5
V
V
I
I
= 4.0 mA
= 8.0 mA
CC
IN
OL
V
Output LOW Voltage
Input HIGH Current
IH
OL
per Truth Table
OL
20
0.1
µA
mA
mA
mA
mA
mA
mA
V
V
= MAX, V = 2.7 V
IN
CC
I
IH
= MAX, V = 7.0 V
IN
CC
MR
CP, CP
–0.4
–1.6
–2.4
–100
26
I
IL
Input LOW Current
V
= MAX, V = 0.4 V
IN
0
CC
CP
1
I
I
Short Circuit Current (Note 1)
Power Supply Current
–20
V
V
= MAX
= MAX
OS
CC
CC
CC
Note 1: Not more than one output should be shorted at a time, nor for more than 1 second.
AC CHARACTERISTICS (T = 25°C, V
= 5.0 V)
CC
A
Limits
Typ
Min
Max
Symbol
Parameter
Maximum Clock Frequency
Unit
Test Conditions
f
f
25
35
MHz
MAX
CP to Q
0
0
Maximum Clock Frequency
CP to Q
20
MHz
ns
MAX
1
1
t
t
Propagation Delay,
CP to Q
12
13
20
20
PLH
PHL
LS393
0
t
t
12
13
20
20
PLH
PHL
CP to Q
LS390
LS393
LS390
LS390
LS390
ns
0
0
t
t
40
40
60
60
PLH
PHL
CP to Q
ns
3
C
= 15 pF
L
t
t
37
39
60
60
PLH
PHL
CP to Q
ns
0
2
1
2
3
t
t
13
14
21
21
PLH
PHL
CP to Q
ns
1
t
t
24
26
39
39
PLH
PHL
CP to Q
ns
1
t
t
13
14
21
21
PLH
PHL
CP to Q
LS390
ns
ns
1
t
MR to Any Output
LS390/393
24
39
PHL
FAST AND LS TTL DATA
5-4
SN54/74LS390 • SN54/74LS393
AC SETUP REQUIREMENTS (T = 25°C, V
= 5.0 V)
CC
A
Limits
Typ
Min
20
20
40
20
25
Max
Symbol
Parameter
Clock Pulse Width
Unit
ns
Test Conditions
t
t
t
t
t
LS393
LS390
LS390
W
W
W
W
rec
CP Pulse Width
0
ns
CP Pulse Width
1
ns
V
CC
= 5.0 V
MR Pulse Width
Recovery Time
LS390/393
LS390/393
ns
ns
AC WAVEFORMS
*CP
1.3 V
1.3 V
t
W
t
PLH
t
PHL
Q
1.3 V
1.3 V
Figure 1
MR & MS
1.3 V
1.3 V
t
t
rec
W
CP
Q
1.3 V
t
PHL
1.3 V
Figure 2
*The number of Clock Pulses required between t
and t
measurements can be determined from the appropriate Truth Table.
PLH
PHL
FAST AND LS TTL DATA
5-5
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