SN74LS165D [ONSEMI]
LOW POWER SCHOTTKY; 小功率肖特基
| 型号： | SN74LS165D |
| 厂家： | 
ONSEMI |
| 描述： | LOW POWER SCHOTTKY |
| 文件： | 总8页 (文件大小：135K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
The SN74LS165 is an 8-bit parallel load or serial-in register with
complementary outputs available from the last stage. Parallel inputing
occurs asynchronously when the Parallel Load (PL) input is LOW.
With PL HIGH, serial shifting occurs on the rising edge of the clock;
new data enters via the Serial Data (DS) input. The 2-input OR clock
can be used to combine two independent clock sources, or one input
can act as an active LOW clock enable.
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LOW
POWER
SCHOTTKY
GUARANTEED OPERATING RANGES
Symbol
Parameter
Supply Voltage
Min
4.75
0
Typ
5.0
25
Max
5.25
70
Unit
V
V
CC
T
A
Operating Ambient
Temperature Range
°C
I
Output Current – High
Output Current – Low
–0.4
8.0
mA
mA
OH
16
I
OL
1
PLASTIC
N SUFFIX
CASE 648
16
1
SOIC
D SUFFIX
CASE 751B
ORDERING INFORMATION
Device
Package
16 Pin DIP
16 Pin
Shipping
SN74LS165N
SN74LS165D
2000 Units/Box
2500/Tape & Reel
Semiconductor Components Industries, LLC, 1999
1
Publication Order Number:
December, 1999 – Rev. 6
SN74LS165/D
SN74LS165
CONNECTION DIAGRAM DIP (TOP VIEW)
V
CP
P
P
P
P
DS
10
Q
7
CC
2
3
2
1
0
16
15
14
13
12
11
9
NOTE:
The Flatpak version has the same
pinouts (Connection Diagram) as
the Dual In-Line Package.
1
2
3
4
5
6
8
7
PL CP
P
4
P
5
P
6
P
7
Q
7
GND
1
LOADING (Note a)
HIGH
LOW
PIN NAMES
CP , CP
DS
PL
Clock (LOW–to–HIGH Going Edge) Inputs
Serial Data Input
Asynchronous Parallel Load (Active LOW) Input
Parallel Data Inputs
Serial Output from Last State
Complementary Output
0.5 U.L.
0.5 U.L.
1.5 U.L.
0.5 U.L.
10 U.L.
10 U.L.
0.25 U.L.
0.25 U.L.
0.75 U.L.
0.25 U.L.
5 U.L.
1
2
P – P
0
7
Q
7
Q
7
5 U.L.
NOTES:
a) 1 TTL Unit Load (U.L.) = 40 A HIGH/1.6 mA LOW.
LOGIC SYMBOL
1 11 12 13 14 3 4 5 6
PL P P
S
P P P P P P
2 3 4 5 6 7
0
1
10
D
Q
7
9
7
2
15
CP
Q
7
V
CC
= PIN 16
GND = PIN 8
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2
SN74LS165
LOGIC DIAGRAM
11
12
13
14
3
4
5
6
P
0
P
1
P
2
P
3
P
4
P
5
P
6
P
7
10
2
D
S
PRESET
PRESET
PRESET
PRESET
PRESET
PRESET
PRESET
PRESET
CP
CP
1
9
7
S
Q
S
Q
S
Q
S
Q
S
Q
S
Q
S
Q
S
Q
0
1
2
3
4
5
6
7
CP
CP
CP
CP
CP
CP
CP
CP
15
2
Q
R
Q
R
Q
R
R
Q
R
Q
R
Q
R
Q
R
Q
7
C
L
2
0
1
3
4
5
6
C
C
C
C
C
C
C
L
L
L
L
L
L
L
PL
1
V
CC
= PIN 16
GND = PIN 8
= PIN NUMBERS
FUNCTIONAL DESCRIPTION
The SN74LS165 contains eight clocked master/slave RS
flip-flops connected as a shift register, with auxiliary gating
to provide overriding asynchronous parallel entry. Parallel
data enters when the PL signal is LOW. The parallel data can
change while PL is LOW, provided that the recommended
setup and hold times are observed.
by applying a HIGH signal. To avoid double clocking,
however, the inhibit signal should only go HIGH while the
clockisHIGH.Otherwise,therisinginhibitsignalwillcause
the same response as a rising clock edge. The flip-flops are
edge-triggered for serial operations. The serial input data
canchangeatanytime, providedonlythattherecommended
setup and hold times are observed, with respect to the rising
edge of the clock.
For clock operation, PL must be HIGH. The two clock
inputs perform identically; one can be used as a clock inhibit
TRUTH TABLE
CP
CONTENTS
PL
RESPONSE
1
2
Q
Q
Q
Q
Q
Q
Q
Q
0
1
2
3
4
5
6
7
L
X
L
H
X
P
D
Q
P
P
P
P
P
P
P
Parallel Entry
Right Shift
No Change
Right Shift
No Change
0
1
2
3
4
5
6
7
H
H
H
H
Q
Q
Q
Q
Q
Q
Q
Q
Q
Q
Q
Q
Q
Q
Q
Q
Q
Q
Q
Q
Q
Q
Q
Q
Q
Q
Q
Q
S
0
1
0
1
1
2
1
2
2
3
2
3
3
4
3
4
4
5
4
5
5
6
5
6
6
7
6
7
0
L
H
D
S
Q
0
H = HIGH Voltage Level
L = LOW Voltage Level
X = Immaterial
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3
SN74LS165
DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified)
Limits
Min
Typ
Max
Symbol
Parameter
Input HIGH Voltage
Unit
Test Conditions
Guaranteed Input HIGH Voltage for
All Inputs
V
V
2.0
V
IH
0.8
Guaranteed Input LOW Voltage for
All Inputs
Input LOW Voltage
V
IL
V
V
Input Clamp Diode Voltage
Output HIGH Voltage
–0.65
3.5
–1.5
V
V
V
V
= MIN, I = –18 mA
IN
IK
CC
2.7
= MIN, I = MAX, V = V
OH IN IH
OH
CC
or V per Truth Table
IL
V
V
= V MIN,
CC
0.25
0.35
0.4
0.5
V
V
I
= 4.0 mA
= 8.0 mA
CC
OL
OL
= V or V
IH
V
OL
Output LOW Voltage
IN
IL
I
per Truth Table
Input HIGH Current
Other Inputs
PL Input
20
60
µA
mA
mA
V
CC
V
CC
V
CC
= MAX, V = 2.7 V
IN
I
I
IH
Other Inputs
PL Input
0.1
0.3
= MAX, V = 7.0 V
IN
Input LOW Current
Other Inputs
PL Input
–0.4
–1.2
= MAX, V = 0.4 V
IL
IN
I
I
Short Circuit Current (Note 1)
Power Supply Current
–20
–100
36
mA
mA
V
V
= MAX
= MAX
OS
CC
CC
CC
Note 1: Not more than one output should be shorted at a time, nor for more than 1 second.
AC CHARACTERISTICS (T = 25°C)
A
Limits
Symbol
Parameter
Unit
Test Conditions
Min
Typ
Max
f
Maximum Input Clock Frequency
25
35
MHz
MAX
t
t
Propagation Delay
PL to Output
22
22
35
35
PLH
PHL
ns
ns
ns
ns
t
t
Propagation Delay
Clock to Output
27
28
40
40
PLH
PHL
V
CC
= 5.0 V
C = 15 pF
L
t
t
Propagation Delay
14
21
25
30
PLH
PHL
P to Q
7
7
t
t
Propagation Delay
P to Q
21
16
30
25
PLH
PHL
7
7
AC SETUP REQUIREMENTS (T = 25°C)
A
Limits
Typ
Symbol
Parameter
CP Clock Pulse Width
PL Pulse Width
Unit
ns
Test Conditions
Min
25
15
10
20
30
0
Max
t
t
t
t
t
t
t
W
ns
W
s
Parallel Data Setup Time
ns
Serial Data Setup Time
ns
V
CC
= 5.0 V
s
1
CP to CP Setup Time
ns
s
1
2
Hold Time
ns
h
Recovery Time, PL to CP
45
ns
rec
1
The role of CP and CP in an application may be interchanged.
1
2
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4
SN74LS165
DEFINITION OF TERMS:
SETUP TIME (t ) — is defined as the minimum time
continued recognition. A negative hold time indicates that
the correct logic level may be released prior to the clock
transition from LOW-to-HIGH and still be recognized.
s
required for the correct logic level to be present at the logic
input prior to the clock transition from LOW-to-HIGH in
order to be recognized and transferred to the outputs.
RECOVERY TIME (t ) — is defined as the minimum time
rec
HOLD TIME (t ) — is defined as the minimum time
following the clock transition from LOW-to-HIGH that the
logic level must be maintained at the input in order to ensure
required between the end of the PL pulse and the clock
transition from LOW-to-HIGH in order to recognize and
transfer loaded Data to the Q outputs.
h
AC WAVEFORMS
CP
CP
1
t
W
1/f
max
t
s
PL
1.3 V
1.3 V
1.3 V
1.3 V
t
W
1.3 V
1.3 V
2
t
t
PLH
PHL
t
PLH
t
1.3 V
Q OR Q
PHL
7
7
1.3 V
Q OR Q
1.3 V
7
7
Figure 1.
Figure 2.
1.3 V
1.3 V
1.3 V
PL
CP
1.3 V
P
n
t
t
h(L)
h(H)
t
rec
t
W
t
t
s(H)
s(L)
1.3 V
1.3 V
PL OR CP
1.3 V
Figure 3.
Figure 4.
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5
SN74LS165
PACKAGE DIMENSIONS
N SUFFIX
PLASTIC PACKAGE
CASE 648–08
ISSUE R
NOTES:
–A–
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
3. DIMENSION L TO CENTER OF LEADS WHEN
FORMED PARALLEL.
4. DIMENSION B DOES NOT INCLUDE MOLD FLASH.
5. ROUNDED CORNERS OPTIONAL.
16
1
9
8
B
S
INCHES
DIM MIN MAX
0.740 0.770 18.80 19.55
MILLIMETERS
MIN MAX
F
A
B
C
D
F
C
L
0.250 0.270
0.145 0.175
0.015 0.021
6.35
3.69
0.39
1.02
6.85
4.44
0.53
1.77
0.040
0.70
SEATING
–T–
G
H
J
K
L
M
S
0.100 BSC
0.050 BSC
0.008 0.015
2.54 BSC
1.27 BSC
PLANE
K
M
0.21
0.38
3.30
7.74
10
H
J
0.110
0.295 0.305
10
0.020 0.040
0.130
2.80
7.50
0
G
D 16 PL
0
0.51
1.01
M
M
0.25 (0.010)
T A
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6
SN74LS165
PACKAGE DIMENSIONS
D SUFFIX
PLASTIC SOIC PACKAGE
CASE 751B–05
ISSUE J
–A–
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS A AND B DO NOT INCLUDE
MOLD PROTRUSION.
16
1
9
8
–B–
P 8 PL
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.
M
S
0.25 (0.010)
B
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 (0.005) TOTAL
IN EXCESS OF THE D DIMENSION AT
MAXIMUM MATERIAL CONDITION.
G
MILLIMETERS
DIM MIN MAX
INCHES
MIN
MAX
0.393
0.157
0.068
0.019
0.049
F
A
B
C
D
F
9.80
3.80
1.35
0.35
0.40
10.00 0.386
4.00 0.150
1.75 0.054
0.49 0.014
1.25 0.016
R X 45
K
C
G
J
K
M
P
1.27 BSC
0.050 BSC
–T–
SEATING
PLANE
0.19
0.10
0
0.25 0.008
0.25 0.004
0.009
0.009
7
J
M
D
16 PL
7
0
5.80
0.25
6.20 0.229
0.50 0.010
0.244
0.019
M
S
S
0.25 (0.010)
T B
A
R
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7
SN74LS165
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SN74LS165/D
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