SN74LS175 [ONSEMI]
LOW POWER SCHOTTKY; 小功率肖特基
ONSEMI 
The LSTTL/MSI SN74LS175 is a high speed Quad D Flip-Flop.
The device is useful for general flip-flop requirements where clock
and clear inputs are common. The information on the D inputs is
stored during the LOW to HIGH clock transition. Both true and
complemented outputs of each flip-flop are provided. A Master Reset
input resets all flip-flops, independent of the Clock or D inputs, when
LOW.
The LS175 is fabricated with the Schottky barrier diode process for
high speed and is completely compatible with all ON Semiconductor
TTL families.
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LOW
POWER
SCHOTTKY
• Edge-Triggered D-Type Inputs
• Buffered-Positive Edge-Triggered Clock
• Clock to Output Delays of 30 ns
• Asynchronous Common Reset
• True and Complement Output
• Input Clamp Diodes Limit High Speed Termination Effects
16
1
GUARANTEED OPERATING RANGES
PLASTIC
N SUFFIX
CASE 648
Symbol
Parameter
Supply Voltage
Min
4.75
0
Typ
5.0
25
Max
5.25
70
Unit
V
V
CC
T
A
Operating Ambient
Temperature Range
°C
I
Output Current – High
Output Current – Low
–0.4
8.0
mA
mA
OH
I
OL
16
1
SOIC
D SUFFIX
CASE 751B
ORDERING INFORMATION
Device
Package
16 Pin DIP
16 Pin
Shipping
SN74LS175N
SN74LS175D
2000 Units/Box
2500/Tape & Reel
Semiconductor Components Industries, LLC, 1999
1
Publication Order Number:
December, 1999 – Rev. 6
SN74LS175/D
SN74LS175
CONNECTION DIAGRAM DIP (TOP VIEW)
V
Q
Q
D
D
Q
Q
2
CP
9
CC
3
3
3
2
2
16
15
14
13
12
11
10
NOTE:
The Flatpak version has the same
pinouts (Connection Diagram) as
the Dual In-Line Package.
1
2
3
4
5
6
8
7
MR
Q
0
Q
0
D
0
D
1
Q
1
Q
1
GND
LOADING (Note a)
HIGH
LOW
PIN NAMES
D – D
CP
MR
Data Inputs
0.5 U.L.
0.5 U.L.
0.5 U.L.
10 U.L.
10 U.L.
0.25 U.L.
0.25 U.L.
0.25 U.L.
5 U.L.
0
3
Clock (Active HIGH Going Edge) Input
Master Reset (Active LOW) Input
True Outputs
Q – Q
0
3
Q – Q
Complemented Outputs
5 U.L.
0
3
NOTES:
a) 1 TTL Unit Load (U.L.) = 40 A HIGH/1.6 mA LOW.
LOGIC SYMBOL
4
5
12
13
D
D
D
D
3
0
1
2
9
1
CP
MR
Q
Q
Q
Q
Q
Q
Q
Q
3 3
0
0
1
1
2
2
3
2
6
7
11 10 14 15
V
CC
= PIN 16
GND = PIN 8
LOGIC DIAGRAM
MR CP
D
3
D
2
D
1
D
0
1
9
13
12
5
4
D
Q
D
Q
D
Q
D
Q
CP Q
D
CP Q
D
CP Q
D
CP Q
C
C
C
C
D
14
15
11
10
6
7
3
2
Q Q
Q Q
Q Q
Q Q
0 0
3
3
2
2
1
1
V
CC
= PIN 16
GND = PIN 8
= PIN NUMBERS
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2
SN74LS175
FUNCTIONAL DESCRIPTION
The LS175 consists of four edge-triggered D flip-flops
withindividualDinputsandQandQoutputs. TheClockand
Master Reset are common. The four flip-flops will store the
stateoftheirindividualDinputsontheLOWtoHIGHClock
(CP) transition, causing individual Q and Q outputs to
follow. A LOW input on the Master Reset (MR) will force
all Q outputs LOW and Q outputs HIGH independent of
Clock or Data inputs.
The LS175 is useful for general logic applications where
a common Master Reset and Clock are acceptable.
TRUTH TABLE
Inputs (t = n, MR = H)
Outputs (t = n+1) Note 1
D
Q
Q
L
H
L
H
H
L
Note 1: t = n + 1 indicates conditions after next clock.
DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified)
Limits
Min
Typ
Max
Symbol
Parameter
Input HIGH Voltage
Unit
Test Conditions
Guaranteed Input HIGH Voltage for
All Inputs
V
V
2.0
V
IH
0.8
Guaranteed Input LOW Voltage for
All Inputs
Input LOW Voltage
V
IL
V
V
Input Clamp Diode Voltage
Output HIGH Voltage
–0.65
3.5
–1.5
V
V
V
V
= MIN, I = –18 mA
IN
IK
CC
2.7
= MIN, I = MAX, V = V
OH IN IH
OH
CC
or V per Truth Table
IL
V
V
= V MIN,
CC
0.25
0.35
0.4
0.5
V
V
I
I
= 4.0 mA
= 8.0 mA
CC
OL
= V or V
IH
V
Output LOW Voltage
Input HIGH Current
IN
IL
OL
per Truth Table
OL
20
0.1
µA
mA
mA
mA
mA
V
V
V
V
V
= MAX, V = 2.7 V
IN
CC
CC
CC
CC
CC
I
IH
= MAX, V = 7.0 V
IN
I
I
I
Input LOW Current
–0.4
–100
18
= MAX, V = 0.4 V
IL
IN
Short Circuit Current (Note 1)
Power Supply Current
–20
= MAX
= MAX
OS
CC
Note 1: Not more than one output should be shorted at a time, nor for more than 1 second.
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3
SN74LS175
AC CHARACTERISTICS (T = 25°C)
A
Limits
Symbol
Parameter
Unit
Test Conditions
Min
Typ
Max
f
Maximum Input Clock Frequency
30
40
MHz
MAX
t
t
20
20
30
30
PLH
PHL
V
= 5.0 V
Propagation Delay, MR to Output
Propagation Delay, Clock to Output
ns
ns
CC
C = 15 pF
L
t
t
13
16
25
25
PLH
PHL
AC SETUP REQUIREMENTS (T = 25°C)
A
Limits
Typ
Symbol
Parameter
Clock or MR Pulse Width
Data Setup Time
Unit
ns
Test Conditions
Min
20
Max
t
t
t
t
W
20
ns
s
V
CC
= 5.0 V
Data Hold Time
5.0
25
ns
h
Recovery Time
ns
rec
AC WAVEFORMS
1/f
max
t
w
CP
1.3 V
1.3 V
t
W
1.3 V
1.3 V
t
t
s(L)
MR
s(H)
t
t
h(L)
h(H)
t
rec
1.3 V
1.3 V
1.3 V
t
D
1.3 V
*
CP
Q
t
t
PLH
PHL
PHL
1.3 V
1.3 V
1.3 V
1.3 V
Q
Q
t
t
t
PLH
PHL
PLH
1.3 V
1.3 V
1.3 V
1.3 V
Q
*The shaded areas indicate when the input is permitted to
*change for predictable output performance.
Figure 1. Clock to Output Delays, Clock Pulse Width,
Frequency, Setup and Hold Times Data to Clock
Figure 2. Master Reset to Output Delay, Master Reset
Pulse Width, and Master Reset Recovery Time
DEFINITIONS OF TERMS
SETUP TIME (t ) — is defined as the minimum time
continued recognition. A negative HOLD TIME indicates
that the correct logic level may be released prior to the clock
transition from LOW to HIGH and still be recognized.
s
required for the correct logic level to be present at the logic
input prior to the clock transition from LOW to HIGH in
order to be recognized and transferred to the outputs.
RECOVERY TIME (t ) — is defined as the minimum time
rec
HOLD TIME (t ) — is defined as the minimum time
following the clock transition from LOW to HIGH that the
logic level must be maintained at the input in order to ensure
required between the end of the reset pulse and the clock
transition from LOW to HIGH in order to recognize and
transfer HIGH Data to the Q outputs.
h
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4
SN74LS175
PACKAGE DIMENSIONS
N SUFFIX
PLASTIC PACKAGE
CASE 648–08
ISSUE R
NOTES:
–A–
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
3. DIMENSION L TO CENTER OF LEADS WHEN
FORMED PARALLEL.
4. DIMENSION B DOES NOT INCLUDE MOLD FLASH.
5. ROUNDED CORNERS OPTIONAL.
16
1
9
8
B
S
INCHES
DIM MIN MAX
0.740 0.770 18.80 19.55
MILLIMETERS
MIN MAX
F
A
B
C
D
F
C
L
0.250 0.270
0.145 0.175
0.015 0.021
6.35
3.69
0.39
1.02
6.85
4.44
0.53
1.77
0.040
0.70
SEATING
–T–
G
H
J
K
L
M
S
0.100 BSC
0.050 BSC
0.008 0.015
2.54 BSC
1.27 BSC
PLANE
K
M
0.21
0.38
3.30
7.74
10
H
J
0.110
0.295 0.305
10
0.020 0.040
0.130
2.80
7.50
0
G
D 16 PL
0
0.51
1.01
M
M
0.25 (0.010)
T A
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5
SN74LS175
PACKAGE DIMENSIONS
D SUFFIX
PLASTIC SOIC PACKAGE
CASE 751B–05
ISSUE J
–A–
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS A AND B DO NOT INCLUDE
MOLD PROTRUSION.
16
1
9
8
–B–
P 8 PL
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.
M
S
0.25 (0.010)
B
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 (0.005) TOTAL
IN EXCESS OF THE D DIMENSION AT
MAXIMUM MATERIAL CONDITION.
G
MILLIMETERS
DIM MIN MAX
INCHES
MIN
MAX
0.393
0.157
0.068
0.019
0.049
F
A
B
C
D
F
9.80
3.80
1.35
0.35
0.40
10.00 0.386
4.00 0.150
1.75 0.054
0.49 0.014
1.25 0.016
R X 45
K
C
G
J
K
M
P
1.27 BSC
0.050 BSC
–T–
SEATING
PLANE
0.19
0.10
0
0.25 0.008
0.25 0.004
0.009
0.009
7
J
M
D
16 PL
7
0
5.80
0.25
6.20 0.229
0.50 0.010
0.244
0.019
M
S
S
0.25 (0.010)
T B
A
R
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6
SN74LS175
Notes
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7
SN74LS175
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PUBLICATION ORDERING INFORMATION
North America Literature Fulfillment:
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Phone: 303–675–2121 (Tue–Fri 9:00am to 1:00pm, Hong Kong Time)
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For additional information, please contact your local
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SN74LS175/D
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