SN74LS259NG [ONSEMI]
LS SERIES, LOW LEVEL TRIGGERED D LATCH, TRUE OUTPUT, PDIP16, LEAD FREE, PLASTIC, DIP-16;
| 型号： | SN74LS259NG |
| 厂家： | 
ONSEMI |
| 描述： | LS SERIES, LOW LEVEL TRIGGERED D LATCH, TRUE OUTPUT, PDIP16, LEAD FREE, PLASTIC, DIP-16 |
| 文件： | 总8页 (文件大小：146K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
The SN74LS259 is a high-speed 8-Bit Addressable Latch designed
for general purpose storage applications in digital systems. It is a
multifunctional device capable of storing single line data in eight
addressable latches, and also a 1-of-8 decoder and demultiplexer with
active HIGH outputs. The device also incorporates an active LOW
common Clear for resetting all latches, as well as, an active LOW
Enable.
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LOW
POWER
SCHOTTKY
• Serial-to-Parallel Conversion
• Eight Bits of Storage With Output of Each Bit Available
• Random (Addressable) Data Entry
• Active High Demultiplexing or Decoding Capability
• Easily Expandable
• Common Clear
GUARANTEED OPERATING RANGES
Symbol
Parameter
Supply Voltage
Min
4.75
0
Typ
5.0
25
Max
5.25
70
Unit
V
16
V
CC
1
PLASTIC
N SUFFIX
CASE 648
T
A
Operating Ambient
Temperature Range
°C
I
Output Current – High
Output Current – Low
–0.4
8.0
mA
mA
OH
I
OL
16
1
SOIC
D SUFFIX
CASE 751B
ORDERING INFORMATION
Device
Package
16 Pin DIP
16 Pin
Shipping
SN74LS259N
SN74LS259D
2000 Units/Box
2500/Tape & Reel
Semiconductor Components Industries, LLC, 1999
1
Publication Order Number:
December, 1999 – Rev. 6
SN74LS259/D
SN74LS259
CONNECTION DIAGRAM DIP (TOP VIEW)
V
CC
C
E
D
Q
7
Q
6
Q
5
Q
4
16
15
14
13
12
11
10
9
1
2
3
4
5
6
8
7
A
o
A
1
A
2
Q
0
Q
1
Q
2
Q
3
GND
LOADING (Note a)
HIGH
LOW
PIN NAMES
A , A , A
D
E
C
Address Inputs
Data Input
Enable (Active LOW) Input
Clear (Active LOW) Input
Parallel Latch Outputs
0.5 U.L.
0.5 U.L.
1.0 U.L.
0.5 U.L.
10 U.L.
0.25 U.L.
0.25 U.L.
0.5 U.L.
0.25 U.L.
5 U.L.
0
1
2
Q – Q
0
7
NOTES:
a) 1 TTL Unit Load (U.L.) = 40 A HIGH/1.6 mA LOW.
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2
SN74LS259
LOGIC DIAGRAM
E
D
A
0
A
1
A
2
C
14
13
1
2
3
15
V
CC
= PIN 16
GND = PIN 8
= PIN NUMBERS
4
5
6
7
9
10
11
12
Q
0
Q
1
Q
2
Q
3
Q
4
Q
5
Q
6
Q
7
FUNCTIONAL DESCRIPTION
The SN74LS259 has four modes of operation as shown in
the mode selection table. In the addressable latch mode, data
on the Data line (D) is written into the addressed latch.The
addressed latch will follow the data input with all
non-addressed latches remaining in their previous states. In
the memory mode, all latches remain in their previous state
and are unaffected by the Data or Address inputs.
other inputs in the LOW state. In the clear mode all outputs
are LOW and unaffected by the address and data inputs.
When operating the SN74LS259 as an addressable latch,
changing more then one bit of the address could impose a
transientwrong address. Therefore, this should only be done
while in the memory mode.
The truth table below summarizes the operations.
In the one-of-eight decoding or demultiplexing mode, the
addressed output will follow the state of the D input with all
TRUTH TABLE
MODE SELECTION
PRESENT OUTPUT STATES
E
C
MODE
C E D
A
A
A
Q
Q
Q
Q
Q
Q
Q
Q
7
MODE
Clear
Demultiplex
0
1
2
0
1
2
3
4
5
6
L
H
L
L H X
X
L
L
H
H
X
X
L
L
H
L
L
L
L
L
L
H
L
L
L
L
L
L
L
L
L
L
•
•
•
•
•
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
H
H
L
Addressable Latch
Memory
L
L
L
L
•
•
•
•
•
L
L H
L
L H
•
•
•
•
•
L
L
L
L
L
•
•
•
•
•
L
L
L
L
Active HIGH Eight-Channel
Demultiplexer
L
H
L
Clear
•
•
•
•
•
L
L H
H
X
H
H
X
L
L
L
L
L
L
L
H
H H X
X
Q
Memory
N–1
H
I
I
L
L
H
H
L
L
L
L
•
•
•
•
•
L
L
L
L
L
H
Q
Q
Q
Q
Q
Q
Q
Addressable
Latch
N–1
N–1
N–1
N–1
N–1
N–1
H L H
H L
H L H
•
•
•
•
•
N–1
L
H
L
Q
Q
N–1
N–1
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
X = Don’t Care Condition
L = LOW Voltage Level
H = HIGH Voltage Level
H L
H L H
L
H
H
H
H
H
H
Q
Q
Q
Q
L
H
N–1
N–1
N–1
N–1
Q
N–1
= Previous Output State
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3
SN74LS259
DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified)
Limits
Min
Typ
Max
Symbol
Parameter
Input HIGH Voltage
Unit
Test Conditions
Guaranteed Input HIGH Voltage for
All Inputs
V
2.0
V
IH
0.8
Guaranteed Input LOW Voltage for
All Inputs
V
V
V
Input LOW Voltage
V
V
V
IL
Input Clamp Diode Voltage
Output HIGH Voltage
–0.65
3.5
–1.5
V
V
= MIN, I = –18 mA
IN
IK
CC
= MIN, I = MAX, V = V
IH
CC
OH
IN
2.7
OH
or V per Truth Table
IL
V
V
= V MIN,
CC
0.25
0.35
0.4
0.5
V
V
I
I
= 4.0 mA
= 8.0 mA
CC
OL
= V or V
IH
V
Output LOW Voltage
Input HIGH Current
IN
IL
OL
per Truth Table
OL
20
0.1
µA
mA
mA
mA
mA
V
V
V
V
V
= MAX, V = 2.7 V
IN
CC
CC
CC
CC
CC
I
IH
= MAX, V = 7.0 V
IN
I
I
I
Input LOW Current
–0.4
–100
36
= MAX, V = 0.4 V
IL
IN
Short Circuit Current (Note 1)
Power Supply Current
–20
= MAX
= MAX
OS
CC
Note 1: Not more than one output should be shorted at a time, nor for more than 1 second.
AC CHARACTERISTICS (T = 25°C, V = 5.0 V)
A
CC
Limits
Typ
Symbol
Parameter
Unit
Test Conditions
Min
Max
t
t
Turn-Off Delay, Enable to Output
Turn-On Delay, Enable to Output
22
15
35
24
ns
ns
PLH
PHL
t
t
Turn-Off Delay, Data to Output
Turn-On Delay, Data to Output
20
13
32
21
ns
ns
PLH
PHL
C = 15 pF
L
t
t
Turn-Off Delay, Address to Output
Turn-On Delay, Address to Output
24
18
38
29
ns
ns
PLH
PHL
t
Turn-On Delay, Clear to Output
17
27
ns
PHL
AC SET-UP REQUIREMENTS (T = 25°C, V = 5.0 V)
A
CC
Limits
Typ
Symbol
Parameter
Unit
ns
Min
Max
t
t
t
t
Input Setup Time
20
15
5.0
20
s
Pulse Width, Clear or Enable
Hold Time, Data
ns
W
h
ns
Hold Time, Address
ns
h
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4
SN74LS259
AC WAVEFORMS
D
1.3 V
1.3 V
D
E
t
w
t
w
t
t
PLH
PHL
Q
1.3 V
1.3 V
1.3 V
t
t
PLH
PHL
OTHER CONDITIONS: E = L, C = H, A = STABLE
1.3 V
Q
Figure 2. Turn-on and Turn-off Delays,
Data to Output
OTHER CONDITIONS: C = H, A = STABLE
Figure 1. Turn-on and Turn-off Delays, Enable To
Output and Enable Pulse Width
A
1.3 V
1.3 V
1.3 V
1.3 V
1
D
E
t (H)
h
t (L)
h
t (L)
s
t (H)
s
1.3 V
A
1
t
t
PLH
PHL
Q
1
Q=D
Q=D
1.3 V
1.3 V
Q
OTHER CONDITIONS: C = H, A = STABLE
OTHER CONDITIONS: E = L, C = L, D = H
Figure 4. Setup and Hold Time, Data to Enable
Figure 3. Turn-on and Turn-off Delays,
Address to Output
C
Q
1.3 V
STABLE ADDRESS
A
t
s
t
PHL
1.3 V
E
OTHER CONDITIONS: E = H
Figure 5. Turn-on Delay, Clear to Output
OTHER CONDITIONS: C = H
Figure 6. Setup Time, Address to Enable
(See Notes 1 and 2)
NOTES:
1. The Address to Enable Setup Time is the time before the HIGH-to-LOW Enable transition that the Address must be stable so that the correct latch is
addressed and the other latches are not affected.
2. The shaded areas indicate when the inputs are permitted to change for predictable output performance.
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5
SN74LS259
PACKAGE DIMENSIONS
N SUFFIX
PLASTIC PACKAGE
CASE 648–08
ISSUE R
NOTES:
–A–
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
3. DIMENSION L TO CENTER OF LEADS WHEN
FORMED PARALLEL.
4. DIMENSION B DOES NOT INCLUDE MOLD FLASH.
5. ROUNDED CORNERS OPTIONAL.
16
1
9
8
B
S
INCHES
DIM MIN MAX
0.740 0.770 18.80 19.55
MILLIMETERS
MIN MAX
F
A
B
C
D
F
C
L
0.250 0.270
0.145 0.175
0.015 0.021
6.35
3.69
0.39
1.02
6.85
4.44
0.53
1.77
0.040
0.70
SEATING
–T–
G
H
J
K
L
M
S
0.100 BSC
0.050 BSC
0.008 0.015
2.54 BSC
1.27 BSC
PLANE
K
M
0.21
0.38
3.30
7.74
10
H
J
0.110
0.295 0.305
10
0.020 0.040
0.130
2.80
7.50
0
G
D 16 PL
0
0.51
1.01
M
M
0.25 (0.010)
T A
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6
SN74LS259
PACKAGE DIMENSIONS
D SUFFIX
PLASTIC SOIC PACKAGE
CASE 751B–05
ISSUE J
–A–
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS A AND B DO NOT INCLUDE
MOLD PROTRUSION.
16
1
9
8
–B–
P 8 PL
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.
M
S
0.25 (0.010)
B
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 (0.005) TOTAL
IN EXCESS OF THE D DIMENSION AT
MAXIMUM MATERIAL CONDITION.
G
MILLIMETERS
DIM MIN MAX
INCHES
MIN
MAX
0.393
0.157
0.068
0.019
0.049
F
A
B
C
D
F
9.80
3.80
1.35
0.35
0.40
10.00 0.386
4.00 0.150
1.75 0.054
0.49 0.014
1.25 0.016
R X 45
K
C
G
J
K
M
P
1.27 BSC
0.050 BSC
–T–
SEATING
PLANE
0.19
0.10
0
0.25 0.008
0.25 0.004
0.009
0.009
7
J
M
D
16 PL
7
0
5.80
0.25
6.20 0.229
0.50 0.010
0.244
0.019
M
S
S
0.25 (0.010)
T B
A
R
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7
SN74LS259
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withoutfurthernoticetoanyproductsherein. SCILLCmakesnowarranty,representationorguaranteeregardingthesuitabilityofitsproductsforanyparticular
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SN74LS259/D
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