SN74LS299 [ONSEMI]
LOW POWER SCHOTTKY; 小功率肖特基
| 型号： | SN74LS299 |
| 厂家： | 
ONSEMI |
| 描述： | LOW POWER SCHOTTKY |
| 文件： | 总8页 (文件大小：173K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
The SN74LS299 is an 8-Bit Universal Shift/Storage Register with
3-state outputs. Four modes of operation are possible: hold (store),
shift left, shift right and load data.
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The parallel load inputs and flip-flop outputs are multiplexed to
reduce the total number of package pins. Separate outputs are provided
for flip-flops Q and Q to allow easy cascading. A separate active
LOW
POWER
SCHOTTKY
0
7
LOW Master Reset is used to reset the register.
• Common I/O for Reduced Pin Count
• Four Operation Modes: Shift Left, Shift Right, Load and Store
• Separate Shift Right Serial Input and Shift Left Serial Input for Easy
Cascading
• 3-State Outputs for Bus Oriented Applications
• Input Clamp Diodes Limit High-Speed Termination Effects
• ESD > 3500 Volts
20
1
GUARANTEED OPERATING RANGES
PLASTIC
N SUFFIX
CASE 738
Symbol
Parameter
Supply Voltage
Min
4.75
0
Typ
5.0
25
Max
5.25
70
Unit
V
V
CC
T
A
Operating Ambient
Temperature Range
°C
I
Output Current – High
–0.4
8.0
mA
mA
mA
mA
OH
Q , Q
0
7
I
Output Current – Low
Q , Q
OL
20
0
7
1
I
Output Current – High
I/O – 1/O
–2.6
24
OH
0
7
SOIC
DW SUFFIX
CASE 751D
I
Output Current – Low
I/O – 1/O
OL
0
7
ORDERING INFORMATION
Device
Package
16 Pin DIP
16 Pin
Shipping
SN74LS299N
1440 Units/Box
SN74LS299DW
2500/Tape & Reel
Semiconductor Components Industries, LLC, 1999
1
Publication Order Number:
December, 1999 – Rev. 6
SN74LS299/D
SN74LS299
CONNECTION DIAGRAM DIP (TOP VIEW)
V
CC
S
1
D
s7
Q
7
I/O I/O I/O I/O CP DS
7 5 3 1
0
20 19 18 17 16 15 14 13 12
11
NOTE:
The Flatpak version has the same
pinouts (Connection Diagram) as
the Dual In-Line Package.
1
2
3
4
5
6
8
9
10
7
S
0
OE OE I/O I/O I/O I/O
Q
0
MR GND
1
2
6
4
2
0
LOADING (Note a)
HIGH
LOW
PIN NAMES
CP
DS0
DS7
Clock Pulse (Active Positive–Going Edge) Input
Serial Data Input for Right Shift
Serial Data Input for Left Shift
Parallel Data Input or
Parallel Output (3–State)
3–State Output Enable (Active LOW) Inputs
Serial Outputs
0.5 U.L.
0.5 U.L.
0.5 U.L.
0.5 U.L.
65 U.L.
0.5 U.L.
10 U.L.
0.5 U.L.
1 U.L.
0.25 U.L.
0.25 U.L.
0.25 U.L.
0.25 U.L.
15 U.L.
0.25 U.L.
5 U.L.
0.25 U.L.
0.5 U.L.
I/O
n
OE , OE
1
2
Q , Q
0
7
MR
S , S
0
Asynchronous Master Reset (Active LOW) Input
Mode Select Inputs
1
NOTES:
a) 1 TTL Unit Load (U.L.) = 40 A HIGH/1.6 mA LOW.
LOGIC DIAGRAM
S
1
S
0
1
19
18
D
S7
DS
0
11
12
CLOCK
D
D
CK
D
D
D
D
D
D
CK
CK
CK
CK
CK
CK
CK
CLR
CLR
CLR
CLR
CLR
CLR
CLR
CLR
17
8
Q
Q
Q
Q
Q
Q
Q
Q
Q
0
Q
7
MR
9
2
OE
V
= PIN 20
1
CC
OE
2
GND = PIN 10
7
13
6
14
5
15
4
16
3
= PIN NUMBERS
I/O
0
I/O
1
I/O
2
I/O
3
I/O
4
I/O
5
I/O
6
I/O
7
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2
SN74LS299
FUNCTION TABLE
INPUTS
RESPONSE
MR
S
1
S
0
OE
OE
CP
DS
DS
7
1
2
0
L
L
L
X
X
H
X
X
H
H
X
X
X
H
X
X
X
X
X
X
X
X
X
X
Asynchronous Reset; Q = Q = LOW
I/O Voltage Undetermined
0
7
L
L
L
X
X
L
L
L
L
L
X
X
X
X
X
X
Asynchronous Reset; Q = Q = LOW
0 7
I/O Voltage LOW
H
H
L
L
H
H
X
L
X
L
D
D
X
X
Shift Right; D Q ; Q Q ; etc.
0
0
1
Shift Right; D Q & I/O ; Q O & I/O ; etc.
0
0
0
1
1
H
H
H
H
L
L
X
L
X
L
X
X
D
D
Shift Left; D Q ; Q Q ; etc.
7 7 6
Shift Left; D Q & I/O ; Q Q & I/O ; etc.
7
7
7
6
6
H
H
H
X
X
X
X
Parallel Load; I/O
Q
n
n
H
H
L
L
L
L
H
X
X
H
X
X
X
X
X
X
Hold: I/O Voltage undetermined
Hold: I/O = Q
H
L
L
L
L
X
X
X
n
n
H = HIGH Voltage Level
L = LOW Voltage Level
X = Immaterial
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3
SN74LS299
DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified)
Limits
Min
Typ
Max
Symbol
Parameter
Input HIGH Voltage
Unit
Test Conditions
Guaranteed Input HIGH Voltage for
All Inputs
V
IH
2.0
V
0.8
Guaranteed Input LOW Voltage for
All Inputs
V
IL
Input LOW Voltage
V
V
V
Input Clamp Diode Voltage
Output HIGH Voltage
–0.65
3.1
–1.5
V
V
V
= MIN, I = –18 mA
IN
IK
CC
CC
2.4
2.7
OH
V
= MIN, I = MAX
OH
I/O –I/O
0
7
V
V
V
Output HIGH Voltage
Q , Q
3.4
V
OH
V
I
= MIN, I = MAX
OH
CC
0
7
V
V
= V MIN,
CC
= V or V
IH
0.25
0.35
0.4
0.5
0.4
0.5
V
V
V
V
= 12 mA
CC
OL
Output LOW Voltage
I/O –I/O
IN
IL
OL
0
7
I
OL
I
OL
I
OL
= 24 mA
= 4.0 mA
= 8.0 mA
per Truth Table
V
V
= V MIN,
CC
= V or V
IH
CC
Output LOW Voltage
I/O –I/O
IN
IL
OL
OZH
OZL
0
7
per Truth Table
I
I
Output Off Current HIGH
I/O –I/O
40
µA
V
= MAX, V
= MAX, V
= 2.7 V
CC
CC
OUT
OUT
0
7
Output Off Current LOW
I/O –I/O
–400
20
µA
µA
µA
V
= 0.4 V
0
7
Others
S , S ,
V
CC
= MAX, V = 2.7 V
IN
0
1
40
I/O –I/O
0
7
I
Input HIGH Current
Input LOW Current
IH
Others
0.1
0.2
mA
mA
mA
mA
mA
mA
mA
mA
V
CC
V
CC
V
CC
= MAX, V = 7.0 V
IN
S , S
0
1
I/O –I/O
0.1
= MAX, V = 5.5 V
IN
0
7
Others
–0.4
–0.8
–100
–130
53
I
I
= MAX, V = 0.4 V
IL
IN
S , S
0
1
Q , Q
0
–20
–30
V
CC
V
CC
V
CC
= MAX
= MAX
= MAX
7
OS
Short Circuit Current
(Note 1)
I/O –I/O
0
7
I
Power Supply Current
CC
Note 1: Not more than one output should be shorted at a time, nor for more than 1 second.
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4
SN74LS299
AC CHARACTERISTICS (T = 25°C, V = 5.0 V)
A
CC
Limits
Symbol
Parameter
Unit
Test Conditions
Min
Typ
Max
f
Maximum Clock Frequency
25
35
MHz
MAX
t
t
Propagation Delay, Clock
to Q or Q
26
22
39
33
PHL
PLH
ns
ns
ns
ns
ns
ns
C = 15 pF
0
7
L
Propagation Delay, Clear
to Q or Q
t
27
40
PHL
0
7
t
t
Propagation Delay, Clock
to I/O –I/O
26
17
39
25
PHL
PLH
0
7
Propagation Delay, Clear
to I/O –I/O
C = 45 pF,
L
t
26
40
PHL
R = 667 Ω
L
0
7
t
t
13
19
21
30
PZH
PZL
Output Enable Time
Output Disable Time
t
t
10
10
15
15
PHZ
PLZ
C = 5.0 pF
L
AC SETUP REQUIREMENTS (T = 25°C, V = 5.0 V)
A
CC
Limits
Typ
Symbol
Parameter
Clock Pulse Width HIGH
Clock Pulse Width LOW
Clear Pulse Width LOW
Data Setup Time
Unit
ns
ns
ns
ns
ns
ns
ns
ns
Test Conditions
Min
25
13
20
20
35
0
Max
t
t
t
t
t
t
t
t
W
W
W
s
V
CC
= 5.0 V
Select Setup Time
Data Hold Time
s
h
Select Hold Time
10
20
h
Recovery Time
rec
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5
SN74LS299
3-STATE WAVEFORMS
V
IN
1.3 V
1.3 V
1.3 V
1.3 V
V
IN
t
t
PHL
PLH
t
t
PHL
PLH
1.3 V
1.3 V
V
OUT
1.3 V
1.3 V
V
OUT
Figure 1.
Figure 2.
V
E
V
E
1.5 V
1.5 V
1.5 V
1.5 V
0.5 V
V
E
V
E
t
PHZ
t
t
t
PZH
PZL
PLZ
≥ V
≈ 1.5 V
0.5 V
OH
V
OUT
1.5 V
1.5 V
≈ 1.5 V
V
OL
V
OUT
Figure 3.
Figure 4.
AC LOAD CIRCUIT
SWITCH POSITIONS
V
CC
SYMBOL
SW1
Open
SW2
Closed
Open
t
PZH
R
L
t
t
Closed
Closed
Closed
PZL
PLZ
PHZ
Closed
Closed
SW1
t
TO OUTPUT
UNDER TEST
5 kΩ
C *
L
SW2
* Includes Jig and Probe Capacitance.
Figure 5.
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6
SN74LS299
PACKAGE DIMENSIONS
N SUFFIX
PLASTIC PACKAGE
CASE 738–03
ISSUE E
–A–
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
20
1
11
10
2. CONTROLLING DIMENSION: INCH.
3. DIMENSION L TO CENTER OF LEAD WHEN
FORMED PARALLEL.
4. DIMENSION B DOES NOT INCLUDE MOLD
FLASH.
B
L
C
INCHES
DIM MIN MAX
1.070 25.66
MILLIMETERS
MIN
MAX
27.17
6.60
4.57
0.55
A
B
C
D
E
F
1.010
0.240
0.150
0.015
0.050 BSC
0.050
0.260
0.180
0.022
6.10
3.81
0.39
–T–
SEATING
PLANE
K
1.27 BSC
M
0.070
1.27
1.77
N
E
G
0.100 BSC
2.54 BSC
J
0.008
0.110
0.300 BSC
0.015
0.140
0.21
2.80
7.62 BSC
0
0.51
0.38
3.55
G
F
K
L
M
N
J 20 PL
D 20 PL
M
M
0.25 (0.010)
T B
0
15
0.040
15
1.01
0.020
M
M
0.25 (0.010)
T A
D SUFFIX
PLASTIC SOIC PACKAGE
CASE 751D–05
ISSUE F
D
A
NOTES:
1. DIMENSIONS ARE IN MILLIMETERS.
2. INTERPRET DIMENSIONS AND TOLERANCES
PER ASME Y14.5M, 1994.
3. DIMENSIONS D AND E DO NOT INCLUDE MOLD
PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 PER SIDE.
5. DIMENSION B DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE PROTRUSION SHALL
BE 0.13 TOTAL IN EXCESS OF B DIMENSION AT
MAXIMUM MATERIAL CONDITION.
20
11
10
E
1
MILLIMETERS
DIM MIN
MAX
2.65
0.25
0.49
0.32
B
20X B
A
A1
B
C
D
E
e
H
h
2.35
0.10
0.35
0.23
12.65 12.95
7.40 7.60
1.27 BSC
10.05 10.55
M
S
S
T
0.25
A
B
A
0.25
0.50
0
0.75
0.90
7
L
SEATING
PLANE
18X e
A1
C
T
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7
SN74LS299
ON Semiconductor and
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withoutfurthernoticetoanyproductsherein. SCILLCmakesnowarranty,representationorguaranteeregardingthesuitabilityofitsproductsforanyparticular
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including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or
specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be
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SN74LS299/D
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