SN74LS540DW [ONSEMI]
OCTAL BUFFER/LINE DRIVER WITH 3-STATE OUTPUTS; 八路缓冲器/ 3态输出线路驱动器型号: | SN74LS540DW |
厂家: | ONSEMI |
描述: | OCTAL BUFFER/LINE DRIVER WITH 3-STATE OUTPUTS |
文件: | 总3页 (文件大小:79K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
SN54/74LS540
SN54/74LS541
OCTAL BUFFER/LINE DRIVER
WITH 3-STATE OUTPUTS
The SN54/74LS540 and SN54/74LS541 are octal buffers and line drivers
with the same functions as the LS240 and LS241, but with pinouts on the
opposite side of the package.
These device types are designed to be used as memory address drivers,
clock drivers and bus-oriented transmitters/receivers. These devices are
especially useful as output ports for the microprocessors, allowing ease of
layout and greater PC board density.
OCTAL BUFFER/LINE DRIVER
WITH 3-STATE OUTPUTS
LOW POWER SCHOTTKY
• Hysteresis at Inputs to Improve Noise Margin
• PNP Inputs Reduce Loading
• 3-State Outputs Drive Bus Lines
• Inputs and Outputs Opposite Side of Package, Allowing Easier
Interface to Microprocessors
J SUFFIX
CERAMIC
CASE 732-03
• Input Clamp Diodes Limit High-Speed Termination Effects
20
LOGIC AND CONNECTION DIAGRAMS DIP (TOP VIEW)
1
SN54/74LS540
V
CC
20 19
N SUFFIX
PLASTIC
18
17
16
15
14
13
12
11
CASE 738-03
20
1
DW SUFFIX
SOIC
CASE 751D-03
1
2
3
4
5
6
8
9
10
GND
7
20
1
SN54/74LS541
V
CC
20 19
18
17
16
15
14
13
12
11
ORDERING INFORMATION
SN54LSXXXJ
Ceramic
SN74LSXXXN Plastic
SN74LSXXXDW SOIC
1
2
3
4
5
6
8
9
10
7
GND
GUARANTEED OPERATING RANGES
Symbol
Parameter
Min
Typ
Max
Unit
V
CC
Supply Voltage
54
74
4.5
4.75
5.0
5.0
5.5
5.25
V
T
Operating Ambient Temperature Range
Output Current — High
54
74
–55
0
25
25
125
70
°C
A
I
I
54
74
–12
–15
mA
mA
OH
Output Current — Low
54
74
12
24
OL
FAST AND LS TTL DATA
5-1
SN54/74LS540 • SN54/74LS541
BLOCK DIAGRAM
LS540
LS541
(1)
(1)
E
E
E
E
1
1
(19)
(19)
INPUTS
OUTPUTS
2
2
E
E
D
LS540 LS541
1
2
(2)
(18)
(2)
(18)
D
D
Y1
D
D
Y1
L
L
H
X
X
L
L
Z
Z
H
H
Z
Z
L
1
1
H
X
L
X
H
L
(3)
(4)
(17)
(16)
(3)
(4)
(17)
(16)
Y2
Y3
Y2
Y3
2
2
L = LOW Voltage Level
H = HIGH Voltage Level
X = Immaterial
D
D
D
D
3
3
(5)
(6)
(7)
(15)
(14)
(13)
(5)
(6)
(7)
(15)
(14)
(13)
4
Y4
Y5
4
Y4
Y5
Z = High Impedance
D
D
D
D
D
D
D
D
5
6
7
8
5
6
7
8
Y6
Y6
(8)
(9)
(12)
(11)
(8)
(9)
(12)
(11)
Y7
Y8
Y7
Y8
DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified)
Limits
Min
Typ
Max
Symbol
Parameter
Input HIGH Voltage
Unit
Test Conditions
Guaranteed Input HIGH Voltage for
All Inputs
V
IH
2.0
V
54
74
0.7
0.8
Guaranteed Input LOW Voltage for
All Inputs
V
V
V
Input LOW Voltage
V
IL
Input Clamp Diode Voltage
Output HIGH Voltage
–0.65
3.4
–1.5
V
V
V
V
CC
V
CC
V
CC
= MIN, I = –18 mA
IN
IK
54, 74
54, 74
2.4
2.0
= MIN, I
= MIN, I
= –3.0 mA
OH
OH
OH
= MAX, V = 0.5 V
IL
V
V
= V
= V or V
MIN,
54, 74
74
0.25
0.4
0.5
V
V
I
= 12 mA
= 24 mA
CC
IN
CC
IL
OL
V
V
Output LOW Voltage
IH
OL
0.35
0.4
I
OL
per Truth Table
–V
T+ T–
Hysteresis
0.2
V
V
V
V
V
V
V
V
= MIN
CC
CC
CC
CC
CC
CC
CC
I
I
Output Off Current HIGH
Output Off Current LOW
20
–20
20
µA
µA
µA
mA
mA
mA
= MAX, V
= MAX, V
= 2.7 V
= 0.4 V
OZH
OUT
OUT
OZL
= MAX, V = 2.7 V
IN
I
IH
Input HIGH Current
0.1
= MAX, V = 7.0 V
IN
I
I
Input LOW Current
–0.2
–225
= MAX, V = 0.4 V
IN
IL
Short Circuit Current (Note 1)
–40
= MAX
OS
Power Supply Current
Total, Output HIGH
mA
LS540
LS541
LS540
LS541
LS540
LS541
25
32
45
52
52
55
mA
mA
mA
mA
mA
I
V
CC
= MAX
CC
Total, Output LOW
Total Output 3-State
Note 1: Not more than one output should be shorted at a time, nor for more than 1 second.
FAST AND LS TTL DATA
5-2
SN54/74LS540 • SN54/74LS541
AC CHARACTERISTICS (T = 25°C)
A
Limits
Symbol
Parameter
Unit
Test Conditions
Min
Typ
9.0
12
12
12
15
15
20
20
10
10
15
15
Max
15
15
15
18
25
32
38
38
18
18
25
29
t
t
t
t
LS540
LS541
LS540
LS541
LS540
LS541
LS540
LS541
LS540
LS541
LS540
LS541
PLH
PLH
PHL
PHL
Propagation Delay,
Data to Output
ns
V
C
R
= 5.0 V
= 45 pF
= 667 Ω
CC
L
L
Output Enable Time
to HIGH Level
t
t
t
t
ns
ns
ns
ns
PZH
PZL
PHZ
PLZ
Output Enable Time
to LOW Level
Output Disable Time
to HIGH Level
C
= 5.0 pF
L
Output Disable Time
to LOW Level
AC WAVEFORMS
V
CC
V
V
1.3 V
1.3 V
IN
R
L
t
t
PLH
PHL
1.3 V
1.3 V
OUT
SW1
Figure 1
TO OUTPUT
UNDER TEST
1.3 V
1.3 V
V
V
IN
t
t
PLH
PHL
5 k
Ω
1.3 V
1.3 V
OUT
C *
SW2
L
Figure 2
V
V
E
1.5 V
1.5 V
E
t
t
PLZ
PZL
≈
1.5 V
V
1.5 V
OUT
V
OL
SWITCH POSITIONS
0.5 V
SYMBOL
SW1
Open
SW2
Closed
Open
Figure 3
t
PZH
V
V
E
t
Closed
Closed
Closed
PZL
PLZ
PHZ
1.5 V
t
1.5 V
t
Closed
Closed
E
t
PZH
PHZ
t
≥
V
OH
1.5 V
V
1.5 V
OUT
≈
0.5 V
Figure 4
Figure 5
FAST AND LS TTL DATA
5-3
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