SN74LS92DR2 [ONSEMI]
LS SERIES, ASYN NEGATIVE EDGE TRIGGERED 3-BIT UP DIVIDE BY 12 COUNTER, PDSO14, SOIC-14;
| 型号： | SN74LS92DR2 |
| 厂家： | 
ONSEMI |
| 描述： | LS SERIES, ASYN NEGATIVE EDGE TRIGGERED 3-BIT UP DIVIDE BY 12 COUNTER, PDSO14, SOIC-14 光电二极管 逻辑集成电路 触发器 |
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SN74LS90
DECADE COUNTER;
DIVIDE-BY-TWELVE
COUNTER;
4-BIT BINARY COUNTER
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The SN54 / 74LS90, SN54 / 74LS92 and SN54 / 74LS93 are
high-speed 4-bit ripple type counters partitioned into two sections.
Each counter has a divide-by-two section and either a divide-by-five
(LS90), divide-by-six (LS92) or divide-by-eight (LS93) section which
are triggered by a HIGH-to-LOW transition on the clock inputs. Each
section can be used separately or tied together (Q to CP) to form BCD,
bi-quinary, modulo-12, or modulo-16 counters. All of the counters
have a 2-input gated Master Reset (Clear), and the LS90 also has a
2-input gated Master Set (Preset 9).
DECADE COUNTER;
DIVIDE-BY-TWELVE COUNTER;
4-BIT BINARY COUNTER
LOW POWER SCHOTTKY
• Low Power Consumption . . . Typically 45 mW
• High Count Rates . . . Typically 42 MHz
J SUFFIX
CERAMIC
CASE 632-08
• Choice of Counting Modes . . . BCD, Bi-Quinary, Divide-by-Twelve,
Binary
• Input Clamp Diodes Limit High Speed Termination Effects
14
1
PIN NAMES
LOADING (Note a)
HIGH
LOW
N SUFFIX
PLASTIC
CASE 646-06
CP
CP
CP
Clock (Active LOW going edge) Input to
÷2 Section
Clock (Active LOW going edge) Input to
÷5 Section (LS90), ÷6 Section (LS92)
0.5 U.L.
1.5 U.L.
0
1
1
0.5 U.L.
0.5 U.L.
2.0 U.L.
1.0 U.L.
14
1
Clock (Active LOW going edge) Input to
÷8 Section (LS93)
MR , MR
Master Reset (Clear) Inputs
0.5 U.L.
0.5 U.L.
10 U.L.
10 U.L.
0.25 U.L.
0.25 U.L.
5 (2.5) U.L.
5 (2.5) U.L.
1
2
2
D SUFFIX
SOIC
CASE 751A-02
MS , MS
Master Set (Preset-9, LS90) Inputs
Output from ÷2 Section (Notes b & c)
Outputs from ÷5 (LS90), ÷6 (LS92),
÷8 (LS93) Sections (Note b)
1
Q
14
0
1
Q , Q , Q
3
1
2
NOTES:
a. 1 TTL Unit Load (U.L.) = 40 μA HIGH/1.6 mA LOW.
ORDERING INFORMATION
b. The Output LOW drive factor is 2.5 U.L. for Military, (54) and 5 U.L. for commercial (74)
b. Temperature Ranges.
SN54LSXXJ
SN74LSXXN
SN74LSXXD
Ceramic
Plastic
SOIC
c. The Q Outputs are guaranteed to drive the full fan-out plus the CP input of the device.
0
1
d. To insure proper operation the rise (t ) and fall time (t ) of the clock must be less than 100 ns.
r
f
LOGIC SYMBOL
LS92
6
7
1 2
LS90
LS93
MS
14
CP
CP
14
1
CP
14
1
CP
CP
0
1
0
0
CP
1
1
1
MR
Q Q Q Q
0 1 2 3
MR
Q
Q
Q
9
Q
8
MR
Q
Q Q Q
0 1 2 3
0
1
2
3
1 2
1 2
1
2
2 3 12 9
V = PIN 5
CC
8 11
2 3 12
9
8 11
6 7 12 11
= PIN 5
V
= PIN 5
V
CC
CC
GND = PIN 10
GND = PIN 10
GND = PIN 10
NC = PIN 4, 6, 7, 13
NC = PINS 4, 13
NC = PINS 2, 3, 4, 13
©
Semiconductor Components Industries, LLC, 2006
1
Publication Order Number:
SN74LS90/D
July, 2006 − Rev. 6
SN74LS90
LOGIC DIAGRAM
CONNECTION DIAGRAM
DIP (TOP VIEW)
LS90
6
MS
MS
1
2
1
2
3
4
5
6
7
14
13
12
11
10
9
CP
MR
MR
CP
1
1
2
0
7
NC
S
S
S
R
S
D
D
D
D
J
Q
J
Q
Q
Q
Q
J
Q
Q
14
Q
0
CP
CP
K
CP
K
CP
S
CP
K
0
NC
Q
3
Q
C
C
C
C
D
D
D
D
GND
V
CC
1
2
Q
MS
1
1
2
CP
1
8
Q
MS
2
MR
MR
1
2
12
9
8
11
3
Q
Q
Q
Q
3
0
1
2
NC = NO INTERNAL CONNECTION
NOTE:
= PIN NUMBERS
= PIN 5
The Flatpak version has the same
pinouts (Connection Diagram) as
the Dual In-Line Package.
V
CC
GND = PIN 10
LOGIC DIAGRAM
CONNECTION DIAGRAM
DIP (TOP VIEW)
LS92
1
2
3
4
5
6
7
14
13
12
11
10
9
CP
CP
1
0
NC
NC
NC
NC
J
Q
Q
J
Q
J
Q
J
Q
Q
14
Q
0
CP
CP
0
1
CP
K
CP
K
CP
K
CP
K
Q
Q
Q
1
C
C
C
C
D
D
D
D
GND
V
CC
1
6
Q
MR
2
1
2
MR
MR
1
2
8
12
11
9
8
MR
Q
3
7
Q
Q
Q
Q
3
0
1
2
NC = NO INTERNAL CONNECTION
= PIN NUMBERS
= PIN 5
NOTE:
The Flatpak version has the same
pinouts (Connection Diagram) as
the Dual In-Line Package.
V
CC
GND = PIN 10
LOGIC DIAGRAM
CONNECTION DIAGRAM
DIP (TOP VIEW)
LS93
1
2
3
4
5
6
7
14
13
12
11
10
9
CP
MR
MR
CP
1
1
2
0
J
Q
Q
J
Q
Q
J
Q
Q
J
Q
Q
NC
14
CP
CP
0
1
CP
K
CP
K
CP
K
CP
K
Q
0
C
C
C
C
D
D
D
D
NC
Q
3
1
2
GND
V
CC
Q
NC
1
MR
MR
1
2
12
9
8
11
3
8
Q
NC
2
Q
Q
Q
Q
3
0
1
2
NC = NO INTERNAL CONNECTION
= PIN NUMBERS
= PIN 5
V
CC
NOTE:
GND = PIN 10
The Flatpak version has the same
pinouts (Connection Diagram) as
the Dual In-Line Package.
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2
SN74LS90
FUNCTIONAL DESCRIPTION
The LS90, LS92, and LS93 are 4-bit ripple type Decade,
Divide-By-Twelve, and Binary Counters respectively. Each
device consists of four master/slave flip-flops which are
internally connected to provide a divide-by-two section and a
C. Divide-By-Two and Divide-By-Five Counter — No
external interconnections are required. The first flip-flop is
used as a binary element for the divide-by-two function
(CP0 as the input and Q0 as the output). The CP1 input is
used to obtain binary divide-by-five operation at the Q3
output.
divide-by-five
(LS90),
divide-by-six
(LS92),
or
divide-by-eight (LS93) section. Each section has a separate
clock input which initiates state changes of the counter on the
HIGH-to-LOW clock transition. State changes of the Q
outputs do not occur simultaneously because of internal
ripple delays. Therefore, decoded output signals are subject
to decoding spikes and should not be used for clocks or
strobes. The Q0 output of each device is designed and
specified to drive the rated fan-out plus the CP1 input of the
device.
A gated AND asynchronous Master Reset (MR1 • MR2) is
provided on all counters which overrides and clocks and
resets (clears) all the flip-flops. A gated AND asynchronous
Master Set (MS1 • MS2) is provided on the LS90 which
overrides the clocks and the MR inputs and sets the outputs
to nine (HLLH).
LS92
A. Modulo 12, Divide-By-Twelve Counter — The CP1 input
must be externally connected to the Q0 output. The CP0
input receives the incoming count and Q3 produces a
symmetrical divide-by-twelve square wave output.
B. Divide-By-Two and Divide-By-Six Counter —No external
interconnections are required. The first flip-flop is used as
a binary element for the divide-by-two function. The CP1
input is used to obtain divide-by-three operation at the Q1
and Q2 outputs and divide-by-six operation at the Q3
output.
LS93
Since the output from the divide-by-two section is not
internally connected to the succeeding stages, the devices
may be operated in various counting modes.
A. 4-Bit Ripple Counter — The output Q0 must be externally
connected to input CP1. The input count pulses are
applied to input CP0. Simultaneous divisions of 2, 4, 8,
and 16 are performed at the Q0, Q1, Q2, and Q3 outputs as
shown in the truth table.
LS90
A. BCD Decade (8421) Counter — The CP1 input must be
externally connected to the Q0 output. The CP0 input
receives the incoming count and a BCD count sequence
is produced.
B. 3-Bit Ripple Counter— The input count pulses are applied
to input CP1. Simultaneous frequency divisions of 2, 4,
and 8 are available at the Q1, Q2, and Q3 outputs.
Independent use of the first flip-flop is available if the reset
function coincides with reset of the 3-bit ripple-through
counter.
B. Symmetrical Bi-quinary Divide-By-Ten Counter — The Q3
output must be externally connected to the CP0 input. The
input count is then applied to the CP1 input and a
divide-by-ten square wave is obtained at output Q0.
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3
SN74LS90
LS90
MODE SELECTION
LS92 AND LS93
MODE SELECTION
RESET
INPUTS
RESET/SET INPUTS
MR MR MS MS
OUTPUTS
OUTPUTS
Q
Q
Q
Q
1
2
1
2
0
1
2
3
MR MR
Q
Q
Q
Q
1
2
0
1
2
3
H
H
X
L
X
L
X
H
H
X
X
L
X
L
L
X
H
L
X
X
L
X
L
H
X
L
L
X
L
L
H
L
L
L
L
L
L
L
L
H
H
L
H
L
H
H
L
L
L
L
L
L
Count
Count
Count
Count
Count
Count
Count
H = HIGH Voltage Level
L = LOW Voltage Level
X = Don’t Care
H = HIGH Voltage Level
L = LOW Voltage Level
X = Don’t Care
LS90
LS92
TRUTH TABLE
LS93
TRUTH TABLE
BCD COUNT SEQUENCE
OUTPUT
OUTPUT
OUTPUT
COUNT
COUNT
COUNT
Q
Q
Q
Q
Q
Q
Q
Q
Q
Q
Q
Q
0
1
2
3
0
1
2
3
0
1
2
3
0
1
2
3
4
5
6
7
8
9
L
H
L
H
L
H
L
H
L
H
L
L
L
L
L
L
L
L
L
L
L
L
L
L
H
H
0
1
L
L
L
L
L
L
L
H
H
L
L
L
L
H
H
L
L
L
L
L
L
H
H
H
H
H
H
0
1
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
H
H
H
H
H
H
H
H
H
L
H
L
H
L
H
L
H
L
H
H
L
H
L
H
L
H
L
H
L
H
L
H
L
H
H
H
L
L
H
H
L
L
2
H
H
L
L
L
L
H
H
L
L
2
H
H
L
3
3
H
H
H
H
L
4
4
H
H
H
H
L
5
5
L
6
6
H
H
L
7
7
8
8
L
9
9
L
L
10
11
10
11
12
13
14
15
H
H
L
L
L
H
H
H
H
L
H
H
NOTE: Output Q is connected to Input
0
CP for BCD count.
1
NOTE: Output Q is connected to Input
0
CP .
1
NOTE: Output Q is connected to Input
0
CP .
1
GUARANTEED OPERATING RANGES
Symbol
Parameter
Min
Typ
Max
Unit
V
Supply Voltage
54
74
4.5
4.75
5.0
5.0
5.5
5.25
V
CC
T
A
Operating Ambient Temperature Range
54
74
−55
0
25
25
125
70
°C
I
I
Output Current — High
Output Current — Low
54, 74
−0.4
mA
mA
OH
OL
54
74
4.0
8.0
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4
SN74LS90
DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified)
Limits
Min
Typ
Max
Symbol
Parameter
Input HIGH Voltage
Unit
Test Conditions
Guaranteed Input HIGH Voltage for
All Inputs
V
2.0
V
IH
54
74
0.7
0.8
Guaranteed Input LOW Voltage for
All Inputs
V
V
V
Input LOW Voltage
V
IL
Input Clamp Diode Voltage
Output HIGH Voltage
−0.65
3.5
−1.5
V
V
V
V
V
= MIN, I = −18 mA
IN
IK
CC
54
74
2.5
2.7
V
= MIN, I
= MAX, V = V
IN
CC
OH
IH
OH
or V per Truth Table
IL
3.5
V
V
= V MIN,
54, 74
0.25
0.4
I
I
= 4.0 mA
= 8.0 mA
CC
CC
OL
OL
V
Output LOW Voltage
Input HIGH Current
= V or V
OL
IN
IL
IH
74
0.35
0.5
20
V
per Truth Table
μA
mA
V
V
= MAX, V = 2.7 V
IN
CC
CC
I
I
IH
0.1
= MAX, V = 7.0 V
IN
Input LOW Current
MS, MR
−0.4
−2.4
−3.2
−1.6
CP
mA
V
= MAX, V = 0.4 V
IL
0
CC
IN
CP (LS90, LS92)
1
CP (LS93)
1
I
I
Short Circuit Current (Note 1)
Power Supply Current
−20
−100
mA
mA
V
V
= MAX
= MAX
OS
CC
CC
CC
15
Note 1: Not more than one output should be shorted at a time, nor for more than 1 second.
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5
SN74LS90
AC CHARACTERISTICS (T = 25°C, V = 5.0 V, C = 15 pF)
A
CC
L
Limits
LS92
Typ
LS90
LS93
Typ
Min
Typ
Max
Min
32
Max
Min
32
Max
Symbol
MAX
Parameter
Unit
MHz
MHz
f
f
CP Input Clock Frequency
32
16
0
CP Input Clock Frequency
16
16
MAX
1
t
t
Propagation Delay,
10
12
16
18
10
12
16
18
10
12
16
18
PLH
PHL
ns
ns
ns
ns
ns
CP Input to Q Output
0
0
t
t
32
34
48
50
32
34
48
50
46
46
70
70
PLH
PHL
CP Input to Q Output
0
3
t
t
10
14
16
21
10
14
16
21
10
14
16
21
PLH
PHL
CP Input to Q Output
1
1
t
t
21
23
32
35
10
14
16
21
21
23
32
35
PLH
PHL
CP Input to Q Output
1
2
t
t
21
23
32
35
21
23
32
35
34
34
51
51
PLH
PHL
CP Input to Q Output
1
3
t
t
t
MS Input to Q and Q Outputs
20
26
26
30
40
40
ns
ns
ns
PLH
PHL
PHL
0
3
MS Input to Q and Q Outputs
1
2
MR Input to Any Output
26
40
26
40
AC SETUP REQUIREMENTS (T = 25°C, V = 5.0 V)
A
CC
Limits
LS92
LS90
LS93
Min
15
30
15
15
25
Max
Min
15
Max
Min
Max
Symbol
Parameter
Unit
ns
t
CP Pulse Width
15
30
W
W
W
W
rec
0
t
t
t
t
CP Pulse Width
30
ns
1
MS Pulse Width
ns
MR Pulse Width
15
25
15
25
ns
Recovery Time MR to CP
ns
RECOVERY TIME (t ) is defined as the minimum time required between the end of the reset pulse and the clock transition from HIGH-to-LOW in order to recognize
rec
and transfer HIGH data to the Q outputs
AC WAVEFORMS
*CP
1.3 V
1.3 V
1.3 V
t
W
t
t
PLH
PHL
Q
1.3 V
1.3 V
Figure 1
*The number of Clock Pulses required between the t
and t
measurements can be determined from the appropriate Truth Tables.
PHL
PLH
MR & MS
1.3 V
1.3 V
1.3 V
1.3 V
MS
CP
t
t
W
t
W
t
rec
rec
1.3 V
1.3 V
CP
Q
t
t
PHL
PLH
Q • Q
0
3
1.3 V
1.3 V
(LS90)
Figure 2
Figure 3
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6
SN74LS90
ON Semiconductor and
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All
operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights
nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications
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SN74LS90/D
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