STD24N06LT4G [ONSEMI]
单 N 沟道，逻辑电平，功率 MOSFET，60V，24A，45mΩ;
| 型号： | STD24N06LT4G |
| 厂家： | 
ONSEMI |
| 描述： | 单 N 沟道，逻辑电平，功率 MOSFET，60V，24A，45mΩ 晶体管 功率场效应晶体管 |
| 文件： | 总8页 (文件大小：82K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
NTD24N06L
Power MOSFET
24 Amps, 60 Volts
Logic Level, N−Channel DPAK
Designed for low voltage, high speed switching applications in
power supplies, converters and power motor controls and bridge
circuits.
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24 AMPERES, 60 VOLTS
Features
RDS(on) = 0.036 W (Typ)
• Pb−Free Packages are Available
N−Channel
Typical Applications
D
• Power Supplies
• Converters
• Power Motor Controls
• Bridge Circuits
G
S
MAXIMUM RATINGS (T = 25°C unless otherwise noted)
J
Rating
Symbol Value
Unit
Vdc
Vdc
Vdc
MARKING DIAGRAMS
& PIN ASSIGNMENTS
Drain−to−Source Voltage
V
60
60
DSS
DGR
Drain−to−Gate Voltage (R = 10 MW)
V
GS
4
Gate−to−Source Voltage
− Continuous
Drain
V
V
"15
"20
GS
GS
− Non−repetitive (t v10 ms)
p
4
DPAK
CASE 369C
(Surface Mount)
STYLE 2
Drain Current
− Continuous @ T = 25°C
I
I
24
10
72
Adc
Apk
A
A
D
D
2
1
− Continuous @ T = 100°C
3
− Single Pulse (t v10 ms)
I
p
DM
2
1
Gate
3
Total Power Dissipation @ T = 25°C
P
62.5
0.42
1.88
1.36
W
W/°C
W
A
D
Drain
Source
Derate above 25°C
Total Power Dissipation @ T = 25°C (Note 1)
Total Power Dissipation @ T = 25°C (Note 2)
A
A
W
4
Operating and Storage Temperature Range
T , T
−55 to
+175
°C
Drain
J
stg
4
DPAK
CASE 369D
(Straight Lead)
STYLE 2
Single Pulse Drain−to−Source Avalanche
E
162
mJ
AS
Energy − Starting T = 25°C
J
(V = 50 Vdc, V = 5.0 Vdc,
DD
GS
L = 1.0 mH, I (pk) = 18 A, V = 60 Vdc)
L
DS
1
2
Thermal Resistance
°C/W
°C
3
− Junction−to−Case
− Junction−to−Ambient (Note 1)
− Junction−to−Ambient (Note 2)
R
R
R
2.4
80
110
q
JC
JA
JA
q
q
1
2
3
Gate Drain Source
Maximum Lead Temperature for Soldering
Purposes, 1/8 in from case for 10 seconds
T
260
L
Y
= Year
Maximum ratings are those values beyond which device damage can occur.
Maximum ratings applied to the device are individual stress limit values (not
normal operating conditions) and are not valid simultaneously. If these limits are
exceeded, device functional operation is not implied, damage may occur and
reliability may be affected.
WW
24N6L
G
= Work Week
= Device Code
= Pb−Free Package
1. When surface mounted to an FR4 board using 0.5 sq. in. pad size.
2. When surface mounted to an FR4 board using minimum recommended pad
size.
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 2 of this data sheet.
©
Semiconductor Components Industries, LLC, 2005
1
Publication Order Number:
August, 2005 − Rev. 2
NTD24N06L/D
NTD24N06L
ELECTRICAL CHARACTERISTICS (T = 25°C unless otherwise noted)
J
Characteristic
Symbol
Min
Typ
Max
Unit
OFF CHARACTERISTICS
Drain−to−Source Breakdown Voltage (Note 3)
V
Vdc
(BR)DSS
60
−
71.9
69.6
−
−
(V = 0 Vdc, I = 250 mAdc)
GS
D
mV/°C
mAdc
Temperature Coefficient (Positive)
Zero Gate Voltage Drain Current
I
I
DSS
−
−
−
−
1.0
10
(V = 60 Vdc, V = 0 Vdc)
DS
GS
(V = 60 Vdc, V = 0 Vdc, T = 150°C)
DS
GS
J
Gate−Body Leakage Current (V
=
15 Vdc, V = 0 Vdc)
−
−
100
nAdc
Vdc
GS
DS
GSS
ON CHARACTERISTICS (Note 3)
Gate Threshold Voltage (Note 3)
V
GS(th)
DS(on)
DS(on)
1.0
−
1.7
5.0
2.0
−
(V = V , I = 250 mAdc)
DS
GS
D
mV/°C
mW
Threshold Temperature Coefficient (Negative)
Static Drain−to−Source On−Resistance (Note 3)
R
V
−
−
36
36
45
−
(V = 5.0 Vdc, I = 10 Adc)
GS
D
(V = 5.0 Vdc, I = 12 Adc)
GS
D
Static Drain−to−Source On−Resistance (Note 3)
(V = 5.0 Vdc, I = 20 Adc)
Vdc
−
−
−
0.9
0.9
0.78
1.2
−
−
GS
D
(V = 5.0 Vdc, I = 24 Adc)
GS
D
(V = 5.0 Vdc, I = 12 Adc, T = 150°C)
GS
D
J
Forward Transconductance (Note 3) (V = 7.0 Vdc, I = 12 Adc)
g
FS
−
19
−
mhos
pF
DS
D
DYNAMIC CHARACTERISTICS
Input Capacitance
C
iss
−
−
−
814
258
80
1140
360
115
(V = 25 Vdc, V = 0 Vdc,
DS
GS
Output Capacitance
C
oss
f = 1.0 MHz)
Transfer Capacitance
C
rss
SWITCHING CHARACTERISTICS (Note 4)
Turn−On Delay Time
ns
t
−
−
−
−
−
−
−
9.4
97
23
52
16
3.4
11
20
200
50
100
32
−
d(on)
(V = 30 Vdc, I = 24 Adc,
DD
D
Rise Time
t
r
V
G
= 5.0 Vdc,
= 9.1 W) (Note 3)
GS
Turn−Off Delay Time
Fall Time
t
d(off)
R
t
f
Gate Charge
nC
Q
T
Q
1
Q
2
(V = 48 Vdc, I = 24 Adc,
DS
D
V
= 5.0 Vdc) (Note 3)
GS
−
SOURCE−DRAIN DIODE CHARACTERISTICS
Forward On−Voltage
(I = 20 Adc, V = 0 Vdc) (Note 3)
V
SD
−
−
−
0.93
0.95
0.86
1.1
−
−
Vdc
ns
S
GS
(I = 24 Adc, V = 0 Vdc)
S
GS
(I = 24 Adc, V = 0 Vdc, T = 150°C)
S
GS
J
Reverse Recovery Time
t
−
−
−
−
49
30
−
−
−
−
rr
(I = 24 Adc, V = 0 Vdc,
S
GS
t
a
dI /dt = 100 A/ms) (Note 3)
S
t
20
b
Reverse Recovery Stored Charge
Q
0.084
mC
RR
3. Pulse Test: Pulse Width ≤ 300 ms, Duty Cycle ≤ 2%.
4. Switching characteristics are independent of operating junction temperatures.
ORDERING INFORMATION
†
Device
Package
Shipping
NTD24N06L
DPAK
75 Units / Rail
75 Units / Rail
NTD24N06LG
DPAK
(Pb−Free)
NTD24N06L−1
DPAK (Straight Lead)
75 Units / Rail
75 Units / Rail
NTD24N06L−1G
DPAK (Straight Lead)
(Pb−Free)
NTD24N06LT4
DPAK
2500 Units / Tape & Reel
2500 Units / Tape & Reel
NTD24N06LT4G
DPAK
(Pb−Free)
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
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2
NTD24N06L
50
40
30
20
10
50
5 V
V
≥ 10 V
V
= 10 V
DS
GS
4.5 V
T = 25°C
J
40
30
20
10
8 V
6 V
4 V
3.5 V
3 V
T = −55°C
J
T = 100°C
J
0
0
0
1
2
3
4
1.6
2.4
3.2
4
4.8
V
, DRAIN−TO−SOURCE VOLTAGE (VOLTS)
DS
V
, GATE−TO−SOURCE VOLTAGE (VOLTS)
GS
Figure 1. On−Region Characteristics
Figure 2. Transfer Characteristics
0.1
0.08
0.06
0.04
0.1
0.08
0.06
0.04
V
= 5 V
GS
V
= 10 V
GS
T = 100°C
J
T = 100°C
J
T = 25°C
J
T = 25°C
J
T = −55°C
J
0.02
0
0.02
0
T = −55°C
J
0
10
20
30
40
50
0
10
20
30
40
50
I , DRAIN CURRENT (AMPS)
D
I , DRAIN CURRENT (AMPS)
D
Figure 3. On−Resistance versus
Gate−to−Source Voltage
Figure 4. On−Resistance versus Drain Current
and Gate Voltage
10000
1000
2
1.8
1.6
V
= 0 V
I
V
= 12 A
GS
D
= 5 V
GS
T = 150°C
J
1.4
1.2
100
1
1
T = 100°C
J
0.8
0.6
−50 −25
0
25
50
75 100 125 150 175
0
10
20
30
40
50
60
T , JUNCTION TEMPERATURE (°C)
J
V
, DRAIN−TO−SOURCE VOLTAGE (VOLTS)
DS
Figure 5. On−Resistance Variation with
Temperature
Figure 6. Drain−to−Source Leakage Current
versus Voltage
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3
NTD24N06L
POWER MOSFET SWITCHING
Switching behavior is most easily modeled and predicted
by recognizing that the power MOSFET is charge
controlled. The lengths of various switching intervals (Dt)
are determined by how fast the FET input capacitance can
be charged by current from the generator.
The capacitance (C ) is read from the capacitance curve at
iss
a voltage corresponding to the off−state condition when
calculating t
and is read at a voltage corresponding to the
d(on)
on−state when calculating t
.
d(off)
At high switching speeds, parasitic circuit elements
complicate the analysis. The inductance of the MOSFET
source lead, inside the package and in the circuit wiring
which is common to both the drain and gate current paths,
produces a voltage at the source which reduces the gate drive
current. The voltage is determined by Ldi/dt, but since di/dt
is a function of drain current, the mathematical solution is
complex. The MOSFET output capacitance also
complicates the mathematics. And finally, MOSFETs have
finite internal gate resistance which effectively adds to the
resistance of the driving source, but the internal resistance
is difficult to measure and, consequently, is not specified.
The resistive switching time variation versus gate
resistance (Figure 9) shows how typical switching
performance is affected by the parasitic circuit elements. If
the parasitics were not present, the slope of the curves would
maintain a value of unity regardless of the switching speed.
The circuit used to obtain the data is constructed to minimize
common inductance in the drain and gate circuit loops and
is believed readily achievable with board mounted
components. Most power electronic loads are inductive; the
data in the figure is taken with a resistive load, which
approximates an optimally snubbed inductive load. Power
MOSFETs may be safely operated into an inductive load;
however, snubbing reduces switching losses.
The published capacitance data is difficult to use for
calculating rise and fall because drain−gate capacitance
varies greatly with applied voltage. Accordingly, gate
charge data is used. In most cases, a satisfactory estimate of
average input current (I
) can be made from a
G(AV)
rudimentary analysis of the drive circuit so that
t = Q/I
G(AV)
During the rise and fall time interval when switching a
resistive load, V remains virtually constant at a level
GS
known as the plateau voltage, V . Therefore, rise and fall
SGP
times may be approximated by the following:
t = Q x R /(V − V )
GSP
r
2
G
GG
t = Q x R /V
f
2
G
GSP
where
= the gate drive voltage, which varies from zero to V
V
GG
GG
R = the gate drive resistance
G
and Q and V
are read from the gate charge curve.
2
GSP
During the turn−on and turn−off delay times, gate current is
not constant. The simplest calculation uses appropriate
values from the capacitance curves in a standard equation for
voltage change in an RC network. The equations are:
t
t
= R C In [V /(V − V )]
G iss GG GG GSP
d(on)
d(off)
= R C In (V /V )
GG GSP
G
iss
2800
2400
2000
1600
1200
800
V
= 0 V
V
= 0 V
GS
DS
T = 25°C
J
C
iss
C
rss
C
iss
400
0
C
oss
C
5
rss
10
5
0
10
15
20
25
V
V
DS
GS
GATE−TO−SOURCE OR DRAIN−TO−SOURCE VOLTAGE (VOLTS)
Figure 7. Capacitance Variation
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4
NTD24N06L
1000
6
5
4
3
2
Q
T
Q
Q
2
1
V
GS
100
10
t
r
t
f
t
d(off)
t
d(on)
V
I
V
= 30 V
= 24 A
= 5 V
DS
GS
1
0
I
= 24 A
D
D
T = 25°C
J
1
0
4
8
12
16
20
1
10
R , GATE RESISTANCE (OHMS)
100
Q , TOTAL GATE CHARGE (nC)
G
G
Figure 8. Gate−To−Source and Drain−To−Source
Voltage versus Total Charge
Figure 9. Resistive Switching Time
Variation versus Gate Resistance
DRAIN−TO−SOURCE DIODE CHARACTERISTICS
24
V
= 0 V
GS
T = 25°C
J
20
16
12
8
4
0
0.6
0.68
0.76
0.84
0.92
1
V
, SOURCE−TO−DRAIN VOLTAGE (VOLTS)
SD
Figure 10. Diode Forward Voltage versus Current
SAFE OPERATING AREA
The Forward Biased Safe Operating Area curves define
the maximum simultaneous drain−to−source voltage and
drain current that a transistor can handle safely when it is
forward biased. Curves are based upon maximum peak
reliable operation, the stored energy from circuit inductance
dissipated in the transistor while in avalanche must be less
than the rated limit and adjusted for operating conditions
differing from those specified. Although industry practice is
to rate in terms of energy, avalanche energy capability is not
a constant. The energy rating decreases non−linearly with an
increase of peak current in avalanche and peak junction
temperature.
junction temperature and a case temperature (T ) of 25°C.
C
Peak repetitive pulsed power limits are determined by using
the thermal response data in conjunction with the procedures
discussed in AN569, “Transient Thermal Resistance −
General Data and Its Use.”
Although many E−FETs can withstand the stress of
drain−to−source avalanche at currents up to rated pulsed
Switching between the off−state and the on−state may
traverse any load line provided neither rated peak current
current (I ), the energy rating is specified at rated
DM
(I ) nor rated voltage (V ) is exceeded and the
continuous current (I ), in accordance with industry custom.
DM
DSS
D
transition time (t ,t ) do not exceed 10 ms. In addition the total
power averaged over a complete switching cycle must not
The energy rating must be derated for temperature as shown
in the accompanying graph (Figure 12). Maximum energy at
r f
currents below rated continuous I can safely be assumed to
exceed (T
− T )/(R ).
D
J(MAX)
C qJC
equal the values indicated.
A Power MOSFET designated E−FET can be safely used
in switching circuits with unclamped inductive loads. For
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5
NTD24N06L
SAFE OPERATING AREA
100
10
180
V
= 15 V
I
= 18 A
GS
D
160
SINGLE PULSE
10 ms
T
= 25°C
C
140
120
100 ms
100
80
1 ms
10 ms
1
60
40
dc
R
LIMIT
DS(on)
THERMAL LIMIT
PACKAGE LIMIT
20
0
0.1
0.1
1
10
100
25
50
75
100
125
150
175
V
, DRAIN−TO−SOURCE VOLTAGE (VOLTS)
DS
T , STARTING JUNCTION TEMPERATURE (°C)
J
Figure 11. Maximum Rated Forward Biased
Safe Operating Area
Figure 12. Maximum Avalanche Energy versus
Starting Junction Temperature
1.0
D = 0.5
0.2
0.1
0.05
0.02
P
(pk)
0.1
R
(t) = r(t) R
q
JC
q
JC
D CURVES APPLY FOR POWER
PULSE TRAIN SHOWN
READ TIME AT t
0.01
SINGLE PULSE
t
1
1
t
2
T
− T = P
R (t)
q
JC
J(pk)
C
(pk)
DUTY CYCLE, D = t /t
1
2
0.01
1.0E−05
1.0E−04
1.0E−03
1.0E−02
t, TIME (ms)
1.0E−01
1.0E+00
1.0E+01
Figure 13. Thermal Response
di/dt
I
S
t
rr
t
a
t
b
TIME
0.25 I
t
p
S
I
S
Figure 14. Diode Reverse Recovery Waveform
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6
NTD24N06L
PACKAGE DIMENSIONS
DPAK
CASE 369C−01
ISSUE O
NOTES:
SEATING
PLANE
−T−
1. DIMENSIONING AND TOLERANCING
PER ANSI Y14.5M, 1982.
C
2. CONTROLLING DIMENSION: INCH.
B
R
E
V
INCHES
DIM MIN MAX
MILLIMETERS
MIN
5.97
6.35
2.19
0.69
0.46
0.94
MAX
6.22
6.73
2.38
0.88
0.58
1.14
A
B
C
D
E
F
G
H
J
0.235 0.245
0.250 0.265
0.086 0.094
0.027 0.035
0.018 0.023
0.037 0.045
0.180 BSC
4
2
Z
A
K
S
1
3
U
4.58 BSC
0.034 0.040
0.018 0.023
0.102 0.114
0.090 BSC
0.87
0.46
2.60
1.01
0.58
2.89
K
L
F
J
2.29 BSC
L
R
S
U
V
Z
0.180 0.215
0.025 0.040
4.57
0.63
0.51
0.89
3.93
5.45
1.01
−−−
1.27
−−−
H
0.020
0.035 0.050
0.155 −−−
−−−
D 2 PL
M
G
0.13 (0.005)
T
STYLE 2:
PIN 1. GATE
2. DRAIN
3. SOURCE
4. DRAIN
SOLDERING FOOTPRINT*
6.20
3.0
0.244
0.118
2.58
0.101
5.80
0.228
1.6
0.063
6.172
0.243
mm
inches
ǒ
Ǔ
SCALE 3:1
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
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7
NTD24N06L
PACKAGE DIMENSIONS
DPAK
CASE 369D−01
ISSUE B
NOTES:
C
B
R
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
V
S
E
INCHES
DIM MIN MAX
MILLIMETERS
MIN
5.97
6.35
2.19
0.69
0.46
0.94
MAX
6.35
6.73
2.38
0.88
0.58
1.14
4
2
Z
A
B
C
D
E
F
G
H
J
K
R
S
V
Z
0.235 0.245
0.250 0.265
0.086 0.094
0.027 0.035
0.018 0.023
0.037 0.045
0.090 BSC
0.034 0.040
0.018 0.023
0.350 0.380
0.180 0.215
0.025 0.040
0.035 0.050
A
K
1
3
−T−
SEATING
PLANE
2.29 BSC
0.87
0.46
8.89
4.45
0.63
0.89
3.93
1.01
0.58
9.65
5.45
1.01
1.27
−−−
J
F
H
0.155
−−−
D 3 PL
STYLE 2:
G
M
T
PIN 1. GATE
0.13 (0.005)
2. DRAIN
3. SOURCE
4. DRAIN
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NTD24N06L/D
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