STK57FU394AG-E [ONSEMI]
智能功率模块 (IPM)，2-in-1 PFC 和逆变器，600 V，15 A;
| 型号： | STK57FU394AG-E |
| 厂家： | 
ONSEMI |
| 描述： | 智能功率模块 (IPM)，2-in-1 PFC 和逆变器，600 V，15 A 功率因数校正 |
| 文件： | 总18页 (文件大小：1079K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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STK57FU394AG-E
2-in-1 PFC and Inverter
Intelligent Power Module (IPM),
600 V, 15 A
The STK57FU394AG-E is a fully-integrated PFC and inverter power
stage consisting of a high-voltage driver, six motor drive IGBT’s, one
PFC IGBT, one PFC rectifier and a thermistor, suitable for driving
permanent magnet synchronous (PMSM) motors, brushless-DC (BLDC)
motors and AC asynchronous motors.
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PACKAGE PICTURE
The IGBT’s are configured in a 3-phase bridge with separate emitter
connections for the lower legs for maximum flexibility in the choice of
control algorithm.
An internal comparator and reference connected to the over-current
protection circuit allows the designer to set individual over-current
protection levels for the PFC and the inverter stages. Additionally, the
power stage has a full range of protection functions including cross-
conduction protection, external shutdown and under-voltage lockout
functions.
Features
Simple thermal design with PFC and inverter stage in one package.
PFC operating frequency up to 40kHz
SIP35 56x25.8 / SIP2A-3
Cross-conduction protection
Adjustable over-current protection level
Integrated bootstrap diodes and resistors
MARKING DIAGRAM
Certification
A B C D D
UL1557 (File Number : E339285)
STK5 7FU3 9 4AG
Typical Applications
Heat Pumps
Home Appliances
Industrial Fans
Industrial Pumps
4
8
12
13
16
20 22 24 26 28 30 32 34
19 21 23 25 27 29 31 33 35
1
5
9
STK57FU394AG = Specific Device Code
A = Year
B = Month
C = Production Site
DD = Factory Lot Code
Device marking is on package top side
HINU
HS1
Three channel
half-bridge
driver
LINU
HINV
LS1
HS2
LS2
HS3
LS3
HS1
LS1
HS2
LS2
HS3
LS3
+
LINV
single-ended
PFC driver
ORDERING INFORMATION
HINW
LINW
PFCIN
with
protection
circuits
Shipping
(Qty / Packing)
Device
Package
SIP35 56x25.8
/ SIP2A-3
STK57FU394AG-E
8 / Tube
(Pb-Free)
Figure 1. Functional Diagram
© Semiconductor Components Industries, LLC, 2016
1
Publication Order Number:
June 2016 - Rev. 0
STK57FU394AG-E/D
STK57FU394AG-E
STK57FU394
PFCL (1)
VP (16)
RC filtering for
HINx, LINx and
PFCIN not
From Op-amp
circuit
+
C1
CS
shown.
PTRIP (31)
Recommended
in noisy
environments.
RSPFC
HVGND (19)
NU (22)
ITRIP (32)
RSU
From HV
Power
Source
HINU (23)
HINV (24)
HINW (25)
LINU (26)
LINV (27)
LINW (28)
PFCIN (29)
RSV
NV (21)
NW (20)
To Op-amp
circuit
RSW
To Op-amp
circuit
VBU (12)
U (13)
+
+
RP
RTH
Controller
VBV (8)
V (9)
FLTEN (30)
TH (33)
Motor
VDD Supply
+
VBW (4)
W (5)
VDD (34)
GND (35)
+
From 15V
Power
LV Ground
Source
Figure 2. Application Schematic
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2
STK57FU394AG-E
PFCL (1)
VBU (12)
VBV (8)
DB
DB
DB
RBS
RBS
RBS
VBW (4)
RBC
VDD (34)
GND (35)
VP (16)
W (5)
V (9)
PFC
Driver
PFCIN(29)
U (13)
HVGND (19)
NU (22)
NV (21)
NW (20)
Level
Level
Level
Shifter
Shifter
Shifter
HINU (23)
HINV (24)
HINW (25)
LINU (26)
LINV (27)
LINW (28)
Logic
Logic
Logic
VDD
undervoltage
shutdown
TH (33)
VDD
FLTEN (30)
ITRIP (32)
VITRIP
Reset after
delay
PTRIP (31)
VPFCTRIP
Figure 3. Simplified Block Diagram
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3
STK57FU394AG-E
PIN FUNCTION DESCRIPTION
Pin
Name
PFCL
Description
1
4
PFC Inductor Connection to IGBT and Rectifier node
High Side Floating Supply voltage for W phase
V phase output. Internally connected to W phase high side driver ground
High Side Floating Supply voltage for V phase
V phase output. Internally connected to V phase high side driver ground
High Side Floating Supply voltage for U phase
U phase output. Internally connected to U phase high side driver ground
Positive PFC Output Voltage
VBW
W
5
8
VBV
V
9
12
13
16
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
VBU
U
VP
HVGND
NW
Negative PFC Output Voltage
Low Side Emitter Connection - Phase W
Low Side Emitter Connection - Phase V
Low Side Emitter Connection - Phase U
Logic Input High Side Gate Driver - Phase U
Logic Input High Side Gate Driver - Phase V
Logic Input High Side Gate Driver - Phase W
Logic Input Low Side Gate Driver - Phase U
Logic Input Low Side Gate Driver - Phase V
Logic Input Low Side Gate Driver – Phase W
Logic Input PFC Gate Driver
NV
NU
HINU
HINV
HINW
LINU
LINV
LINW
PFCIN
FLTEN
PTRIP
ITRIP
TH
Bidirectional FAULT output and ENABLE input
Current protection pin for PFC
Current protection pin for inverter
Thermistor output
VDD
GND
+15V Main Supply
Negative Main Supply
Note: Pins 2, 3, 6, 7, 10, 11, 14, 15, 17 and 18 are not present
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4
STK57FU394AG-E
ABSOLUTE MAXIMUM RATINGS (Notes 1, 2)
Tc=25C unless otherwise noted.
Rating
Symbol
Conditions
Value
Unit
PFC Section
V
Collector-emitter voltage
PFCL to HVGND
600
72
36
18
73
600
60
30
15
56
11
5
V
A
CE
Repetitive peak collector current
PFC
ICP
Duty cycle 10%, pulse width 1ms
A
IGBT
Collector current
IC
A
Tc=100C
Maximum power dissipation
Diode reverse voltage
PC
W
V
VRM
IFP1
VP to PFCL
Repetitive peak forward current
PFC
Duty cycle 10%, pulse width 1ms
A
A
Diode
Diode forward current
IF1
A
Tc=100C
Maximum power dissipation
PD1
IFP2
IF2
W
A
Repetitive peak forward current
Anti-
parallel Diode forward current
Duty cycle 10%, pulse width 1ms
A
Diode
Maximum power dissipation
PD2
VAC
Vo
10
264
450
15
W
V
Maximum AC input voltage
Maximum output voltage
Input AC current (steady state)
Inverter Section
Single-phase Full-rectified
V
In the Application Circuit
(VAC=200V)
Iin
Arms
VP to NU, NV, NW surge < 500V
(Note 3)
VP to U, V, W or U to NU, V to NV, W
to NW
VP, U, V, W, NU, NV, NW terminal
current
VP, U, V, W, NU, NV, NW terminal
current at Tc=100C
V
Supply voltage
450
600
±15
±8
V
V
A
A
CC
V
max
Collector-emitter voltage
CE
Output current
Io
VP, U, V, W, NU, NV, NW terminal
current, pulse width 1ms
Output peak current
Iop
Pd
±30
35
A
Maximum power dissipation
IGBT per 1 channel
W
Gate driver section
VBU to U, VBV to V, VBW to W, VDD
to GND (Note 4)
HINU, HINV, HINW, LINU, LINV,
LINW, PFCIN
V
, V
BS DD
Gate driver supply voltage
Input signal voltage
V
V
0.3 to +20.0
0.3 to V
VIN
DD
0.3 to V
FLTEN terminal voltage
ITRIP terminal voltage
PFCTRIP terminal voltage
Intelligent Power Module
Junction temperature
VFLTEN
VITRIP
FLTEN terminal
ITRIP terminal
PTRIP terminal
V
V
V
DD
0.3 to +10.0
1.5 to +2.0
VPTRIP
Tj
IGBT, FRD, Gate driver IC
150
C
C
Storage temperature
Tstg
Tc
45 to +125
30 to +100
0.9
Operating case temperature
Tightening torque
IPM case temperature
Case mounting screws
C
MT
Nm
50Hz sine wave AC 1 minute
(Note 5)
Isolation voltage
Vis
2000
Vrms
1. Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device
functionality should not be assumed, damage may occur and reliability may be affected.
2. Refer to ELECTRICAL CHARACTERISTICS, RECOMMENDED OPERATING RANGES and/or APPLICATION INFORMATION for
Safe Operating parameters.
3. This surge voltage developed by the switching operation due to the wiring inductance between VP and NU, NV, NW terminals.
4. VBS=VBU to U, VBV to V, VBW to W
5. Test conditions : AC2500V, 1 s
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5
STK57FU394AG-E
RECOMMENDED OPERATING RANGES (Note 6)
Rating
Symbol
Min
0
Typ
Max
400
17.5
16.5
5.0
0.3
40
Unit
V
V
Supply voltage
VP to HVGND, NU, NV, NW
280
CC
V
VBU to U, VBV to V, VBW to W
12.5
13.5
2.5
0
15
15
-
V
BS
Gate driver supply voltage
V
V
to GND (Note 6)
DD
V
DD
ON-state input voltage
OFF-state input voltage
PWM frequency(PFC)
PWM frequency(Inverter)
Dead time
VIN(ON)
VIN(OFF)
fPWMp
fPWMi
DT
V
HINU, HINV, HINW, LINU, LINV, LINW,
PFCIN
-
V
1
-
kHz
kHz
μs
μs
Nm
1
-
20
Turn-off to Turn-on (external)
ON and OFF
1.5
1
-
-
Allowable input pulse width
Tightening torque
PWIN
-
-
‘M3’ type screw
0.6
-
0.9
6. Functional operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to
stresses beyond the Recommended Operating Ranges limits may affect device reliability.
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6
STK57FU394AG-E
ELECTRICAL CHARACTERISTICS (Note 7)
Tc=25C, V
(V , V )=15V unless otherwise noted.
BIAS BS DD
Parameter
Test Conditions
Symbol
Min
Typ
Max
Unit
PFC Section
V
=600V
I
Collector-emitter cut-off current
Reverse leakage current (PFC Diode)
-
-
-
-
-
-
-
-
-
-
0.1
0.1
2.5
-
mA
mA
V
CE
CE
VR=600V
IR
-
IC=30A, Tj=25°C
IC=15A, Tj=100°C
IF=30A, Tj=25°C
IF=15A, Tj=100°C
IF=5A, Tj=25°C
IGBT
1.9
1.6
2.0
1.5
1.7
-
V
(sat)
Collector-emitter saturation voltage
CE
V
2.6
-
V
Diode forward voltage (PFC Diode)
Diode forward voltage (Anti-parallel Diode)
Junction to case thermal resistance
Switching characteristics
VF1
VF2
2.3
1.7
2.2
V
θj-c(T)
θj-c(D)
°C/W
°C/W
PFC Diode
-
tON
tOFF
trr
0.1
0.1
-
0.3
0.4
60
0.8
0.9
-
μs
μs
ns
Switching time
IC=30A, VP=300V, Tj=25C
Diode reverse recovery time
Inverter section
V
=600V
I
Collector-emitter leakage current
Bootstrap diode reverse current
-
-
100
μA
μA
V
CE
CE
VR(DB)=600V
IC=15A, Tj=25C
IC=8A, Tj=100C
IF=15A, Tj=25C
IF=8A, Tj=100C
IGBT
IR(BD)
-
-
100
-
2.0
1.7
2.1
1.7
-
2.6
V
(SAT)
Collector to emitter saturation voltage
Diode forward voltage
CE
-
-
V
-
2.7
V
VF
-
-
V
Junction to case thermal resistance
Junction to case thermal resistance
θj-c(T)
θj-c(D)
tON
-
3.5
C/W
C/W
μs
μs
μJ
μJ
μJ
μJ
μJ
μJ
μJ
ns
FRD
-
-
7.2
0.1
0.5
0.7
200
150
350
300
200
500
100
200
1.0
IC = 15A, V =300V, Tj=25C
Switching time
CC
tOFF
0.2
1.2
Turn-on switching loss
Turn-off switching loss
Total switching loss
EON
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
IC = 15A, V =300V, Tj=25C
EOFF
ETOT
EON
CC
Turn-on switching loss
Turn-off switching loss
Total switching loss
IC = 15A, V =300V, Tj=100C
EOFF
ETOT
EREC
trr
CC
Diode reverse recovery energy
Diode reverse recovery time
IC = 15A, V =300V, Tj=100C
(di/dt set by internal driver)
CC
Full
Square
Ic=30A, V =450V
CE
Reverse bias safe operating area
RBSOA
-
V
=400V, Tj=100C
Short circuit safe operating area
Allowable offset voltage slew rate
SCSOA
dv/dt
4
-
-
-
μs
CE
U to NU, V to NV, W to NW
50
V/ns
50
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7
STK57FU394AG-E
Parameter
Test Conditions
Symbol
Min
Typ
Max
Unit
Driver Section
V
V
=15V (Note 4), per driver
=15V, total
ID
-
0.08
0.85
-
0.4
2.4
-
mA
mA
V
BS
Gate driver consumption current
ID
-
DD
High level Input voltage
Low level Input voltage
Logic 1 input current
VIN H
VIN L
IIN+
2.5
HINU, HINV, HINW, LINU, LINV, LINW,
PFCIN to GND
-
-
-
-
-
0.8
143
2
V
VIN=+3.3V
VIN=0V
100
-
μA
μA
V
Logic 0 input current
IIN-
Bootstrap diode forward voltage
IF=0.1A
VF(DB)
0.8
-
Resistor value for common boot charge
line
Resister values for separate boot
charge lines
RBC
RBS
-
-
22
22
-
-
Ω
Ω
Bootstrap circuit resistance
FLTEN terminal sink current
FLTEN clearance delay time
FLTEN : ON / VFAULT=0.1V
IoSD
-
1.3
2
1.65
-
-
2.0
mA
ms
V
FLTCLR
VEN(ON)
VEN(OFF)
VITRIP
VPTRIP
tITRIP
VEN ON-state voltage
VEN OFF-state voltage
ITRIP to GND
2.5
-
FLTEN Threshold
-
-
0.8
V
ITRIP threshold voltage
0.44
0.37
490
440
0.49
0.31
600
550
0.54
0.25
850
800
V
PTRIP threshold voltage
PTRIP to GND
V
ITRIP to shutdown propagation delay
PTRIP to shutdown propagation delay
ns
ns
tPTRIP
tITRIPBL
tPFCTRIPBL
ITRIP and PTRIP blanking time
290
10.5
10.3
0.14
350
11.1
10.9
0.2
-
ns
V
V
and V
supply undervoltage
BS
VDDUV+
VBSUV+
DD
positive going input threshold
and V supply undervoltage
11.7
11.5
-
V
VDDUV-
VBSUV-
DD
negative going input threshold
and V supply undervoltage Iockout
BS
V
V
VDDUVH
VBSUVH
DD
hysteresis
BS
V
7. Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted.
Product performance may not be indicated by the Electrical Characteristics if operated under different conditions.
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8
STK57FU394AG-E
TYPICAL CHARACTERISTICS PFC SECTION
60
50
40
30
20
10
0
60
50
40
30
TJ = 25°C
TJ = 100°C
20
10
0
TJ = 100°C
TJ = 25°C
0
0.5
1
1.5
2
2.5
3
3.5
4
0
0.5
1
1.5
2
2.5
3
3.5
4
VCE, COLLECTOR-EMITTERVOLTAGE (V)
VF, FORWARD VOLTAGE (V)
Figure 4. V
versus IC for different temperatures
Figure 5. PFC Diode VF versus IF for different
temperatures
CE
(V =15V)
DD
2.5
1.2
0.9
0.6
0.3
0
VCE = 300V
DD = 15V
VCE = 300V
VDD = 15V
V
2
1.5
1
TJ = 100°C
TJ = 100°C
TJ = 25°C
TJ = 25°C
0.5
0
0
10
20
30
40
50
60
70
0
10
20
30
40
50
60
70
IC, COLLECTOR CURRENT (A)
IC, COLLECTOR CURRENT (A)
Figure 6. EON versus IC for different temperatures
Figure 7. EOFF versus IC for different temperatures
1.0
0.8
0.6
0.4
0.2
0.0
0.000001
0.0001
0.01
1
100
ON-PULSE WIDTH (S)
Figure 8. Thermal Impedance Plot
600
500
400
300
200
100
0
60
600
500
400
300
200
100
0
60
50
40
30
20
10
0
50
40
30
20
10
0
VCE
IC
VCE
IC
-100
-10
-100
-10
-1 -0.8 -0.6 -0.4 -0.2
0
0.2 0.4 0.6 0.8
1
-1 -0.8 -0.6 -0.4 -0.2
0
0.2 0.4 0.6 0.8
1
Time (μs)
Time (μs)
Figure 9. Turn-on waveform Tj=100°C, V =300V
CC
Figure 10. Turn-off waveform Tj=100°C, V =300V
CC
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9
STK57FU394AG-E
TYPICAL CHARACTERISTICS INVERTER SECTION
30
30
25
20
15
10
5
25
TJ = 25°C
20
15
10
5
TJ = 100°C
TJ = 25°C
TJ = 100°C
0
0
0
0.5
1
1.5
2
2.5
3
3.5
4
0
0.5
1
1.5
2
2.5
3
3.5
4
VF, FORWARD VOLTAGE (V)
VCE, COLLECTOR-EMITTERVOLTAGE (V)
Figure 11. V
versus ID for different temperatures
Figure 12. VF versus ID for different temperatures
CE
(V =15V)
DD
1.5
0.8
0.6
0.4
0.2
0
VCE = 300V
VDD = 15V
VCE = 300V
DD = 15V
V
1
0.5
0
TJ = 100°C
TJ = 100°C
TJ = 25°C
TJ = 25°C
0
5
10
15
20
25
30
35
0
5
10
15
20
25
30
35
IC, COLLECTOR CURRENT (A)
IC, COLLECTOR CURRENT (A)
Figure 13. EON versus ID for different temperatures
Figure 14. EOFF versus ID for different temperatures
1.0
0.8
0.6
0.4
0.2
0.0
0.000001
0.0001
0.01
1
100
ON-PULSE WIDTH (S)
Figure 15. Thermal Impedance Plot
600
500
400
300
200
100
0
60
50
40
30
20
10
0
600
500
400
300
200
100
0
60
50
40
30
20
10
0
VCE
IC
IC
VCE
-100
-10
-100
-10
-1 -0.8 -0.6 -0.4 -0.2
0
0.2 0.4 0.6 0.8
1
-1 -0.8 -0.6 -0.4 -0.2
0
0.2 0.4 0.6 0.8
1
Time (μs)
Time (μs)
Figure 16. Turn-on waveform Tj=100°C, V =300V
CC
Figure 17. Turn-off waveform Tj=100°C, V =300V
CC
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STK57FU394AG-E
APPLICATIONS INFORMATION
Input / Output Timing Chart
Figure 18. nput / Output Timing Chart
Notes
1. This section of the timing diagram shows the effect of cross-conduction prevention.
2. This section of the timing diagram shows that when the voltage on V decreases sufficiently all gate output signals will go low,
DD
rises sufficiently, normal operation will resume.
switching off all six IGBTs. When the voltage on V
DD
3. This section shows that when the bootstrap voltage on VBU (VBV, VBW) drops, the corresponding high side output U (V, W) is
switched off. When the voltage on VBU (VBV, VBW) rises sufficiently, normal operation will resume.
4. This section shows that when the voltage on ITRIP exceeds the threshold, all IGBT’s are turned off. Normal operation resumes
later after the over-current condition is removed. Similarly, when the voltage on PTRIP exceeds the threshold, all IGBT’s are
turned off. Normal operation resumes later after the over-current condition is removed
5. After V
has risen above the threshold to enable normal operation, the driver waits to receive an input signal on the LIN input
DD
before enabling the driver for the HIN signal.
Input / Output Logic Table
INPUT
OUTPUT
Low side IGBT
HIN
H
LIN
L
ITRIP
PTRIP
High side IGBT
ON (Note 5)
OFF
U,V,W
FAULT
OFF
OFF
OFF
OFF
ON
L
L
L
L
OFF
ON
VP
L
H
L
NU,NV,NW
L
L
L
OFF
OFF
OFF
OFF
OFF
High Impedance
High Impedance
High Impedance
High Impedance
H
H
X
L
L
OFF
X
H
X
X
H
OFF
X
X
OFF
ON
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11
STK57FU394AG-E
Thermistor characteristics
Parameter
Symbol
Condition
Min
99
Typ
100
Max
101
Unit
kΩ
kΩ
K
R
25
Tc=25℃
Resistance
R
100
5.18
4208
40
5.38
4250
5.60
4293
+125
Tc=100℃
B
B-Constant (25 to 50℃)
Temperature Range
℃
Figure 19. Thermistor Resistance versus Case Temperature
Figure 20. Thermistor Voltage versus Case Temperature
Conditions: RTH=39kΩ, pull-up voltage 5.0V (see Figure 2)
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12
STK57FU394AG-E
Calculation of bootstrap capacitor value
Signal inputs
The bootstrap capacitor value CB is calculated using
the following approach. The following parameters
influence the choice of bootstrap capacitor:
Each signal input has a pull-down resistor. An
additional pull-down resistor of between 2.2kΩ and
3.3kΩ is recommended on each input to improve noise
immunity.
V
: Bootstrap power supply.
BS
15V is recommended.
FLTEN pin
QG: Total gate charge of IGBT at V =15V.
BS
The FLTEN pin is connected to an open-drain FAULT
output requiring a pull-up resistor and an ENABLE
input. If the pull-up voltage is 5V, use a pull-up resistor
with a value of 6.8kꢀ or higher. If the pull-up voltage
is 15V, use a pull-up resistor with a value of 20kꢀ or
higher. The pulled up voltage in normal operation for
the FLTEN pin should be above 2.5V, noting that it is
connected to an internal ENABLE input. The FAULT
output is triggered if there is a VDD undervoltage or an
overcurrent condition on either the PFC or inverter
stages.
53nC
UVLO: Falling threshold for UVLO.
Specified as 12V.
IDMAX: High side drive power dissipation.
Specified as 0.4mA
TONMAX: Maximum ON pulse width of
high side IGBT.
Capacitance calculation formula:
CB = (QG + IDMAX * TONMAX)/(V - UVLO)
BS
Driving the FLTEN terminal pin is used to enable or
shut down the built-in driver. If the voltage on the
FLTEN pin rises above the positive going FLTEN
threshold, the output drivers are enabled. If the voltage
on the FLTEN pin falls below the negative going
FLTEN threshold, the drivers are disabled.
CB is recommended to be approximately 3 times the
value calculated above. The recommended value of CB
is in the range of 1 to 47μF, however, the value needs
to be verified prior to production. When not using the
bootstrap circuit, each high side driver power supply
requires an external independent power supply. If the
capacitors selected are 47 μF or more, a series resistor
of 20Ω should be added in series with the three
capacitors to limit the current. The resistors should be
inserted between VBU and U, VBV and V and VBW
and W.
Undervoltage protection
If VDD goes below the VDD supply undervoltage
lockout falling threshold, the FAULT output is
switched on. The FAULT output stays on until VDD
rises above the VDD supply undervoltage lockout
rising threshold. The hysteresis is approximately
200mV.
80
60
40
20
0
Overcurrent protection
An over-current condition is detected if the voltage on
the ITRIP/PTRIP pin is larger than the reference
voltage. There is a blanking time of typically 350ns to
improve noise immunity. After
a
shutdown
propagation delay of typically 0.6 us, the FAULT
output is switched on.
0.1
1
10
100
1000
The over-current protection threshold should be set to
be equal or lower to 2 times the module rated current
(Io).
Tonmax [ms]
Figure 21. Bootstrap capacitance versus Tonmax
An additional fuse is recommended to protect against
system level or abnormal over-current fault conditions.
Capacitors on High Voltage and VDD supplies
Both the high voltage and VDD supplies require an
electrolytic capacitor and an additional high frequency
capacitor. The recommended value of the high
frequency capacitor is between 100nF and 10 μF.
Minimum input pulse width
When input pulse width is less than 1μs, an output may
not react to the pulse. (Both ON signal and OFF signal)
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13
STK57FU394AG-E
Mounting Instructions
Item
Recommended Condition
Pitch
56.0±0.1mm (Please refer to Package Outline Diagram)
diameter : M3
Screw head types: pan head, truss head, binding head
Screw
Plane washer
The size is D:7mm, d:3.2mm and t:0.5mm JIS B 1256
Washer
Material: Aluminum or Copper
Warpage (the surface that contacts IPM ) : 50 to 100 μm
Screw holes must be countersunk.
Heat sink
No contamination on the heat sink surface that contacts IPM.
Temporary tightening : 20 to 30 % of final tightening on first screw
Temporary tightening : 20 to 30 % of final tightening on second screw
Final tightening : 0.6 to 0.9Nm on first screw
Torque
Grease
Final tightening : 0.6 to 0.9Nm on second screw
Silicone grease.
Thickness : 100 to 200 μm
Uniformly apply silicone grease to whole back.
Thermal foils are only recommended after careful evaluation. Thickness, stiffness and
compressibility parameters have a strong influence on performance.
Figure23. Size of Washer
Figure 22. Mount IPM on a Heat Sink
Figure24. Uniform Application of Grease Recommended
Steps to mount an IPM on a heat sink
1st: Temporarily tighten maintaining a left/right balance.
2nd: Finally tighten maintaining a left/right balance.
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14
STK57FU394AG-E
TEST CIRCUITS
■ I , I
CE R(DB)
ICE
VBS=15V
VBS=15V
VBS=15V
4
PFC
IGBT
U+
V+
W+
U-
V-
W-
A
5
A
B
8
A
B
16
13
16
9
16
5
13
22
9
5
1
VCE,VR
9
21
20
19
12
13
34
U+,V+,W+ : High side phase
U-,V-,W- : Low side phase
VDD=15
35,19,20,21,22
PFC
Diode
U(DB)
V(DB) W(DB)
Figure 25. Test Circuit for ICE
A
B
12
35
8
4
16
35
35
1
■ V
(Test by pulse)
CE(sat)
VBS=15V
VBS=15V
VBS=15V
4
PFC
IGBT
U+
V+
W+
U-
V-
W-
5
A
8
A
B
C
16
13
23
16
9
16
5
13
22
26
9
5
1
9
21
27
20
28
19
29
12
13
34
24
25
V
IC
VCE(sat)
VDD=15V
5V
30
C
B
35,19,20,21,22
Figure 26. Test circuit for VCE(SAT)
■ V (Test by pulse)
F
A
U+
V+
16
9
W+
16
5
U-
13
22
V-
9
W-
5
A
B
16
13
21
20
V
IF
PFC
Diode
Anti-parallel
Diode
U(DB)
V(DB)
W(DB)
B
A
B
12
34
8
4
16
1
34
34
1
19
Figure 27. Test circuit for VF
■ I
D
ID
V
VBS U+
12
VBS V+
VBS W+
A
DD
A
A
8
9
4
5
34
35
VBS, VDD
B
13
B
Figure 28. Test circuit for ID
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15
STK57FU394AG-E
■ V
, V
ITRIP PTRIP
VITRIP(U-)
VPTRIP
A
B
C
D
13
22
26
32
1
19
29
31
A
34
VDD=15
V
Io
30
C
Input Signal
VITRIP/VPFCTRIP
Input signal
D
B
(0 to 5V)
35,19,20,21,22
Figure 29. Test circuit for ITRIP.PTRIP
ITRIP
/PFCTRIP
Io
■ Switching time (The circuit is a representative example of the lower side U phase.)
PFC
U+
V+
W+
U-
V-
W-
IGBT
16
19
1
A
B
C
D
E
16
22
13
22
23
16
21
9
16
20
5
16
22
13
16
26
16
21
9
16
20
5
VBS=15V
VBS=15V
VBS=15V
4
5
A
C
8
9
21
24
20
25
16
27
16
28
16
12
13
34
CS
Vcc
29
D
B
VDD=15
30
Input signal
(0 to 5V)
Input Signal
E
35,19,20,21,22
Io
Figure 30. Test circuit for switching time
Io
90%
10%
tON
tOFF
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16
STK57FU394AG-E
Package Dimensions
unit : mm
SIP35 56x25.8 / SIP2A-3
CASE 127DY
ISSUE O
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