STK672-442BN-E [ONSEMI]
Unipolar 2-phase Stepper Motor Driver;
| 型号： | STK672-442BN-E |
| 厂家： | 
ONSEMI |
| 描述： | Unipolar 2-phase Stepper Motor Driver 局域网 电动机控制 |
| 文件： | 总28页 (文件大小：910K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Ordering number : ENA2249A
STK672-442BN-E
Thick-Film Hybrid IC
2-phase Stepper Motor Driver
http://onsemi.com
Overview
The STK672-442BN-E is a hybrid IC for use as a unipolar, 2-phase stepper motor driver with PWM current control.
Applications
Office photocopiers, printers, etc.
Features
Built-in motor terminal open detection function, overcurrent detection function, overheat detection function
(output current OFF).
FAULT1 signal (active low) is output when any of motor terminal open, overcurrent or overheat is detected.
The FAULT2 signal is used to output the result of activation of protection circuit detection at 3 levels.
Built-in power on reset function.
A micro-step sine wave-driven driver can be activated merely by inputting an external clock.
External pins can be used to select 2, 1-2 (including pseudo-micro), W1-2, 2 W1-2, or 4W1-2 excitation.
The switch timing of the 4-phase distributor can be switched by setting an external pin (MODE3) to detect either the
rise and fall, or rise only, of CLOCK input.
Phase is maintained even when the excitation mode is switched. Rotational direction switching function.
Supports schmitt input for 2.5V high level input.
Incorporating a current detection resistor (0.122Ω: resistor tolerance 2%), motor current can be set using two
external resistors.
The ENABLE pin can be used to cut output current while maintaining the excitation mode.
With a wide current setting range, power consumption can be reduced during standby.
No motor sound is generated during hold mode due to external excitation current control.
PWM operation is separately excited system. As for PWM phase the constant current control
which shifts the phase of Ach Bch.
Supports compatible pins with STK672-432BN/-440BN-E.
Specifications
Absolute Maximum Ratings at Tc = 25C
Parameter
Maximum supply voltage 1
Maximum supply voltage 2
Input voltage
Symbol
Conditions
Ratings
Unit
V
Vcc max
No signal
50
0.3 to 6.0
0.3 to 6.0
20
VDD max
Vin max
IOP max
IOH max
IOF max
PdMF max
PdPK max
Tcmax
No signal
V
Logic input pins
V
Output current 1
10μs 1 pulse (resistance load)
VDD=5V,CLOCK 200Hz
16pin Output current
A
Output current 2
A
3.5
Output current 3
mA
W
W
°C
°C
°C
10
Allowable power dissipation 1
Allowable power dissipation 2
Operating substrate temperature
Junction temperature
Storage temperature
With an arbitrarily large heat sink. Per MOSFET
No heat sink
8.3
2.8
105
Tjmax
150
Tstg
40 to 125
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating
Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability.
ORDERING INFORMATION
See detailed ordering and shipping information on page 28 of this data sheet.
Semiconductor Components Industries, LLC, 2014
January, 2014 Ver. 2.0
10714HK/D0413HK 018-13-0054 No.A2249-1/28
STK672-442BN-E
Allowable Operating Ranges at Tc=25C
Parameter
Operating supply voltage 1
Operating supply voltage 2
Input high voltage
Symbol
Conditions
With signals applied
Ratings
unit
V
V
0 to 46
CC
DD
IH
V
V
V
With signals applied
55%
V
Pins 10, 11, 12, 13, 14, 15, 17, V =55%
DD
2.5 to V
V
DD
Input low voltage
Pins 10, 11, 12, 13, 14, 15, 17, V =55%
0 to 0.8
V
IL
DD
CLOCK frequency
f
Minimum pulse width: at least 10s
Tc=105C, CLOCK200Hz
0 to 50
3.0
kHz
A
CL
OH
Output current
I
Recommended operating
substrate temperature
Tc
No condensation
0 to 105
C
Recommended Vref range
Vref
Tc=105C
0.2 to 1.8
V
Electrical Characteristics at Tc=25C, V =24V, V =5.0V *1
CC DD
Parameter
Symbol
Conditions
min
typ
7.2
0.32
1
max
8.5
unit
mA
A
V
supply current
I
V
=5.0V, ENABLE=Low
DD
CCO
DD
R/L=1/0.62mH in each phase
If=1A (R =23)
Output average current *2
FET diode forward voltage
Output saturation voltage
Input voltage
Ioave
Vdf
0.27
0.37
1.6
V
L
Vsat
R =23
0.25
0.38
V
L
V
Pins 10, 11, 12, 13, 14, 15, 17
Pins 10, 11, 12, 13, 14, 15, 17
Pins 10, 11, 12, 13, 14, 15, 17=5V
Pins 10, 11, 12, 13, 14, 15, 17=GND
Pin 19 =1.0V
2.5
V
V
IH
DD
V
0.3
0.8
V
Control
IL
input pin
5V level input current
I
I
I
50
75
10
1
A
A
A
V
ILH
ILL
IB
GND level input current
Vref input bias current
FAULT1
pin
Output low voltage
V
Pin 16 (I =5mA)
O
0.25
0.5
OLF
5V level leakage current
Pin 16 =5V
I
10
A
ILF
Motor terminal open detection
output voltage
V
1
2
3
0.0
2.4
3.1
0.01
2.5
0.2
OF
OF
OF
FAULT2
pin
Overcurrent detection output
voltage
Pin 8 (when all protection functions have
been activated)
V
V
2.6
3.5
V
Overheat detection output
voltage
3.3
Overheat detection temperature
PWM frequency
TSD
fc
Design guarantee
144
48
C
kHz
A
41
55
1
Drain-source cut-off current
I
V
=100V, Pins 2, 6, 9, 18=GND
DSS
DS
4W1-2
4W1-2
4W1-2
4W1-2
4W1-2
4W1-2
4W1-2
4W1-2
4W1-2
4W1-2
4W1-2
4W1-2
4W1-2
4W1-2
4W1-2
2W1-2
2W1-2
W1-2
1-2
=15/16, 16/16
=14/16
=13/16
=12/16
=11/16
=10/16
=9/16
100
97
95
93
87
83
77
71
64
55
47
40
30
20
11
100
2W1-2
2W1-2
2W1-2
2W1-2
2W1-2
2W1-2
W1-2
W1-2
W1-2
1-2
=8/16
Vref
*3
%
=7/16
=6/16
=5/16
=4/16
=3/16
=2/16
=1/16
2
Notes
*1: A fixed-voltage power supply must be used.
*2: The value for Ioave assumes that the lead frame of the product is soldered to the mounting circuit board.
*3: The values given for Vref are design targets, no measurement is performed.
No.A2249-2/28
STK672-442BN-E
Derating Curve of Motor Current, I
vs. STK672-442BN-E Operating Substrate Temperature, Tc
OH,
4
3.5
3
2.5
2
200Hz 2ex
Hold
1.5
1
0.5
0
0
10 20 30 40 50 60 70 80 90 100 110
Operation substrate temperature Tc C
Notes
The current range given above represents conditions when output voltage is not in the avalanche state.
If the output voltage is in the avalanche state, see the allowable avalanche energy for STK672-4** series hybrid ICs
given in a separate document.
The operating substrate temperature, Tc, given above is measured while the motor is operating.
Because Tc varies depending on the ambient temperature, Ta, the value of I , and the continuous or intermittent
OH
operation of I , always verify this value using an actual set.
OH
The Tc temperature should be checked in the center of the metal surface of the product package.
No.A2249-3/28
STK672-442BN-E
Block Diagram
AB
5
B
3
VDD
9
MOI
7
A
BB
1
FAULT2 Vref
4
19
8
1÷4.9
MODE1
MODE2 11
10
Excitation
mode
selection
Current
divider ratio
switching
VSS
Phase
advance
counter
13
12
CWB
Pseudo
sine wave
generator
F1
F2
F3
F4
Rising edge /
falling edge
detection
CLOCK
MODE3
RESETB
17
14
Phase
excitation
signal
Power on reset
generator
Over heating
detection
ENABLE
15
Over current
detection
Latch
Open
detection
Reference
PWM
Oscillator
clock
control
generator
16
18
FAULT1
S.G
P.G2
P.G1
2
6
SUB
No.A2249-4/28
STK672-442BN-E
Measurement Circuit
(The terminal which is not appointed is open. The measurement circuit of STK672-440BN-E is the
same as STK672-442BN-E.)
Vsat
IIH,IIL,IIB,ILF
VDD
9
VDD
9
24V
MODE1
10
11
17
12
13
14
15
16
IIH
15
MODE2
MODE3
A
ILF
RL
23Ω
Start
17
12
10
11
19
13
14
4
5
CLOCK
CWB
STK672-
442BN-E
STK672-
442BN-E
3
1
RESETB
2V
ENABLE
FAULT1
V
IIL
A
Vsat
VREF
A
19
18
2
6
GND
18
IIB
1V
GND
Vdf
Icco,Ioave,fc,VOLF
VDD
24V
9
Icco
A
9
Start
4
5
3
23Ω
0.62mH
23Ω
12
SW4
STK672-
442BN-E
10
11
15
17
14
SW1
SW2
a
5
3
4
1
1Ω
STK672-
442BN-E
ENABLE
1
b
VDD
7.5kΩ
a
V
1Ω
6
2
Ioave
V
b
910Ω
19
IF=1A
Vdf
24V
SW3
16
1kΩ
100μF
GND
fc
18
2
6
V
VOLF
GND
GND
Ioave measurement : Set switch SW2 in the setting SW1 to ‘b’.
fc measurement : Set switch SW3 in the setting SW1 to ‘a’.
Icco measurement : Set ENABLE low.
VOLF measurement : Set SW4‘on’in the Ioave measurement condition.
No.A2249-5/28
STK672-442BN-E
Sample Application Circuit
(2W1-2 Phase Excitation Drive /micro stepping operation)
VDD
5V
9
10
11
17
2-phase stepper motor
A
4
5
12
15
13
7
AB
CLOCK
ENABLE
CWB
Vcc=24V
C01
STK672
-442BN-E
B
3
1
BB
MOI
100μ
RESETB
Vref
14
+
P.G2
R01
R02
2
6
19
P.GND
8
16 18
P.G1
C02
10μ
+
S.GND
FAULT1
FAULT2
Precautions
[GND wiring]
To reduce noise on the 5V/24V system, be sure to place the GND of C01 in the circuit given above as close as possible
to Pin 2 and Pin 6 of the hybrid IC.
In addition, in order to set the current accurately, the GND side of RO2 of Vref must be connected to the shared ground
terminal used by the Pin 18 (S.G) GND, P.G1 and P.G2.
[Input pins]
If V
is being applied, use care that each input pin does not apply a negative voltage less than -0.3V to S. GND,
DD
Pin 18. Measures must also be taken so that a voltage equal to or greater than V
is not input.
DD
High voltage input other than V , MOI, FAULT1, and FAULT2 is 2.5V.
DD
Pull-up resistors are not connected to input pins. Pull-down resistors are attached. When controlling the input to the
hybrid IC with the open collector type, be sure to connect a pull-up resistor (1 to 20k).
Be sure to use a device (0.8V or less, low level, when I =5mA) for the open collector driver at this time that has an
OL
output voltage specification such that voltage is pulled to less than 0.8V at low level.
When using the power on reset function built into the hybrid IC, be sure to directly connect Pin 14 to V
.
DD
We recommend attaching a 1,000pF capacitor to each input to prevent malfunction during high-impedance input. Be
sure to connect the capacitor near the hybrid IC, between Pin 18 (S, G).
When input is fixed low, directly connect to Pin 18. When input is fixed high, directly connect to V
.
DD
[Current setting Vref]
If the motor current is temporarily reduced, the circuit given below is recommended.
The variable voltage range of Vref input is 0.2 to 1.8V.
No.A2249-6/28
STK672-442BN-E
5V
5V
R01
Vref
R01
Vref
R02
R3
R3
R02
[Setting the motor current]
The motor current, I , is set using the Pin 19 voltage, Vref, of the hybrid IC.
OH
Equations related to I
and Vref are given below.
OH
Vref (RO2 (RO2+RO1))V (5V) ··········································· (1)
DD
(Vref 4.9) Rs ······························································· (2)
I
OH
The value of 4.9 in Equation (2) above represents the Vref voltage as divided by a circuit inside the control IC.
Rs: 0.122 (Current detection resistor inside the hybrid IC)
IOH
0
[Smoke Emission Precuations]
If Pin 18 (S.G terminal) is attached to the PCB without using solder, overcurrent may flow into the MOSFET at V ON
CC
(24V ON), causing the STK672-442B-E to emit smoke because 5V circuits cannot be controlled.
Function Table
M2
0
0
0
1
0
1
1
CLOCK Edge Timing for
Phase Switching
M1
1
M3
2-phase excitation
selection
1-2-phase excitation
W1-2 phase
excitation
2W1-2 phase
excitation
1
0
CLOCK rising edge
CLOCK both edges
(I =100%)
OH
1-2 phase excitation
W1-2 phase
excitation
2W1-2 phase
excitation
4W1-2 phase
excitation
(I =100%, 71%)
OH
I
=100% results in the Vref voltage setting, I .
OH
OH
During 1-2 phase excitation, the hybrid IC operates at a current setting of I =100% when the CLOCK signal rises.
OH
Conversely, pseudo micro current control is performed to control current at I =100% or 71% at both edges of the
OH
CLOCK signal.
WB pin
Forward/CW
0
1
Reverse/CCW
ENABLE RESETB pin
ENABLE
RESETB
Motor current cut: Low
Active Low
No.A2249-7/28
STK672-442BN-E
Timing Charts
2-phase excitation timing charts (M3=1)
1-2-phase excitation timing charts (M3=1)
A phase
A phase
B phase
B phase
W1-2-phase excitation timing charts (M3=1)
2W1-2-phase excitation timing charts (M3=1)
A phase
A phase
B phase
B phase
No.A2249-8/28
STK672-442BN-E
1-2-phase excitation timing charts (M3=0)
W1-2-phase excitation timing charts (M3=0)
A phase
A phase
B phase
B phase
2W1-2-phase excitation timing charts (M3=0)
4W1-2-phase excitation timing charts (M3=0)
A phase
A phase
B phase
B phase
No.A2249-9/28
STK672-442BN-E
Package Dimensions
unit : mm
SIP19 24.2x14.4
CASE 127BA
ISSUE O
24.2
(18.4)
+0.15
−0.05
4.5
(2 - R1.47)
19
1
+0 . 2
0.4−0.05
1
2
0.5 0.05
0.35
4
18 X 1 = 18
4.45
No.A2249-10/28
STK672-442BN-E
STK672-442BN-E
Technical data
1. Input Pins and Functional Overview
2. STK672-442BN-E output pins open detection, over current detection,
thermal shutdown detection.
3. STK672-442BN-E Allowable Avalanche Energy
4. STK672-442BN-E Internal Loss Calculation
5. Thermal Design
6. Package Power Loss PdPK Derating Curve for the Ambient Temperature Ta
7. Other usage notes
No.A2249-11/28
STK672-442BN-E
1.I/O Pins and Functions of the Control Block
[Pin description]
HIC pin
Pin Name
MOI
Function
Output pin for the excitation monitor
7
19
10
11
17
12
13
14
15
16
8
Vref
Current value setting
MODE1
MODE2
MODE3
CLOCK
CWB
Excitation mode selection
External CLOCK (motor rotation instruction)
Sets the direction of rotation of the motor axis
System reset
RESETB
ENABLE
FAULT1
FAULT2
Motor current OFF
Motor terminal open/Overcurrent/over-heat detection output
Description of each pin
1-1.[CLOCK (Phase switching clock)]
Input frequency: DC-20kHz (when using both edges) or DC-50kHz (when using one edge)
Minimum pulse width: 20s (when using both edges) or 10s (when using one edge)
Pulse width duty: 40% to 50% (when using both edges)
Both edge, single edge operation
M3:1 The excitation phase moves one step at a time at the rising edge of the CLOCK pulse.
M3:0 The excitation phase moves alternately one step at a time at the rising and falling edges of the CLOCK pulse.
1-2.[CWB (Motor direction setting)]
When CWB=0: The motor rotates in the clockwise direction.
When CWB=1: The motor rotates in the counterclockwise direction.
Do not allow CWB input to vary during the 7s interval before and after the rising and falling edges of CLOCK input.
1-3. [ENABLE (Forcible OFF control of excitation drive output A, AB, B, and BB, and selecting operation/hold status
inside the HIC)]
ENABLE=1: Normal operation
When ENABLE=0: Motor current goes OFF, and excitation drive output is forcibly turned OFF.
The system clock inside the HIC stops at this time, with no effect on the HIC even if input pins other than RESET input
vary. In addition, since current does not flow to the motor, the motor shaft becomes free.
If the CLOCK signal used for motor rotation suddenly stops, the motor shaft may advance beyond the control position
due to inertia. A SLOW DOWN setting where the CLOCK cycle gradually decreases is required in order to stop at the
control position.
1-4. [MODE1, MODE2, and MODE3 (Selecting the excitation mode, and selecting one edge or both edges of the
CLOCK)]
Excitation select mode terminal (See the sample application circuit for excitation mode selection), selecting the
CLOCK input edge(s).
Mode setting active timing
Do not change the mode within 7s of the input rising or falling edge of the CLOCK signal.
1-5.[RESETB (System-wide reset)]
The reset signal is formed by the power-on reset function built into the HIC and the RESETB terminal.
When activating the internal circuits of the HIC using the power-on reset signal within the HIC, be sure to connect Pin
14 of the HIC to V
.
DD
1-6.[Vref (Voltage setting to be used for the current setting reference)]
Pin type: Analog input configuration
Input voltage is in the voltage range of 0.2V to 1.8V.
No.A2249-12/28
STK672-442BN-E
1-7. [Input timing]
The control IC of the driver is equipped with a power on reset function capable of initializing internal IC operations
when power is supplied. A 4V typ setting is used for power on reset. Because the specification for the MOSFET gate
voltage is 5V5%, conduction of current to output at the time of power on reset adds electromotive stress to the
MOSFET due to lack of gate voltage. To prevent electromotive stress, be sure to set ENABLE=Low while V
,
DD
which is outside the operating supply voltage, is less than 4.75V.
In addition, if the RESETB terminal is used to initialize output timing, be sure to allow at least 10s until CLOCK
input.
4Vtyp
3.8Vtyp
Control IC power (V ) rising edge
DD
Control IC power on reset
RESETB signal input
ENABLE signal input
No time specification
CLOCK signal input
At least 10s
At least 10s
ENABLE, CLOCK, and RESETB Signals Input Timing
1-8. [Configuration of control block I/O pins]
<Configuration of the MODE1, MODE2, MODE3, CLOCK,
CWB, ENABLE, and RESETB input pins>
<Configuration of the FAULT2 pin>
VDD
50k
VDD
Output pin
Pin 8
10kΩ
Motor terminal open
50k
Overcurrent
50k
Input pin
100kΩ
VSS
Overheating
(The buffer has an open drain configuration.)
The input pins of this driver all use Schmitt input. Typical specifications at Tc=25C are given below. Hysteresis voltage
is 0.3V (VIHa-VILa).
When rising
When falling
1.8Vtyp
1.5Vtyp
Input voltage
VIHa
VILa
Input voltage specifications are as follows.
V
V
=2.5Vmin
IH
=0.8Vmax
IL
No.A2249-13/28
STK672-442BN-E
<Configuration of the Vref input pin>
<Configuration of the FAULT1 output pin>
VDD
Output pin
Pin16
Vref/4.9
Motor terminal open
Overcurrent
Amplifier
Overheating
Inputpin
Pin19
VSS
VSS
<FAULT1, FAULT2 output>
FAULT1 Output
FAULT1 is an open drain output. It outputs low level when any of motor terminal open, overcurrent, or overheat is
detected.
FAULT2 output
Output is resistance divided (3 levels) and the type of abnormality detected is converted to the corresponding output
voltage.
Motor terminal open: 10mV (typ)
Overcurrent: 2.5V (typ)
Overheat: 3.3V (typ)
Abnormality detection can be released by a RESETB operation or turning V
voltage on/off.
DD
1-9. [MOI output]
The output frequency of this excitation monitor pin varies depending on the excitation mode. For output operations, see
the timing chart.
No.A2249-14/28
STK672-442BN-E
2. Overcurrent detection, overheat detection, and motor terminal open detection functions
Each detection function operates using a latch system and turns output off. Because a RESET signal is required to restore
output operations, once the power supply, V , is turned off, you must either again apply power on reset with V ON
DD
DD
or apply a RESETB=HighLowHigh signal.
2-1. [Motor terminal open detection]
This hybrid IC is equipped with a function for detecting open output terminals to prevent thermal destruction of the
MOSFET due to repeated avalanche operation that occurs when an output terminal connected to the motor is open. The
open condition is determined by checking the presence or absence of the flyback current that flows in the motor
inductance during the off period of the PWM cycle.
Detection is performed by using the fact that the flyback current does not flow when a motor terminal is open.
Terminal open
Current detection
resistor voltage
Used to set the motor current
0V (GND potential)
Used for open detection
(Negative current does not flow
when the terminal is open.)
MOSFET gate signal
PWM period
When the current level drops, the difference with the GND potential decreases, making detection difficult.
The motor current that can be detected by motor terminal open detection is 1.1A or more with the STK672-432BN-E
and 1.4A or more with the STK672-440BN-E/442BN-E.
<Notes on the ENABLE high edge>
When ENABLE changes from low to high and the STK672-4xxBN-E performs constant-current PWM operation that
flows a negative current during the 30s period after the high edge, open detection may activate and stop the driver.
The motor current setting voltage Vref must be set so that PWM operation is not performed within a period of 30s after
the high edge.
If the motor current setup voltage is set for the rated motor current, PWM operation is not performed during this 30s
period after the high edge, so this is not a problem.
In addition, there is no problem with operation that lowers the current setting Vref after the motor rated current is
reached as shown in the diagram on the following page.
Whether constant-current PWM operation is performed during the 30s period after the high edge can be judged by
substituting the motor L and R values into the formula on the following page.
Vref= (R02÷ (R01+R02)) × VDD
I
I
1= (Vref÷4.9) ÷Rs
I
I
1: Motor current value to be set
2: Current value 30s after the ENABLE high edge
OH
OH
OH
OH
2= (V ÷R) × (1-e-tR/L
)
CC
Judgment standard: I 1I
OH OH
2
R01, R02, VDD : See the Sample Application Circuit documents.
Rs: Current detection resistance value ()
V
: Motor supply voltage (V)
CC
R: Motor winding resistance ()
L: Motor winding inductance (H)
There is no problem if the I 2 obtained by substituting t = 30s and the motor L and R values is smaller than the
OH
current setting value I 1.
OH
No.A2249-15/28
STK672-442BN-E
ENABLE
Vref
Output current
Constant-current PWM operation must not be performed for 30s or less.
<Connection of capacitors between output pins and GND prohibited>
Capacitors must not be connected between the phase A (pin 4), phase AB (pin 5), phase B (pin 3) and phase BB (pin 1)
outputs and GND. What happens if capacitors are connected is that open-circuit detection may be triggered by the
discharge current of the capacitors when the internal MOSFET is set ON. This current is not an inductance current
generated by the motor winding but a capacitor current so a negative current will not flow to the other phase in each pair
of phases, possibly causing the driver to shut down.
<Excessive external noise>
If, when the motor current rises prior to the PWM operation, a spike-shaped current exceeding the Vref-setting current is
generated by excessive external noise, for instance, before the current level (1.1A for the STK672-432BN-E, 1.4A for
the STK672-440BN-E and 442BN-E motor drivers) at which motor pin open-circuiting can be detected is reached, the
internal MOSFET is set OFF. Since the MOSFET has been set OFF before the actual motor current reaches 1.1A (or
1.4A), the level of the negative current subsequently flowing to the other phase in each pair of phases is low, and it may
be judged that no negative current is flowing, possibly causing open-circuit detection to be triggered.
During normal constant-current PWM operation, the duration of 1.25s, which is equivalent to 6% of the initial
operation in the PWM period, corresponds to the section where the current is not detected, and this ensures that no
current is detected for the linking part of the current that is generated in this section. The no-current detection section is
not synchronized at the current rise prior to the PWM operation so when a spike-shaped current exceeding the
Vref-setting current is generated, the MOSFET is set OFF at the stage where the level of the actual motor current is low.
As a result, the level of the negative current subsequently flowing to the other phase in each pair of phases is low, and it
may be judged that no negative current is flowing, possibly causing open-circuit detection to be triggered.
Spike-shaped current
Vref setting
current (I
)
OH
Motor
current
Current level at
which open-circuiting
is detected
No-current detection time (1.25s typ)
PWM period
No.A2249-16/28
STK672-442BN-E
2-2.[Overcurrent detection]
This hybrid IC is equipped with a function for detecting overcurrent that arises when the motor burns out or when there is
a short between the motor terminals.
Overcurrent detection occurs at 3.4A typ with the STK672-432BN-E, and 5.0A typ with the
STK672-440BN-E/442BN-E.
Current when motor terminals are shorted
PWM period
Overcurrent detection
I
max
OH
Set motor
current, I
MOSFET all OFF
OH
No detection interval
(1.25s typ)
1.25s typ
Operation when motor pins are shorted
Normal operation
Overcurrent detection begins after an interval of no detection (a dead time of 1.25s typ) during the
initial ringing part during PWM operations. The no detection interval is a period of time where
overcurrent is not detected even if the current exceeds I
.
OH
2-3. [Overheat detection]
Rather than directly detecting the temperature of the semiconductor device, overheat detection detects the temperature of
the aluminum substrate (144C typ).
Within the allowed operating range recommended in the specification manual, if a heat sink attached for the purpose of
reducing the operating substrate temperature, Tc, comes loose, the semiconductor can operate without breaking.
However, we cannot guarantee operations without breaking in the case of operations other than those recommended,
such as operations at a current exceeding I
max that occurs before overcurrent detection is activated.
OH
No.A2249-17/28
STK672-442BN-E
3. Allowable Avalanche Energy Value
(1) Allowable Range in Avalanche Mode
When driving a 2-phase stepping motor with constant current chopping using an STK672-4** Series hybrid IC, the
waveforms shown in Figure 1 below result for the output current, I , and voltage, V
.
DS
D
VDSS: Voltage during avalanche operations
I
: Motor current peak value
OH
IAVL: Current during avalanche operations
tAVL: Time of avalanche operations
Figure 1 Output Current, I , and Voltage, V , Waveforms 1 of the STK672-4** Series when Driving a
D
DS
2-Phase Stepper Motor with Constant Current Chopping
When operations of the MOSFET built into STK672-4** Series ICs is turned off for constant current chopping, the I
D
signal falls like the waveform shown in the figure above. At this time, the output voltage, V , suddenly rises due to
DS
electromagnetic induction generated by the motor coil.
In the case of voltage that rises suddenly, voltage is restricted by the MOSFET V
DSS
. Voltage restriction by V
DSS
results in a MOSFET avalanche. During avalanche operations, I flows and the instantaneous energy at this time, EAVL1,
D
is represented by Equation (3-1).
EAVL1=V
IAVL0.5tAVL ------------------------------------------- (3-1)
: V units, IAVL: A units, tAVL: sec units
DSS
V
DSS
The coefficient 0.5 in Equation (3-1) is a constant required to convert the IAVL triangle wave to a square wave.
During STK672-4** Series operations, the waveforms in the figure above repeat due to the constant current chopping
operation. The allowable avalanche energy, EAVL, is therefore represented by Equation (3-2) used to find the average
power loss, PAVL, during avalanche mode multiplied by the chopping frequency in Equation (3-1).
PAVL=V
IAVL0.5tAVLfc ------------------------------------------- (3-2)
DSS
fc: Hz units (fc is set to the PWM frequency of 50kHz.)
For V
DSS
, IAVL, and tAVL, be sure to actually operate the STK672-4** Series and substitute values when operations
are observed using an oscilloscope.
Ex. If V =110V, IAVL=1A, tAVL=0.2s, the result is:
DSS
PAVL=11010.50.210-650103=0.55W
=110V is a value actually measured using an oscilloscope.
V
DSS
The allowable loss range for the allowable avalanche energy value, PAVL, is shown in the graph in Figure 3.
When examining the avalanche energy, be sure to actually drive a motor and observe the I , V , and tAVL waveforms
D
DSS
during operation, and then check that the result of calculating Equation (3-2) falls within the allowable range for
avalanche operations.
No.A2249-18/28
STK672-442BN-E
(2) I
V
Operating Waveforms in Non-avalanche Mode
D and DSS
Although the waveforms during avalanche mode are given in Figure 1, sometimes an avalanche does not result during
actual operations.
Factors causing avalanche are listed below.
Poor coupling of the motor’s phase coils (electromagnetic coupling of A phase and AB phase, B phase and BB phase).
Increase in the lead inductance of the harness caused by the circuit pattern of the P.C. board and motor.
Increases in V
, tAVL, and IAVL in Figure 1 due to an increase in the supply voltage from 24V to 36V.
DSS
If the factors above are negligible, the waveforms shown in Figure 1 become waveforms without avalanche as shown
in Figure 2.
Under operations shown in Figure 2, avalanche does not occur and there is no need to consider the allowable loss
range of PAVL shown in Figure 3.
I
: Motor current peak value
OH
Figure 2 Output Current, I , and Voltage, V , Waveforms 2 of the STK672-4** Series when Driving
DS
D
a 2-Phase Stepper Motor with Constant Current Chopping
Figure 3 Allowable Loss Range, PAVL-I
OH
During STK672-442BN-E Avalanche Operations
5
4.5
4
3.5
3
Tc=105°C
Tc=80°C
2.5
2
1.5
1
0.5
0
0
0.5
1
1.5
2
2.5
3
3.5
Moter current, IOH - A
Note:
The operating conditions given above represent a loss when driving a 2-phase stepper motor with constant current
chopping.
Because it is possible to apply 3W or more at I =0A, be sure to avoid using the MOSFET body diode that is used to
OH
drive the motor as a zener diode.
No.A2249-19/28
STK672-442BN-E
4. Calculating STK672-442BN-E HIC Internal Power Loss
The average internal power loss in each excitation mode of the STK672-442B-E can be calculated from the following
formulas. *1
4-1. [Each excitation mode]
2-phase excitation mode
2PdAVex= 2Vsat0.5CLOCKI t2+0.5CLOCKI (Vsatt1+Vdft3) --------------------------- (4-1)
OH OH
1-2 Phase excitation mode
1-2PdAVex= 2Vsat0.25CLOCKI t2+0.25CLOCKI (Vsatt1+Vdft3) ---------------------- (4-2)
OH OH
W1-2 Phase excitation mode
W1-2PdAVex=0.64[2Vsat0.125CLOCKI t2+0.125CLOCKI (Vsatt1+Vdft3)] ---------- (4-3)
OH OH
2W1-2 Phase excitation mode
2W1-2PdAVex=0.64[2Vsat0.0625CLOCKI t2+0.0625CLOCKI (Vsatt1+Vdft3)] ------ (4-4)
OH OH
4W1-2 Phase excitation mode
4W1-2PdAVex=0.64[2Vsat0.0625CLOCKI t2+0.0625CLOCKI (Vsatt1+Vdft3)] ------ (4-5)
OH OH
Motor hold mode
HoldPdAVex= 2VsatI ---------------------------------------------------------------------------------------------- (4-6)
OH
Note: 2-phase 100% conductance is assumed in Equation (4-6).
Vsat: Combined voltage of Ron voltage drop + current detection resistance
Vdf: Combined voltage of the FET body diode + current detection resistance
CLOCK: Input CLOCK (HIC: input frequency at Pin 12)
t1, t2, and t3 represent the waveforms shown in the figure below.
t1: Time required for the winding current to reach the set current (I
t2: Time in the constant current control (PWM) region
)
OH
t3: Time from end of phase input signal until inverse current regeneration is complete
IOH
0 A
t1
t2
t3
Motor COM Current Waveform Model
t1= (-L/(R+0.25)) ln (1-(((R+0.25)/V ) I )) ----------------------------------------------------------- (4-7)
CC OH
t3= (-L/R) ln ((V +0.25)/(I R+V +0.25)) ---------------------------------------------------------- (4-8)
CC OH CC
: Motor supply voltage (V)
CC
V
L: Motor inductance (H)
R: Motor winding resistance ()
I
: Motor set output current crest value (A)
OH
No.A2249-20/28
STK672-442BN-E
Fixed current control time, t2, for each excitation mode
(1) 2-phase excitation
(2) 1-2 phase excitation
(3) W1-2 phase excitation
t2 = (2CLOCK) - (t1 + t3)······················· (4-9)
t2 = (3CLOCK) - t1 ······························ (4-10)
t2 = (7CLOCK) - t1 ······························ (4-11)
(4) 2W1-2 phase excitation (and 4W1-2 phase excitation) t2 = (15CLOCK) - t1····························· (4-12)
For the values of Vsat and Vdf, be sure to substitute from Vsat vs I
(See pages to follow)
and Vdf vs I
OH
at the setting current value I .
OH
OH
Then, determine if a heat sink is necessary by comparing with the Tc vs Pd graph (see next page) based on the calculated
average output loss, HIC.
For heat sink design, be sure to see ‘5. Thermal Design’.
The HIC average power, PdAVex described above, represents loss when not in avalanche mode. To add the loss in
avalanche mode, be sure to add PAVL (4-13, 14) using the formula (3-2) for average power loss , PAVL, for STK672-4**
avalanche mode, described below to PdAVex described above.
When using this IC without a fin, always check for temperature increases in the set, because the HIC substrate temperature,
Tc, varies due to effects of convection around the HIC.
4-2. [Calculating the average power loss, PAVL, during avalanche mode]
The allowable avalanche energy, EAVL, during fixed current chopping operation is represented by Equation (3-2) used
to find the average power loss, PAVL, during avalanche mode that is calculated by multiplying Equation (3-1) by the
chopping frequency.
PAVL=V
IAVL0.5tAVLfc ············································································· (3-2)
fc: Hz units (fc is set to the PWM frequency of 50kHz.)
DSS
Be sure to actually operate an STK672-4** series and substitute values found when observing operations on an
oscilloscope for V , IAVL, and tAVL.
DSS
The sum of PAVL values for each excitation mode is multiplied by the constants given below and added to the average
internal HIC loss equation, except in the case of 2-phase excitation.
1-2 excitation mode and higher: PAVL(1)=0.7PAVL ····················································(4-13)
During 2-phase excitation and motor hold: PAVL(1)=1PAVL(4-14)
No.A2249-21/28
STK672-442BN-E
Output current, IOH - A
No.A2249-22/28
STK672-442BN-E
5. Thermal design
[Operating range in which a heat sink is not used]
Use of a heat sink to lower the operating substrate temperature of the HIC (Hybrid IC) is effective in increasing the
quality of the HIC.
The size of heat sink for the HIC varies depending on the magnitude of the average power loss, PdAV, within the HIC.
The value of PdAV increases as the output current increases. To calculate PdAV, refer to “Calculating Internal HIC
Loss” in the specification document.
Calculate the internal HIC loss, PdAV, assuming repeat operation such as shown in Figure 1 below, since
conduction during motor rotation and off time both exist during actual motor operations,
IO1
Motor phase current
(sink side)
IO2
0 A
-IO1
T1
T3
T2
T0
Figure 1 Motor Current Timing
T1: Motor rotation operation time
T2: Motor hold operation time
T3: Motor current off time
T2 may be reduced, depending on the application.
T0: Single repeated motor operating cycle
I 1 and I 2: Motor current peak values
O
O
Due to the structure of motor windings, the phase current is a positive and negative current with a pulse form.
Note that figure 1 presents the concepts here, and that the on/off duty of the actual signals will differ.
The hybrid IC internal average power dissipation PdAV can be calculated from the following formula.
PdAV= (T1P1+T2P2+T30) TO ---------------------------- (I)
(Here, P1 is the PdAV for I 1 and P2 is the PdAV for I 2)
O
O
If the value calculated using Equation (I) is 1.5W or less, and the ambient temperature, Ta, is 60C or less, there is no
need to attach a heat sink. Refer to Figure 2 for operating substrate temperature data when no heat sink is used.
[Operating range in which a heat sink is used]
Although a heat sink is attached to lower Tc if PdAV increases, the resulting size can be found using the value of
c-a in Equation (II) below and the graph depicted in Figure 3.
c-a= (Tc max-Ta) PdAV ---------------------------- (II)
Tc max: Maximum operating substrate temperature =105C
Ta: HIC ambient temperature
Although a heat sink can be designed based on equations (I) and (II) above, be sure to mount the HIC in a set and
confirm that the substrate temperature, Tc, is 105C or less.
The average HIC power loss, PdAV, described above represents the power loss when there is no avalanche operation.
To add the loss during avalanche operations, be sure to add Equation (3-2), “Allowable STK672-4** Avalanche
Energy Value”, to PdAV.
No.A2249-23/28
STK672-442BN-E
Figure 2
Figure 3
No.A2249-24/28
STK672-442BN-E
6. Mitigated Curve of Package Power Loss, PdPK, vs. Ambient Temperature, Ta
Package power loss, PdPK, refers to the average internal power loss, PdAV, allowable without a heat sink.
The figure below represents the allowable power loss, PdPK, vs. fluctuations in the ambient temperature, Ta.
Power loss of up to 2.8W is allowable at Ta=25C, and of up to 1.5W at Ta=60C.
* The package thermal resistance θc-a is 28.6°C/W.
No.A2249-25/28
STK672-442BN-E
7. Other usage notes
In addition to the “Notes” indicated in the Sample Application Circuit, care should also be given to the following
contents during use.
(1) Allowable operating range
Operation of this product assumes use within the allowable operating range. If a supply voltage or an input voltage
outside the allowable operating range is applied, an overvoltage may damage the internal control IC or the
MOSFET.
If a voltage application mode that exceeds the allowable operating range is anticipated, connect a fuse or take other
measures to cut off power supply to the product.
(2) Input pins
If the input pins are connected directly to the board connectors, electrostatic discharge or other overvoltage outside
the specified range may be applied from the connectors and may damage the product. Current generated by this
overvoltage can be suppressed to effectively prevent damage by inserting 100 to 1k resistors in lines connected
to the input pins.
Take measures such as inserting resistors in lines connected to the input pins.
(3) Power connectors
If the motor power supply V
is applied by mistake without connecting the GND part of the power connector
when the product is operated, such as for test purposes, an overcurrent flows through the V decoupling capacitor,
CC
CC
of the internal control IC and GND, and may damage the power supply
C1, to the parasitic diode between the V
pin block of the internal control IC.
DD
To prevent damage in this case, connect a 10 resistor to the V
pin, or insert a diode between the V
CC
DD
decoupling capacitor C1 GND and the V
pin.
DD
Overcurrent protection measure: insert a resistor
VDD=5V
A
AB
BB
B
3
1
4
5
5V
Reg.
.
9
VDD
FAO
FABO
MODE1
FBO
Vcc
CLOCK
FBBO
CWB
24V
Reg
.
RESETB
R2
R1
C1
GND
2
ENABLE
MODE2
MODE3
A1
B1
6
Vref
FAULT
Vref
VSS
S.G
18
open
Overcurrent protection measure: insert a diode
Overcurrent path
(4) Input Signal Lines
1) Do not use an IC socket to mount the driver, and instead solder the driver directly to the board to minimize
fluctuations in the GND potential due to the influence of the resistance component and inductance
component of the GND pattern wiring.
2) To reduce noise caused by electromagnetic induction to small signal lines, do not design small signal lines
(sensor signal lines, and 5V or 3.3V power supply signal lines) that run parallel in close proximity to the
motor output line A (Pin 4), AB (Pin 5), B (Pin 3), or BB (Pin 1) phases.
No.A2249-26/28
STK672-442BN-E
(5) When mounting multiple drivers on a single board
When mounting multiple drivers on a single board, the GND design should mount a V
CC
decoupling capacitor, C1, for each driver to stabilize the GND potential of the other drivers. The
key wiring points are as follows.
24v
5V
9
9
9
Motor
3
Motor
1
Motor
2
Input
Signals
Input
Signals
Input
Signals
IC1
IC2
IC3
2
6
2
6
2
6
18
18
18
19
19
19
GND
GND
Thick and short
Short
Thick
(6) V
operating limit
CC
When the output (for example F1) of a 2-phase stepper motor driver is turned OFF, the AB phase back electromotive
force eab produced by current flowing to the paired F2 parasitic diode is induced in the F1 side, causing the output
voltage VFB to become twice or more the V
voltage. This is expressed by the following formula.
CC
VFB = V
+ eab
CC
CC
= V
+ V
+ I
x RM + Vdf (1.6V)
CC OH
V
: Motor supply voltage, I : Motor current set by Vref
CC OH
Vdf: Voltage drop due to F2 parasitic diode and current detection resistor R1, RM: Motor winding resistance value
Using the above formula, make sure that VFB is always less than the MOSFET withstand voltage of 100V. This is
because there is a possibility that operating limit of V
falls below the allowable operating range of 46V, due to the
CC
RM and I
OH
specifications.
V
CC
V
CC
AB phase
eab
A phase
AB phase
A phase
eab is generated by the
mutual induction M.
Current path
Current path
VFB
eab
CC
M
M
V
F2
F2
OFF
OFF
F1
OFF
F1
ON
R1
GND
R1
GND
The oscillating voltage in excess of VFB is caused by LCRM (inductance, capacitor, resistor, mutual inductance)
oscillation that includes micro capacitors C, not present in the circuit. Since M is affected by the motor characteristics,
there is some difference in oscillating voltage according to the motor specifications. In addition, constant voltage drive
without constant current drive enables motor rotation at V
CC
0V.
No.A2249-27/28
STK672-442BN-E
OERING INFORMATION
Device
Package
Shipping (Qty / Packing)
20 / Tube
SIP-19
(Pb-Free)
STK672-442BN-E
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PS No.2249-28/28
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