TCC-303_技术文档

Three-Output PTIC Control

IC

TCC-303

Introduction

TCC−303 is a three−output high−voltage digital to analog control IC

specifically designed to control and bias ON Semiconductor’s Passive

Tunable Integrated Circuits (PTICs).

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These tunable capacitor control circuits are intended for use in

mobile phones and dedicated RF tuning applications. The

implementation of ON Semiconductor’s tunable circuits in mobile

phones enables significant improvement in terms of antenna radiated

performance.

WLCSP12

CASE 567MW

The tunable capacitors are controlled through a bias voltage ranging

from 1 V to 24 V. The TCC−303 high−voltage PTIC control IC has

been specifically designed to cover this need, providing three

independent high−voltage outputs that control up to three different

tunable PTICs in parallel. The device is fully controlled through a

MIPI RFFE digital interface.

MARKING DIAGRAM

T33x

ALYWG

G

Key Features

T33x= Specific Device Code

• Controls ON Semiconductor’s PTIC Tunable Capacitors

• Compliant with Timing Needs of Cellular and Other Wireless System

Requirements

• 28 V Integrated Boost Converter with Three 24 V Programmable

DAC Outputs

x

A

L

= a or b

= Assembly Location

= Wafer Lot

Y

W

G

= Year

= Work Week

= Pb−Free Package

• Low Power Consumption

• MIPI RFFE Interfaces (1.8 V)

(Note: Microdot may be in either location)

• Available in WLCSP (RDL ball arrays)

• Compliant with MIPI 26 MHz Read−Back

• This is a Pb−Free Device

ORDERING INFORMATION

See detailed ordering and shipping information on page 30 of

this data sheet.

Typical Applications

• Multi−band, Multi−standard, Advanced and Simple Mobile Phones

• Tunable Antenna Matching Networks

• Compatible with Closed−loop and Open−loop Antenna Tuner

Applications

1

Publication Order Number:

September, 2019 − Rev. 5

TCC−303/D

TCC−303

L_BOOST VHV

GND_BOOST

VREG

Booster

Regulator

Bandgap

VDDA

GND

vio_on

ibias_start / vref_start

VREG

POR

RC

OSC

7 bit

DAC

4 bit

DAC

7

OUTA

VIO

POR

VIO

por_vreg

Start

Reference

Registers

7 bit

DAC

7

OUTB

OUTC

7 bit

DAC

Interface

Level

Shifter

Level

VIO

Shifter

VDDA

VREG

VHV

OTP

CLK

DATA

ATEST

Figure 1. Control IC Functional Block Diagram

A1

OUTC

A2

VREG

A3

VHV

A3

B3

C3

D3

A2

B2

C2

D2

A1

B1

C1

D1

B1

OUTB

B2

ATEST

B3

L_BOOST

C1

OUTA

C2

GND

C3

VDDA

D1

VIO

D2

DATA

D3

CLK

Figure 2. RDL Padout, Bump Side View (left), PCB footprint (right), with RDL Bump Assignment

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2

TCC−303

RDL Pin Out

Table 1. PAD DESCRIPTIONS

RDL

Name

OUTC

VREG

VHV

Type

AOH

AO

Description

High Voltage Output C

Regulator Output

A1

A2

A3

AOH / AIH

AOH

AO

Boost High Voltage can be Forced Externally

High Voltage Output B

Analog Test Out (Note 1)

Boost Inductor

B1

OUTB

ATEST

L_BOOST

OUTA

GND

B2

B3

AOH

P

C1

High Voltage Output A

Ground

C2

C3

VDDA

VIO

P

Analog Supply

D1

P

Digital IO Supply

D2

DATA

CLK

DIO

DI

MIPI RFFE Digital IO

MIPI RFFE Clock

D3

Legend: Pad Types

AIH= High Voltage Analog Input

AO= Analog Output

AOH= High Voltage Analog Output

DI= Digital Input

DIO= Digital Input/Output (IO)

P= Power

1. To be grounded in normal operation.

ELECTRICAL PERFORMANCE SPECIFICATIONS

Table 2. ABSOLUTE MAXIMUM RATINGS

Symbol

VDDA

VIO

Parameter

Rating

−0.3 to +5.5

−0.3 to +2.5

−0.3 to VIO + 0.3

−0.3 to 30

2,000

Unit

V

Analog Supply Voltage

IO Reference Supply Voltage

V

I/O

Input Voltage Logic Lines (DATA, CLK)

VHV Maximum Voltage

V

HVH

ESD (HBM)

V

Human Body Model, JESD22−A114, All I/O

Machine Model, JESD22−A115

V

200

V

ESD (MM)

T

Storage Temperature

−55 to +150

+110

°C

STG

T

Max Operating Ambient Temperature without Damage

AMB_OP_MAX

Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality

should not be assumed, damage may occur and reliability may be affected.

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3

TCC−303

Table 3. RECOMENDED OPERATING CONDITIONS

Rating

Min

Typ

−

Max

+85

Symbol

Parameter

Operating Ambient Temperature

Operating Junction Temperature

Analog Supply Voltage

Unit

°C

V

T

−30

2.3

AMB_OP

T

J_OP

−

+125

5.5

VDDA

VIO

−

IO Reference Supply Voltage

1.62

−

1.98

V

Functional operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses beyond

the Recommended Operating Ranges limits may affect device reliability.

Table 4. DC CHARACTERISTICS (T = −30 to +85°C; V

= 15 V for each output; 2.3 V<VDDA< 5.5 V; V = 1.8 V; R

= 15 mH; unless otherwise specified)

=

A

OUTX

IO

LOAD

equivalent series load of 5.6 kW and 2.7 nF; C = 22 nF; L

HV

BOOST

Symbol

Parameter

Min

Typ

Max

Unit

Comment

SHUTDOWN MODE

I

VDDA Supply Current

L_BOOST Leakage

Battery Current

−

1.5

2.5

1

mA

VIO Supply is Low

VDDA

I

L_BOOST

I

−

BATT

I

VIO Supply Current

CLK Leakage

−1

VIO

I

1

CLK

I

DATA Leakage

1

DATA

ACTIVE MODE

I

Average battery current, 3 outputs act-

ively switching 16 V for 1205 ms to 2 V

for 1705 ms to 8 V for 1705 ms

−

980

1290

mA

At VHV = 20 V

VDDA = 3.3 V

BATT

I

Average battery current, 3 outputs @

0 V steady state

−

590

610

780

730

830

860

At VHV = 20 V

VDDA = 3.3 V

BATT_SS0

I

Average battery current, 3 outputs @

2 V steady state

At VHV = 20 V

VDDA = 3.3 V

BAT_SS2

I

Average battery current, 3 outputs @

16 V steady state

1020

1000

At VHV = 20 V

VDDA = 3.3 V

BATT_SS16

I

Average inductor current, 3 outputs ac-

tively switching 16 V for 1205 ms to 2 V

for 1705 ms to 8 V for 1705 ms and 3

outputs are @ 16 V steady state

At VHV = 20 V

VDDA = 3.3 V

L_BOOST

I

Average inductor current, 3 outputs @

0 V steady state

−

350

380

550

570

750

At VHV = 20 V

VDDA = 3.3 V

L_BOOST_SS0

Average inductor current, 3 outputs @

2 V steady state

At VHV = 20 V

VDDA = 3.3 V

L_BOOST_SS2

I

Average inductor current, 3 outputs @

16 V steady state

At VHV = 20 V

VDDA = 3.3 V

L_BOOST_SS16

I

VIO average inactive current

VIO average active current

−

3

VIO is high, no bus activity

VIO_INACT

I

250

VIO = 1.8 V, master sending

data at 26 MHz

VIO_ACTIVE

V

VREG

1.7

−

1.9

V

No external load allowed

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4

TCC−303

Table 4. DC CHARACTERISTICS (T = −30 to +85°C; V

= 15 V for each output; 2.3 V<VDDA< 5.5 V; V = 1.8 V; R

= 15 mH; unless otherwise specified)

=

A

OUTX

IO

LOAD

equivalent series load of 5.6 kW and 2.7 nF; C = 22 nF; L

HV

BOOST

Symbol

Parameter

Min

Typ

Max

Unit

Comment

LOW POWER MODE

I

VDDA Supply Current

L_BOOST Leakage

Battery Current

−

8

6

mA

VDDA

I

L_BOOST

I

−

14

3

I

+ I

BATT

VDDA L_BOOST

I

VIO Supply Current

−

No bus activity

No external load allowed

VIO

V

1.6

1.9

V

VREG

Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product

performance may not be indicated by the Electrical Characteristics if operated under different conditions.

Table 5. BOOST CONVERTER CHARACTERISTICS

(VDDA from 2.3 V to 5.5 V; V = 1.8 V; T = –30 to +85°C; C = 22 nF; L

= 15 mH; unless otherwise specified)

IO

A

HV

BOOST

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

VHV_min

Minimum programmable output volt-

age (average), DAC Boost = 0h

Active mode

4−bit DAC

−

13

−

V

VHV_max

Maximum programmable output volt-

age (average), DAC Boost = Fh

−

28

−

Resolution

Boost voltage resolution

Inductor current limit

−

1

−

I

200

mA

L_BOOST_LIMIT

Table 6. ANALOG OUTPUTS (OUT A, OUT B, OUT C)

(VDDA from 2.3 V to 5.5 V; V = 1.8 V; V = 26 V; T = –30 to +85°C; R

= ∞ unless otherwise specified)

IO

HV

A

load

Parameter

Description

Min

Typ

Max

Unit

Comment

SHUTDOWN MODE

Z

OUT

OUT A, OUT B, OUT C output

impedance

7

−

MW

DAC disabled

ACTIVE MODE

V

Maximum output voltage

−

24

−

1

V

DAC A, B, C = 7Fh,

OH

DAC Boost = Fh, I < 10 mA

OH

V

Minimum output voltage

DAC A, B C = 01h, DAC Boost = 0h

OL

to Fh, I < 10 mA

OH

Slew Rate

3

10

ms

2 V to 20 V step, measured at

V

R

= 15.2 V,

OUT

= equivalent series load of

LOAD

5.6 kW and 2.7 nF, Turbo enabled

R

OUT A, OUT B, OUT C set in pull−

down mode

−

1000

W

DAC A, B C = 00h, DAC Boost = 0h

to Fh, selected output(s) is disabled

PD

Resolution

Voltage resolution (1−bit)

−

189

−

mV

(1 LSB = 1−bit)

V

Zero scale, least squared best fit

−1

+1

LSB

OFFSET

Gain Error

DNL

−3.0

−0.9

−

+3.0

+0.9

%V

1 V to 24 V with 26 V VHV

OUT

Differential non−linearity least

squared best fit

−

LSB

INL

Integral non−linearity least squared

best fit

−1

−

+1

LSB

1 V to 24 V with 26 V VHV

I

Over current protection

−

5

−

65

40

mA

Any DAC output shorted to ground

1 V to 24 V with 26 V VHV

SC

V

Output ripple with all outputs at

steady state

mV RMS

RIPPLE

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5

TCC−303

THEORY OF OPERATION

Overview

2. Startup Mode: Startup is only a transitory mode.

Startup mode is entered upon a VIO high state. In

startup mode all registers are reset to their default

states, the digital interface is functional, the boost

converter is activated, outputs OUT A, OUT B,

OUT C are disabled and the DAC outputs are

placed in a high Z state. Control software can

request a full hardware and register reset of the

TCC−303 by sending an appropriate PWR_MODE

command to direct the chip from either the active

mode or the low power mode to the startup mode.

From the startup mode the device automatically

proceeds to the active mode.

The control IC outputs are directly controlled by

programming the three DACs (DAC A, DAC B, DAC C)

through the digital interface.

The DAC stages are driven from a reference voltage,

generating an analog output voltage driving a high−voltage

amplifier supplied from the boost converter (see Figure 1 −

Control IC Functional Block Diagram).

The control IC output voltages are scaled from 0 V to

24 V, with 127 steps of 189 mV. The nominal control IC

output can be approximated to 189 mV x (DAC value).

For performance optimization the boost output voltage

(VHV) can be programmed to levels between 13 V and 28 V

via the DAC_boost register (4 bits with 1 V steps). The

startup default level for the boosted voltage is VHV = 24 V.

For proper operation and to avoid saturation of the output

devices and noise issues, it is recommended to operate the

boosted VHV voltage at least 2 V (>4 V [6 V recommended]

if using Turbo−Charge Mode) above the highest

3. Active Mode: All blocks of the TCC−303 are

activated and the DAC outputs are fully controlled

through the digital interface, DACs remain off

until enabled. The DAC settings can be

dynamically modified and the HV outputs will be

adjusted according to the specified timing

programmed V

voltage of any of the three outputs.

diagrams. Each DAC can be individually

OUT

controlled and/or switched off according to

application requirements. Active mode is

Operating Modes

The following operating modes are available:

1. Shutdown Mode: All circuit blocks are off, the

DAC outputs are disabled and placed in high Z

state and current consumption is limited to

automatically entered from the startup mode.

Active mode can also be entered from the low

power mode under control software command.

4. Low Power Mode: In low power mode the serial

interface stays enabled, the DAC outputs are

disabled and are placed in a high Z state and the

boost voltage circuit is disabled. Control software

can request to enter the low power mode from the

active mode by sending an appropriate

minimal leakage current. The shutdown mode is

entered upon initial application of VDDA or upon

VIO being placed in the low state. The contents of

the registers are not maintained in shutdown mode.

PWR_MODE command. The contents of all

registers are maintained in the low power mode.

Battery insertion

VDDA = 0

VIO = HIGH

Startup

Shutdown

(Registers reset)

PWR_MODE =

0b01

PWR_MODE =

0b01

VIO = LOW

automatic

PWR_MODE = 0b00

PWR_MODE = 0b10

Active

(User Defined)

Low Power

(User Defined)

Figure 3. Modes of Operation

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6

TCC−303

VDDA Power−On Reset (POR)

VIO Power−On Reset and Startup Conditions

Upon application of VDDA, TCC−303 will be in

shutdown mode. All circuit blocks are off and the chip draws

only minimal leakage current.

A high level on VIO places the chip in startup mode which

provides a POR to TCC−303. POR resets all registers to their

default settings as described in Register Content Details.

VIO POR also resets the serial interface circuitry. POR isnot

a brown−out detector and VIO needs to be brought back to

a low level to enable the POR to trigger again.

Table 7. VIO POWER−ON RESET AND STARTUP

Default State for

VIO POR

Register

DAC Boost

Power Mode

DAC Enable

DAC A

Comment

[1011]

VHV = 24 V

Transitions from shutdown to startup and then automatically to active mode

A, B, C Disabled

[01]>[00]

[000]

V

OUT

Output in High−Z Mode

DAC B

DAC C

VIO Shutdown

A low level at any time on VIO places the chip in shutdown mode in which all circuit blocks are off. The contents of the

registers are not maintained in shutdown mode.

Table 8. VIO THRESHOLDS (VDDA from 2.3 V to 5.5 V; T = –30 to +85°C unless otherwise specified)

A

Parameter

Description

Min

Typ

Max

Unit

Comments

VIORST

VIO Low Threshold

−

0.2

V

When VIO is lowered below this threshold level the

chip is reset and placed into the shutdown mode

Power Supply Sequencing

The VDDA input is typically directly supplied from the battery and thus is the first on. After VDDA is applied and before VIO

is applied to the chip, all circuits are in the shutdown mode and draw minimum leakage currents. Upon application of VIO,

the chip automatically starts up using default settings and is placed in the active state waiting for a command via the serial

interface.

Table 9. TIMING (VDDA from 2.3 V to 5.5 V; V = 1.8 V; T = –30 to +85°C; OUT A, OUT B, OUT C; CHV = 47 nF; L = 15 mH;

BOOST

IO

A

VHV = 20 V; Turbo−Charge mode off unless otherwise specified)

Parameter

Description

Min

−

Typ

50

Max

120

−

Unit

ms

Comments

For info only

T

Internal bias settling time from shutdown to active mode

Time to charge CHV @ 95% of set VHV

Startup time from shutdown to active mode

POR_VREG

T

−

130

180

50

ms

BOOST_START

T

−

300

60

ms

SD_TO_ACT

T

SET+

Timing for a 2 V to 16 V transition, measured when

voltage reaches within 5% of target voltage, mea-

sured between the R (5.6 kW) and C (2.7 nF) of an

equivalent PTIC series load.

−

ms

Voltage settling time

connected on V

A, B, C

OUT

T

SET−

Timing for a 16 V to 2 V transition, measured when

voltage reaches within 5% of target voltage, mea-

sured between the R (5. 6 kW) and C (2.7 nF) of an

equivalent PTIC series load.

−

50

60

ms

Effective PTIC

tuning voltage

settling time,

measured between

an equivalent R and

C PTIC load

T

Output A, B, C positive settling time with Turbo

Output A, B, C negative settling time with Turbo

−

35

−

ms

Voltage settling time

SET+

connected on V

A, B, C

OUT

Voltage settling time

SET−

connected on V

A, B, C

OUT

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7

TCC−303

Figure 4. Output Settling Diagram

Figure 5. Startup Timing Diagram

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8

TCC−303

Boost Control

Due to the slow response time of the control loop, the

VHV voltage may drop below the set voltage before the

control loop compensates for it. In the same manner, VHV

can rise higher than the set value. This effect may reduce the

maximum output voltage available. Please refer to Figure 6

below.

TCC−303 integrates an asynchronous current control

boost converter. It operates in a discontinuous mode and

features spread−spectrum circuitry for Electro−Magnetic

Interference (EMI) reduction. The average boost clock is

2 MHz and the clock is spread between 0.8 MHz and 4 MHz.

The asynchronous control reduces switching losses and

improves the output (VHV) regulation of the DC/DC

converter under light load, particularly in the situation

where TCC−303 only maintains the output voltages to fixed

values.

Boost Output Voltage (VHV) Control Principle

The asynchronous control starts the boost converter as

soon as the VHV voltage drops below the reference set by

the 4−bit DAC and stops the boost converter when the VHV

voltage rises above the reference again.

CHV

Recharge

CHV

Discharge

VHV

Set

Delay

VHV

Time

Boost

Running

Figure 6. VHV Voltage Waveform

High Impedance (High Z) Feature

In shutdown mode the OUT pins are set to a high

impedance mode (high Z). Following is the principle of

operation for the control IC:

1. The DAC output voltage V

is defined by:

OUT

DAC code

V_OUT

+

24 V

(eq. 1)

127

2. The voltage VHV defines the maximum supply

voltage of the DAC supply output regulator and is

set by a 4−bit control.

3. The maximum DAC DC output voltage V

is

OUT

Figure 8. DAC Output Range Example B

Digital Interface

The control IC is fully controlled through a digital

interface (DATA, CLK). The digital interface is described in

the following sections of this document.

limited to (VHV – 2 V). DAC can achieve higher

output voltages, but timing is not maintained for

swings above VHV − 2 V.

4. The minimum output DAC voltage V

max.

is 1.0 V

OUT

Turbo−Charge Mode

The TCC−303 control IC has a Turbo−Charge Mode that

significantly shortens the system settling time when

changing programming voltages.

In Turbo−Charge Mode the DAC output target voltage is

temporarily set to either a delta voltage above or a delta

voltage below the actual desired target. The delta voltage is

4 volts.

After the DAC value message is received, the delta

voltage is calculated by hardware, and is applied in digital

format to the input of the DAC, right after trigger is received.

The period for which the delta voltage is maintained to the

input of the DAC, the Turbo time, is calculated based on

following considerations:

Figure 7. DAC Output Range Example A

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9

TCC−303

• DAC_TIMER_A[4:0] / DAC_TIMER_B[4:0] /

DAC_TIMER_C[4:0]: These are the DAC timer

configuration fields. For the turbo mode, they define

the turbo latency value, when the target+delta voltage is

active. If each DAC is updated over and over with the

same turbo delay value, these fields do NOT need to be

updated at each DAC update. The register has to hold a

non−zero value for a Turbo update.

• The Turbo UP or DOWN voltage is decided based on

the comparison of the new DAC value and the old DAC

value. If the new value is greater, the turbo direction

will be UP. Otherwise it will be down. In case of both

DAC values being equal, there is no DAC update

applied.After a turbo request is received, any trigger

will start the turbo output transition. The trigger could

be:

♦ A MIPI−RFFE software trigger controlled by

RFFE_PM_TRIG register

♦ An internal generated trigger after the corresponding

DAC value is updated, as described in section DAC

Update Triggering.

• DAC_TC2X_A / DAC_TC2X_B / DAC_TC2X_C: If

these bits are set, the timer loads DAC_TIMER_X * 2

value as opposed to DAC_TIMER_X value. This

allows a turbo operation delay up to 124 ms.

• DAC_TCM_A [1:0] / DAC_TCM_B [1:0] /

DAC_TCM_C [1:0] : If the Turbo direction is down

and the Turbo target is below 4 V, these multiplication

factors are utilized to extend the turbo delay. Further

formula provided below.

The DAC values send by digital turbo−charge logic to

DACs are:

• During turbo−charge delay duration the value applied is

“DAC_new 4 V” (the polarity of the 4 V turbo will

depend on if turbo charge is up or down)

• GL_A / GL_B / GL_C: These are the DAC update

mode configuration fields, which need to be set to turbo

mode at the new DAC value update and prior to the SW

trigger (optional). These bits are part of the DAC value

register. If they are set to 0, the DAC is in Turbo Mode,

as long as the corresponding DAC_TIMER register is

non−zero. A DAC_TIMER =0 means an immediate

update independent of the GL_A/B/C value.

• If DAC_new > DAC old, and DAC_new+4 V is

exceeding the word length of the DAC, it is saturated to

max value possible.

• If DAC_new < DAC_old, and DAC_new−4 V is a

negative number, a DAC value of 0 is applied.

♦ After turbo−charge delay duration the value applied

is the actual DAC_new.

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10

TCC−303

Table 10. DAC_TIMER_A/B/C UNIT DELAYS

DAC_TIMER_A/B/C [4:0]

Bit 4

0

1

Bit 3

0

1

0

1

Bit 2

0

1

0

1

0

1

0

1

Bit 1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

Bit 0

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

Turbo delay time in Turbo Mode or glide step duration in Glide Mode [ms]

Immediate Update

2

4

6

8

10

12

14

16

18

20

22

24

26

28

30

32

34

36

38

40

42

44

46

48

50

52

54

56

58

60

62

The value of turbo delay time is deducted based on the

hardware comparison of new DAC value in respect to old

DAC value, as follows. In this calculation the decimal “21”

value corresponds to 4 V DAC drive. As the DAC new value

is closer to 0 V in a down Turbo, the delay time increases

more.

If DAC new < DAC old, and DAC new > 21, then T

= DAC_TIMER_A/B/C << DAC_TC2X_A/B/C

If DAC new < DAC old, and DAC new = 21, then T

= DAC_TIMER_A/B/C << DAC_TC2X_A/B/C

DOWN

Table 11. TURBO−CHARGE MULTIPLICATION FACTOR

TCM [1:0]

Multiplication Factor

If DAC new

DAC_TIMER_A/B/C << DAC_TC2X_A/B/C

If DAC new < DAC old, and DAC new < 21, then T

>

DAC old, then

T

=

UP

00 (default)

4

3

2

1

DOWN

01

10

11

=

DAC_TIMER_A/B/C << DAC_TC2X_A/B/C

+

DAC_TCM_A/B/C * (21 – DAC new)

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11

TCC−303

Transition from Turbo to Turbo or Immediate Update

From the moment the trigger is received, a tick is

generated internally, with a frequency controlled by the

DAC_TIMER_A/B/C registers. Each DAC has its own tick

generator running independently of the other DAC. Each

time a trigger is received for a DAC, the setting of the

DAC_TIMER_A/B/C register is sampled in a counter

dedicated to that DAC. Any update of the

DAC_TIMER_A/B/C register after trigger is received will

be ignored until the next trigger is received

Each time a tick is generated, the content of the

accumulator is either incremented or decremented,

depending whether DAC_new is either bigger or smaller

than DAC_old.

In the event a new trigger is received during a turbo

transition, the ongoing turbo operation is halted and the new

DAC value is applied immediately. There won’t be any

Turbo and the hi_slew is kept low.

Transition from Turbo to Glide

In the event that a new glide transition is triggered during

a turbo event, then the turbo process is stopped and the

current target value is set at the DAC output immediately

without hi_slew. The new glide is started from this value.

DAC disable during Turbo (including active to low

power mode transition)

ACCUMULATOR[14:0] = ACCUMULATOR[14:0] +

GLIDE_STEP; if DAC_new > DAC_old

ACCUMULATOR[14:0] = ACCUMULATOR[14:0] −

GLIDE_STEP; if DAC_new < DAC_old

If the DAC, which is in Turbo is disabled, the target DAC

value is immediately applied without hi_slew. The DAC

does not continue with the Turbo when it is re−enabled.

Glide Mode

Each time a tick is generated, the output of the DAC[6:0]

is updated with the value of ACCUMULATOR[14:8];

The Gliding process continues until, upper 7 bits of the

accumulator matches the value of the DAC_new.

ACCUMULATOR[14:8] ≥ DAC_new, when DAC_new

> DAC_old

The TCC−303 control IC has a Glide Mode that

significantly extends the system transition time when

changing programming voltages.

Glide Mode is controlled by the following registers:

• DAC_TIMER_A[4:0] / DAC_TIMER_B[4:0] /

DAC_TIMER_C[4:0]: These are the DAC timer

configuration fields. For the glide mode they define the

step duration. If each DAC is updated over and over

with the same glide step, these fields do NOT need to

be updated at each DAC update. The register has to

hold a non−zero value for a Glide update.

• GL_A / GL_B / GL_C: These are the DAC update

mode configuration fields, which need to be set to glide

mode at the new DAC value update and prior to the SW

trigger (optional). These bits are part of the DAC value

register. If they are set to 1, the DAC is in glide mode,

as long as the corresponding DAC_TIMER register is

non−zero. A DAC_TIMER =0 means an immediate

update independent of the GL_A/B/C value.

ACCUMULATOR[14:8] ≤ DAC_new, when DAC_new

< DAC_old

The Glide timer will reference the 2 MHz clock divided to

provide between 2 ms and 62 ms per glide step.

Each DAC is independent in terms of its switching

operation, thus each DAC may be independently

programmed for Normal, Turbo or Glide regardless of the

switching operation of the other DACs.

Use−case hint:

In a scenario where the Turbo delay needs to be set to 54

us and the glide should be taking ~7 ms, the DAC_TIMER

can be configured as 7000/256 = 27 ms and the DAC_TC2X

configuration can be set. This way the timer value would not

need to be updated during the glide – turbo switches, and

only the GL_X bit in DAC value update needs to be toggled.

After a Glide request is received, any trigger will start the

Glide output transition.

The trigger could be:

• a MIPI−RFFE software trigger controlled by

RFFE_PM_TRIG register

Transition from Glide to Glide

In the event a new glide request is received during a glide

transition, the ongoing glide operation is halted and the new

glide operation is started from the DAC value, where the

previous glide has left off. The DAC timers can be updated

to a new value at the trigger.

• an internal generated trigger after the corresponding

DAC value is updated, as described in a later section.

Immediately after the trigger, the DAC_old value is loaded

in the MSB’s of the upper byte of a 15 bit accumulator, while

the lower byte of accumulator is being reset to 0x00.

At the same time a count step is calculated:

Transition from Glide to Turbo or Normal Switching

In the event that a new Normal switching or Turbo DAC

value is received during a Glide transition, then the Glide

process is stopped and the DAC immediately switches to the

newly received target value without Turbo or Glide. The

hi_slew is not applied.

GLIDE_STEP[6:0]

DAC_new > DAC_old

GLIDE_STEP[6:0]

=

DAC_new

–

DAC_old; if

=

DAC_old

–

DAC_new; if

DAC_new < DAC_old

ACCUMULATOR[14:0] = DAC_old, 0x00;

DAC Disable during Glide (including active to low

power mode transition)

If the DAC, which is gliding is disabled, the DAC value

holds on to the value where the glide stops. The DAC does

NOTE: Glide is disabled if DAC_new = DAC_old.

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12

TCC−303

not continue with the glide when it is re−enabled. It drives

the last calculated DAC value without a hi_slew.

After the DACx_value register is written using

MIPI−RFFE clock, the data is copied on RC clock domain,

into the first data stage represented in Figure 9 as

‘Completed’. The data is moved into ‘New’ and ‘DAC−Out’

stages by the DAC driver state machine, once the trigger is

detected. The Turbo path also highlights the glide

calculation.

If SW trigger is not enabled, then data will flow through

the stages right after the corresponding DAC is updated,

without waiting for a trigger (MIPI write is considered as the

trigger).

DAC Update Triggering

The entire digital logic responsible for DAC updates is

using the clock provided by the internal RC oscillator. In

order to minimize the power consumption, the RC clock is

set at a low frequency around 2 MHz.

DAC Writes

Figure 9 shows the diagram of the DAC data path, from

the moment data is written into DACx_value register, until

it is sent out to DAC.

Figure 9. DACx Data Path

To bypass the SW trigger and enable an immediate trigger

the Mask bits under the RFFE_PM_TRIG register should be

set according to the USID control of the DAC. Trigger Mask

2 is controller with USID_2, Trigger Mask 1 is controlled

with USID_1 and Trigger Mask 0 is controlled with USID_0.

In MIPI−RFFE configuration, if RFFE_PM_TRIG /

same USID or the DURs of the DACs are sitting at “11”

configuration. Right after MIPI_RFEE_WRITE #1 to

RFFE_REG_0x06, above, is received the DAC_A value

register is copied in ‘Completed’ stage of DAC_A. The

timers DO NOT need to be updated for each DAC update.

But if they need to be, they can be updated as part of a full

extended write or single write prior to the DAC value

updates without any timing limitation. Since the SW trigger

is masked, next RC clock cycle after DAC values are copied

in ‘Completed’ stage, the data will move in next stages

‘New’ and ‘DAC−Out’ without waiting for any trigger.

The similar events occur for DAC_B and DAC_C after

the MIPI_RFEE_WRITE #2 and MIPI_RFEE_WRITE #3.

Due to the fact that the MIPI−RFFE master can send DAC

updates messages at a higher frequency, than RC clock, the

data buffer ‘Completed’, can be overwritten if new DAC

updates occur in the same time when the buffer is loaded.

While data and configuration are copied from

DACx_value register into ‘Completed’ stage, the

MIPI−RFFE master must not send any new DAC updates to

DACx_value registers or configurations. The time required

Trigger_Mask_2

Trigger_Mask_1

=

‘1’, and RFFE_PM_TRIG

‘1’ and RFFE_PM_TRIG

/

Trigger_Mask_0 = ‘1’ (all software triggers are masked), then

each DAC value is copied into ‘Completed’ stages of each

DAC,

after

the

messages

RFFE_REG_0x06,

RFFE_REG_0x07 or RFFE_REG_0x08 respectively are

received, as shown in following sequence.

MIPI_RFFE_WRITE #1: send DAC_A_value and

glide/turbo mode to RFFE_REG_0x06

MIPI_RFFE_WRITE #2: send DAC_B_value and

glide/turbo mode to RFFE_REG_0x07

MIPI_RFFE_WRITE #3: send DAC_C_value and

glide/turbo mode to RFFE_REG_0x08

The individual writes above could be combined into a

single extended write with all DACs controlled with the

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13

TCC−303

for the data to be copied from DACx_value register into

The DAC enables (RFFE_REG_0x00) and Booster

configurations (RFFE_REG_0x02) are applied

immediately without waiting any trigger. These registers

should be configured prior, so that the DAC updates are

effective as fast as possible. In test mode the hi_slew settings

are sampled at the trigger similar to the dac_timers.

‘Completed’ stage is Max 1500 ns, which is defined by the

three RC clock cycles required to synchronize data from

MIPI−RFFE clock domain to RC clock domain.

In Figure 10, DAC_UPDATE_LAT represents the period

when MIPI−RFFE master is not allowed to send any new

DAC updates to DACx_value registers and DAC

configuration registers.

Figure 10. DAC_UPDATE_LAT Requirement

The SW trigger as well as immediate trigger can be

configured in many combinations using the DUR settings of

the DACs and the USID values. The SW trigger masks can

only be changed with the write access using the slave

address of their corresponding USID. But the corresponding

triggers can be set by accesses over broadcast, with

broadcast ID (0x0) or GSID.

The triggering and DAC register access is governed by

these rules:

• The DUR configuration assigns a DAC to a USID. The

corresponding DAC registers can only be accessed with

USID defined by its DUR.

• The immediate update of this DAC is enabled if the SW

trigger mask of the corresponding USID is set (disabled).

• The PM_TRIG register bit0 (SW trigger0) is masked by

bit4 and assigned to DACs triggering, which are mapped

to USID0 or all USIDs (the DAC DUR=0 or 3).

• The PM_TRIG register bit1 (SW trigger1) is masked by

bit5 and assigned to DACs triggering, which are mapped

to USID1 or all USIDs (the DAC DUR=1 or 3).

If all DACs are kept at DUR values of 3 and the USIDs are

kept the same (reset condition), the part behaves according

to the MIPI spec with single USID. If some of the USIDs are

different while DUR=3, the part responds to the accesses

with these different USIDs the same fashion.

If all USIDs are kept equal, the part functions with a single

USID. But the DUR settings still control the SW trigger

mapping for the DACs independent of the USID values. The

DACs which are not holding a DUR value of 3 will be under

the control of the SW trigger−mask duo mapped by their

DUR setting.

In Table 12 some example register settings for listed

functionality are provided. For the given functionality the

response of the part to DAC updates and SW triggers are

tabulated. In this table the “DAC trigger” corresponds to a

trigger happening at the time of the DAC value update. The

“SW trigger” corresponds to a trigger happening with the

PM_TRIG register write. At this point, it is assumed that the

DACs are enabled and the new DAC value is not matching

to the existing pre−triggered DAC value in the active

register. Some of the abbreviations utilized in the table are:

• The PM_TRIG register bit2 (SW trigger2) is masked by

bit6 and assigned to DACs triggering, which are mapped

to USID2 or all USIDs (the DAC DUR=2 or 3).

TRG = successful trigger of the new targets

HLD = no trigger, hold on to existing DAC drives

WR = The new DAC values are captured into RFFE shadow

registers

• For a DAC with DUR=3, all SW masks need to be set

for that DAC to be triggered with direct access to its

target register.

NW = The RFFE write to shadow registers are blocked, no

register update.

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14

TCC−303

Table 12. IMMEDIATE vs SOFTWARE TRIGGERING USING USIDs and DURs

DACA DACA DACA DACA Trigger Trigger Trigger Trigger Trigger Trigger Trigger

FUNCTIONALITY & EXAM-

PLE REGISTER VALUES

WR

ID0

WR

ID1

WR

WR 3b111 3b111 3b111 3b111 3b001 3b010 3b100

ID1 ID2 Broad Broad Broad Broad

Comments

ID2 Broad ID0

(DEFAULT) DAC TRIGGER TRG TRG TRG HLD HLD HLD HLD HLD HLD HLD HLD All USIDs are the same. All

– SINGLE USID – DUR=3

(WR) (WR) (WR) (NW)

SW triggers are masked.

The USID DAC writes trig-

ger immediately.

DUR_A = 3 (USIDx, TRGx)

SW−TRG Mask = 3’b111

USID0,1,2 = 4b0111

SW TRIGGER −SINGLE

USID – DUR =3

HLD HLD HLD HLD TRG TRG TRG TRG HLD TRG HLD All USIDs are the same.

(WR) (WR) (WR) (NW)

Only trigger 1 is enabled.

This enables the SW trig-

ger since DUR=3, mapping

the DAC to all triggers

DUR_A = 3 (USIDx, TRGx)

SW−TRG Mask = 3’b101

USID0,1,2 = 4b0111

DAC TRIGGER −SINGLE

USID – DUR=0

TRG TRG TRG HLD HLD HLD HLD HLD HLD HLD HLD All USIDs are the same.

(WR) (WR) (WR) (NW)

Only trigger 1 is enabled.

The DUR of the DAC is

mapping it to trigger 0

(masked). Therefore SW

trigger is disabled.

DUR_A = 0 (USID0, TRG0)

SW−TRG Mask = 3’b101

USID0,1,2 = 4b0111

SW TRIGGER −SINGLE

USID – DUR =1

HLD HLD HLD HLD TRG TRG TRG TRG HLD TRG HLD All USID’s are the same.

(WR) (WR) (WR) (NW)

Only trigger 1 is enabled.

The DUR of the DAC is

mapping it to trigger 1 (en-

abled). Therefore SW trig-

ger is enabled.

DUR_A = 1 (USID1, TRG1)

SW−TRG Mask = 3’b101

USID0,1,2 = 4b0111

DAC TRIGGER – (1,2)

USIDs – DUR=2

HLD HLD TRG HLD HLD HLD HLD HLD HLD HLD HLD USID2 is different, only

(NW) (NW) (WR) (NW)

USID2 dac access is al-

lowed and the DAC trig-

gers immediately, since the

SW trigger mask is set.

DUR_A = 2 (USID2, TRG2)

SW−TRG Mask = 3’b100

USID0,1 = 4b0111, USID2 =

4b1000

SW TRIGGER – (1,2)

USIDs – DUR =2

HLD HLD HLD HLD HLD HLD TRG TRG HLD HLD TRG USID2 is different, only

(NW) (NW) (WR) (NW)

USID2 dac access is al-

lowed. Trigger 2 is un-

masked, SW trigger is en-

abled. Only trigger 2 is ac-

tive for USID2.

DUR_A = 2 (USID2, TRG2)

SW−TRG Mask = 3’b000

USID0,1 = 4b0111, USID2 =

4b1000

DAC TRIGGER – (2,1)

USIDs – DUR = 1

TRG TRG HLD HLD HLD HLD HLD HLD HLD HLD HLD Since USID0 = USID1 both

(WR) (WR) (NW) (NW)

USID0, USID1 DAC target

writes are allowed. SW

trigger1 masked; SW trig-

gering disabled

DUR_A = 1 (USID1, TRG1)

SW−TRG Mask = 3’b110

USID0,1 = 4b0111, USID2 =

4b1000

SW TRIGGER – (2,1)

USIDs –DUR = 1

HLD HLD HLD HLD TRG TRG HLD TRG HLD TRG HLD Same as above but SW

(WR) (WR) (NW) (NW)

trigger 1 is enabled; SW

triggering enabled. USID0,

USID1 are the same but

the DAC is mapped to Trg1

only. Trg0 alone does not

trigger.

DUR_A = 1 (USID1, TRG1)

SW−TRG Mask = 3’b100

USID0,1 = 4b0111, USID2 =

4b1000

DAC TRIGGER – (1,1,1)

USIDs – DUR = 0

TRG HLD HLD HLD HLD HLD HLD HLD HLD HLD HLD The DAC is mapped to

(WR) (NW) (NW) (NW)

USID0 and the corre-

sponding trigger is

masked. It triggers imme-

diately at DAC update with

USID0

DUR_A = 0 (USID0, TRG0)

SW−TRG Mask = 3’b001

USID0 = 4b0111, USID1 =

4b1000, USID2 = 4b1001

SW TRIGGER – (1,1,1)

USIDs – DUR = 0

HLD HLD HLD HLD TRG HLD HLD TRG TRG HLD HLD The DAC is mapped to

(WR) (NW) (NW) (NW)

USID0 and the TRG0 is

enabled. It triggers only at

TRG0 with USID0 or

Broadcast access

DUR_A = 0 (USID0, TRG0)

SW−TRG Mask = 3’b000

USID0 = 4b0111, USID1 =

4b1000, USID2 = 4b1001

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15

TCC−303

MIPI RFFE Interface

capture is a violation for RFFE interface standard. The

violation is due to the toggling during the 2 half of the bus

park cycle, which could create bus contention with the

master.

nd

TCC−303 is a slave device and is fully compliant to the

MIPI Alliance Specification for RF Front−End Control

Interface (RFFE) Version 1.10.00.

Following MIPI RFFE commands are supported:

1. Register 0 WRITE

The extended register write long and read long commands

are not supported. If an extended register write long

command is received, no register is written and the

RFFE_STATUS.WURE flag is set. If an extended register

read long command is received, the part responds with bus

idle and the RFFE_STATUS.RURE flag is set.

2. Register WRITE

3. Register READ

4. Extended Register WRITE

5. Extended Register READ

Registers 0x00 to 0x1F are available to be read/written. At

full−speed read with heavy load, the RFFE read mode bit

RFFE_RDM can be configured to ‘1’, to shift the data

capture to falling edge. Otherwise it is recommended to keep

this bit in its default state, since the falling edge read data

The read access to registers RFFE_REG_0x03 to

RFFE_REG_0x08 returns the active register content, which

is the register updated after a trigger. The pre−trigger

shadow register does not have read access.

Table 13. MIPI RFFE INTERFACE SPECIFICATION

(T = −30 to +85°C; 2.3 V < VDDA < 5.5 V; 1.1 V < V < 1.8 V; unless otherwise specified)

A

IO

Parameter

Description

Min

Typ

Max

Unit

Comments

F

SCLK

Clock Full−Speed

Frequency

0.032

−

26

MHz

Full−Speed Operation:

1.65 V < V < 1.95 V

IO

T

SCLK

Clock Full−Speed Period

0.038

−

32

ms

Full−Speed Operation:

1.65 V < V < 1.95 V

IO

T

CLK Input High Time

CLK Input Low Time

11.25

−

ns

V

Full−Speed

SCLKIH

T

Full−Speed

SCLKIL

V

Positive Going Threshold

Voltage

0.4 x VIO

0.7 x VIO

CLK, DATA, 1.2 or 1.8 V Bus

TP

Negative Going Thresh-

old Voltage

0.3 x VIO

0.1 x VIO

−

0.6 x VIO

0.4 x VIO

V

CLK, DATA, 1.2 or 1.8 V Bus

TN

V

H

Hysteresis Voltage

(V – V

)

TP

TN

I

Input Current High

−2

−1

−2

−1

−

+10

+1

SDATA = 0.8 x VIO

SCLK = 0.8 x VIO

SDATA = 0.2 x VIO

SCLK = 0.2 x VIO

CLK Pin

mA

pF

ns

IH

I

Input Current Low

IL

+1

C

Input Capacitance

2.2

2.5

1

CLK

C

Input Capacitance

−

DATA Pin

DATA

TD

Write DATA Setup Time

Write DATA Hold Time

−

Full−Speed

SETUP

TD

−

5

Full−Speed

HOLD

T

Read DATA valid from

CLK rising edge

−

7.11

Full Speed at V = 1.80 V, +25°C,

READ_ACCESS

IO

and max 15 pF load on DATA pin

Read DATA valid from

CLK rising edge

−

9.11

ns

Full Speed at V = 1.80 V, +25°C,

READ_ACCESS

IO

and max 50 pF load on DATA pin

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16

TCC−303

CLK

TD

SETUP

TD

HOLD

DATA

Figure 11. MIPI−RFFE Signal Timing during Master Writes to PTIC Control IC

CLK

T

READ_ACCESS

T

SDATAOTR

SDATAZ

SDATAOTR

DATA

Bus Park Cycle

Figure 12. MIPI−RFFE Signal Timing during Master

Reads from PTIC Control IC

Figure 13. Bus Park Cycle Timing

when MIPI−RFFE Master Reads

from PTIC Control IC

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17

TCC−303

The control IC contains eighteen 8−bit registers. Register content is described in Table 14. Some additional registers

implemented as provision, are not described in this document.

Table 14. MIPI RFFE ADDRESS MAP

Address

Description

USID

Purpose

Access

Size [bits]

0x00

RFFE_REG_0x00

All

DAC enables

R/W

RegWrite0

8

0x01

0x02

RFFE_REG_0x01

RFFE_REG_0x02

RFFE_REG_0x03

RFFE_REG_0x04

RFFE_REG_0x05

RFFE_REG_0x06

RFFE_REG_0x07

RFFE_REG_0x08

RFFE_REG_0x09

SPARE

All

DUR for DAC_A/_B/_C

Booster settings

R/W

8

All

0x03

DUR_A

DUR_B

DUR_C

DUR_A

DUR_B

DUR_C

All

DAC_A timer setup

0x04

DAC_B timer setup

0x05

DAC_C timer setup

0x06

Used to set up / trigger OUT A

Used to set up / trigger OUT B

Used to set up / trigger OUT C

RFFE read mode control

Spare for future product development

0x07

0x08

0x09

0x09 to 0x17

0x18

N/A

USID_1

&

Broadcast

Spare [7:6]

[5,4] = Manufacturer ID [9:8]

USID_1 [3:0]

0x19

USID_2

&

Broadcast

Spare [7:6]

[5,4] = Manufacturer ID [9:8]

USID_2 [3:0]

R/W

8

0x1A

0x1B

0x1C

RFFE_STATUS

RFFE_GROUP_SID

RFFE_PM_TRIG

All

RFFE status register

R/W

8

The Group Broadcast ID

All

&

Power Mode & Trigger Control

PWR_MODE [7:6]

Broadcast

TRIG_REG [5:0]

0x1D

0x1E

PID_0, default

All

MIPI Product ID (Note 2)

R

8

Manufacturer ID Register

MN (10bits long)

Manufacturer ID[7:0] (Note 2)

0x1F

USID_0, default

USID_0

&

Broadcast

Spare [7:6]

[5,4] = Manufacturer ID [9:8] (Note 3)

USID [3:0]

R/W

8

2. The least significant bits from the Product ID register are refined by OTP. The other seven bits of product ID are hardcoded in ASIC.

3. The manufacturer ID is hardcoded in ASIC, mapped in a READ−only register.

Register Content Details

Register RFFE:

RFFE_REG_0x00

Address RFFE A[4:0]:

[0x00]

Reset Source: nreset_dig or SWR = ‘1’ or PWR_MODE = ‘01’ (transition through STARTUP mode)

7

6

5

4

3

2

1

0

Bits

spare

U−0

spare

U−0

spare

U−0

spare

U−0

spare

U−0

DAC C en

W−0

DAC B en

W−0

DAC A en

W−0

Reset

Bit [2:0] Each DAC is enabled when the corresponding bit is set. The enable or disable occurs immediately without waiting

for a trigger. 0: Off (default) 1: enabled

Bit [7]: Register 0 write command excludes this bit. The extended writes to this address ignores bit 7. The bit is not utilized.

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18

TCC−303

Register RFFE:

RFFE_REG_0x01

Address RFFE A[4:0]:

0x01

Reset Source: nreset_dig or SWR = ‘1’ or PWR_MODE = ‘01’ (transition through STARTUP mode)

7

6

5

4

3

2

1

0

Bits

spare

DUR_C [1:0]

DUR_B [1:0]

DUR_A [1:0]

W−1 W−1

Reset

U−0

W−1

DUR_x [1:0] (DAC x USID response)

‘00’: Responds only to USID_0 in DAC register write. SW trigger0 mask defines the triggering source.

‘01’: Responds only to USID_1 in DAC register write. SW trigger1 mask defines the triggering source.

‘10’: Responds only to USID_2 in DAC register write. SW trigger2 mask defines the triggering source.

‘11’: Responds to any 3 USID in DAC register write. Any trigger mask cleared enables the SW triggering.

Register RFFE:

RFFE_REG_0x02

Address RFFE A[4:0]:

0x02

Reset Source: nreset_dig or SWR = ‘1’ or PWR_MODE = ‘01’ (transition through STARTUP mode)

7

6

5

4

3

2

1

0

Bits

boost_clk_en

W−1

boost_pwm_en

W−1

spare

U−0

boost_en

W−1

Boost voltage value

W−0 W−1

Reset

W−1

Bit [7]: Enables the booster clock. The clock should be

disabled when the booster is turned off.

Bit [6]: Enables the boost oscillator pwm function. This

signal should be turned off in case the booster generates low

voltages to reduce the ripple.

Bit [4]: Enable/disable of the booster. Booster must be

turned off when the high voltage is provided externally.

Bit [3:0]: Boost voltage value. Refer to Table 15 for

values

Table 15. BOOST VOLTAGE SETTING

Boost Voltage Value[3:0]

VHV [V]

13

Note

Boost Voltage Value[3:0]

VHV [V]

Note

0000

0001

0010

0011

0100

0101

0110

0111

1000

1001

1010

1011

1100

1101

1110

1111

21

14

22

15

23

16

24 (default)

Target values

17

25

26

27

28

18

19

20

Register RFFE:

RFFE_REG_0x03

Address RFFE A[4:0]:

[0x03]

Reset Source: nreset_dig or SWR = ‘1’ or PWR_MODE = ‘01’ (transition through STARTUP mode)

7

6

5

4

3

2

1

0

Bits

DAC_TC2X_A

W−0

DAC_TCM_A

DAC_TIMER_A

W−0

Reset

W−0

Bit [7] If this bit is set, in Turbo mode dac_timer * 2 value is loaded into the DAC timer. The glide always sets the step delay

to dac_timer value independent of this bit.

Bit [6:5] It defines the multiplication factor of timer extension when the turbo−down value is below 4 V.

Bit [4:0] For the definition of dac_timer field, see Table 10.

NOTE: The read access to this register will return the active content post−trigger, not the shadow register.

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TCC−303

Register RFFE:

RFFE_REG_0x04

Address RFFE A[4:0]:

[0x04]

Reset Source: nreset_dig or SWR = ‘1’ or PWR_MODE = ‘01’ (transition through STARTUP mode)

7

6

5

4

3

2

1

0

Bits

DAC_TC2X_B

W−0

DAC_TCM_B

DAC_TIMER_B

W−0

Reset

W−0

Bit [7] If this bit is set, in Turbo mode dac_timer * 2 value is loaded into the DAC timer. The glide always sets the step delay

to dac_timer value independent of this bit.

Bit [6:5] Defines the multiplication factor of timer extension when the turbo−down value is below 4 V

Bit [4:0] For definition of dac_timer field, see Table 10.

NOTE: The read access to this register will return the active content post−trigger, not the shadow register.

Register RFFE:

RFFE_REG_0x05

Address RFFE A[4:0]:

[0x05]

Reset Source: nreset_dig or SWR = ‘1’ or PWR_MODE = ‘01’ (transition through STARTUP mode)

7

6

5

4

3

2

1

0

Bits

DAC_TC2X_C

W−0

DAC_TCM_C

DAC_TIMER_C

W−0

Reset

W−0

Bit [7] If this bit is set, in Turbo mode dac_timer * 2 value is loaded into the DAC timer. The glide always sets the step delay

to dac_timer value independent of this bit.

Bit [6:5] Defines the multiplication factor of timer extension when the turbo−down value is below 4 V

Bit [4:0] For definition of dac_timer field, see Table 10.

NOTE: The read access to this register will return the active content post−trigger, not the shadow register.

Register RFFE:

RFFE_REG_0x06

Address RFFE A[4:0]:

0x06

Reset Source: nreset_dig or SWR = ‘1’ or PWR_MODE = ‘01’ (transition through STARTUP mode)

7

6

5

4

3

2

1

0

Bits

GL_A

W−0

DAC A value [6:0]

W−0

Reset

W−0

Bit [7] If the GL_A=1, a non−zero value in DAC timer in starts a glide. If GL_A =0 and the DAC_TIMER_A is not zero, Turbo

is started with the new DAC A value.

NOTE: The read access to this register will return the active content post−trigger, not the shadow register. The DAC value read−back is

not the actual analog drive, it is the target level.

Register RFFE:

RFFE_REG_0x07

Address RFFE A[4:0]:

0x07

Reset Source: nreset_dig or SWR = ‘1’ or PWR_MODE = ‘01’ (transition through STARTUP mode)

7

6

5

4

3

2

1

0

Bits

GL_B

W−0

DAC B value [6:0]

W−0

Reset

W−0

Bit [7] If the GL_B=1, a non−zero value in DAC timer in starts a glide. If GL_B =0 and the DAC_TIMER_B is not zero, Turbo

is started with the new DAC B value.

NOTE: The read access to this register will return the active content post−trigger, not the shadow register. The DAC value read−back is

not the actual analog drive, it is the target level.

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20

TCC−303

Register RFFE:

RFFE_REG_0x08

Address RFFE A[4:0]:

0x08

Reset Source: nreset_dig or SWR = ‘1’ or PWR_MODE = ‘01’ (transition through STARTUP mode)

7

6

5

4

3

2

1

0

Bits

GL_C

W−0

DAC C value [6:0]

W−0

Reset

W−0

Bit [7] If the GL_C=1, a non−zero value in DAC timer in starts a glide. If GL_C =0 and the DAC_TIMER_C is not zero, Turbo

is started with the new DAC C value.

NOTE: The read access to this register will return the active content post−trigger, not the shadow register. The DAC value read−back is

not the actual analog drive, it is the target level.

Register RFFE:

RFFE_REG_0x09

Address RFFE A[4:0]:

0x09

Reset Source: nreset_dig or SWR = ‘1’ or PWR_MODE = ‘01’ (transition through STARTUP mode)

7

6

5

4

3

2

1

0

Bits

spare

U−0

spare

U−0

spare

U−0

spare

U−0

spare

U−0

spare

U−0

spare

U−0

RFFE_RDM

W−0

Reset

Bit [0] this bit defines the read capture edge internal to the chip. If 1, the read data is released at the falling edge of the RFFE

clock. In a system with very heavy load and 26 MHz speed, this bit can be set to gain some time .For speeds below full−speed

and light load, it is recommended to keep this bit cleared to switch to rising edge read data release.

Register RFFE:

RFFE_USID_1

Address RFFE A[4:0]:

0x18

Reset Source: nreset_dig or SWR = ‘1’ or PWR_MODE = ‘01’ (transition through STARTUP mode)

7

6

5

MPN9 (2)

0

4

MPN8 (2)

1

3

2

1

0

Bits

Reserved (2)

USID3 (1)

W−0

USID2 (1)

W−1

USID1 (1)

W−1

USID0 (1)

W−1

Reset

0

USID = Unique Slave Identifier Register

1. USID field can be changed by:

♦ MIPI−RFFE broadcast messages when USID field within the Register Write Command is 0b0000

♦ MIPI−RFFE individual messages when USID field within the Register Write Command equal with content of

RFFE_REG_0x18[3:0]

2. In the sequence of writing USID field, the upper [7:4] must match the value 0b0001 hardcoded in the RFFE register

0x18

NOTE: USID_1 value is NOT retained during SHUTDOWN power mode.

Register RFFE:

RFFE_USID_2

Address RFFE A[4:0]:

0x19

Reset Source: nreset_dig or SWR = ‘1’ or PWR_MODE = ‘01’ (transition through STARTUP mode)

7

6

5

MPN9 (2)

0

4

MPN8 (2)

1

3

2

1

0

Bits

Reserved (2)

USID3 (1)

W−0

USID2 (1)

W−1

USID1 (1)

W−1

USID0 (1)

W−1

Reset

0

USID = Unique Slave Identifier Register

1. USID field can be changed by:

♦ MIPI−RFFE broadcast messages when USID field within the Register Write Command is 0b0000

♦ MIPI−RFFE individual messages when USID field within the Register Write Command equal with content of

RFFE_REG_0x19[3:0]

2. In the sequence of writing USID field, the upper [7:4] must match the value 0b0001 hardcoded in the RFFE register

0x19

NOTE: USID_2 value is NOT retained during SHUTDOWN power mode.

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21

TCC−303

Register RFFE:

RFFE_STATUS

Address RFFE A[4:0]:

0x1A

Reset Source: nreset_dig or SWR = ‘1’ or PWR_MODE = ‘01’ (transition through STARTUP mode)

7

6

5

4

3

2

1

0

Bits

SWR

W−0

CFPE

R−0

CLE

R−0

AFPE

R−0

DFPE

R−0

RURE

R−0

WURE

R−0

BGE

R−0

Reset

SWR Soft−Reset MIPI−RFFE registers

Write ‘1’ to this bit to reset all the MIPI−RFFE registers, except RFFE_PM_TRIG, RFFE_GROUP_SID, RFFE_USID_0,

RFFE_USID_1 and RFFE_USID_2.

This bit will always Read−back ‘0’.

The soft reset occurs in the last clock cycle of the MIPI−RFFE frame which Writes ‘1’ to this bit.

Right immediately after this frame, all the MIPI−RFFE registers have the reset value and are ready to be reprogrammed as

desired.

The OTP duplicated registers below the address 0x1F are reset to the values written in OTP.

RFFE_STATUS Bits [6:0] are set ‘1’ by hardware to flag when a certain condition is detected, as described below.

RFFE_STATUS Bits [6:0] cannot be written, but it is cleared to ‘0’ under following conditions:

♦ Hardware Self−reset is applied after RFFE_STATUS is READ

♦ When SWR is written ‘1’

♦ When power mode transitions through STARTUP mode ‘01’

♦ After Power−up Reset

CFPE

1: Command frame with parity error received.

On the occurrence of this error, the slave will ignore the entire Command Sequence

CLE

1: Incompatible command length, due to unexpected SSC received before command length to be completed.

On the occurrence of this error, the slave will accept Write data up to the last correct and complete frame.

When MIPI−RFFE multi−byte Read command is detected, the slave will always replay with an extended

Read command of length of one byte.

AFPE

1: Address frame with parity error received.

On the occurrence of this error, the slave will ignore the entire Command Sequence

DFPE

1: Data frame with parity error received.

On the occurrence of this error, the slave will ignore only the erroneous data byte (s)

RURE

1: Read of non−existent register was detected.

On the occurrence of this error, the slave will not respond to the Read command frame. It will keep the bus idle.

WURE

1: Write to non−existent register was detected.

On the occurrence of this error, the slave discards data being written, and on the next received frame, proceeds as normal

BGE

1: Read using the Broadcast ID was detected

On the occurrence of this error, the slave will ignore the entire Command Sequence

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TCC−303

Register RFFE:

RFFE_GROUP_SID

Address RFFE A[4:0]:

0x1B

Reset Source: nreset_dig or PWR_MODE = ‘01’ (transition through STARTUP mode)

7

Reserved

0

6

Reserved

0

5

Reserved

0

4

Reserved

0

3

2

1

0

Bits

GSID[3]

W−0

GSID[2]

W−0

GSID[1]

W−0

GSID[0]

W−0

Reset

GSID = Group Slave Identifier Register

NOTE: The GSID [3:0] field can be written directly by messages using USID_0, USID_1 or USID_2.

NOTE: GSID value is NOT retained during SHUTDOWN power mode.

NOTE: GSID value is not affected by SWR bit from RFFE_STATUS register

NOTE: Frames using slave address = GSID, can write only to RFFE_PM_TRIG [7:6] and [2:0].

NOTE: RFFE READ frames containing GSID will be ignored

Register RFFE:

RFFE_PM_TRIG

Address RFFE A[4:0]:

0x1C

Reset Source: nreset_dig or PWR_MODE = ‘01’ (transition through STARTUP mode)

7

6

5

4

3

2

1

0

Bits

Power Mode

(Note 7)

Trigger Mask 2

(Notes 4, 5, 6)

Trigger Mask 1

(Notes 4, 5, 6)

Trigger Mask 0

(Notes 4, 5, 6)

Trigger 2

(Note 7)

Trigger 1

(Note 7)

Trigger 0

(Note 7)

Reset

W−0

W−1

W−0

4. The Trigger Mask 2 (bit [5]) can be changed, either set or cleared, only with an individual message using USID_2. The Trigger Mask 1 (bit

[4]) can be changed, either set or cleared, only with an individual message using USID_1. The Trigger Mask 0 (bit [3]) can be changed, either

set or cleared, only with an individual message using USID_0.

5. During broadcast MIPI−RFFE accesses using Broadcast ID or GSID, Trigger bits [2:0] are masked by the pre−existent setting of Trigger Mask

bits [5:3].

6. During Individual MIPI−RFFE accesses, Trigger bits [2:0] are masked by the incoming Trigger Mask bits [5:3] within the same write message

to RFFE_PM_TRIG register according to the DAC DUR configurations.

7. Power mode field bits [7:6] and Triggers bits [2:0] can be changed by either MIPI−RFFE broadcast messages (with GSID or Broadcast ID

slave address). The power mode can be changed by all USID accesses. The trigger bits can be set by individual messages when slave

address fields within the Register Write Command is are equal to their corresponding control USIDs.

NOTE: None of the 8 bits of RFFE_PM_TRIG register bits are affected by SWR bit from RFFE_STATUS register. The default reset values

of the Trigger Masks are set to ‘1’ violating the RFFE spec, but the trigger at DAC write is requested to be the default

Bit [7:6]: Power Mode

00: ACTIVE mode, defined by following hardware behavior:

♦ Boost Control active, VHV set by Digital Interface

♦ Vout A, B, C enabled and controlled by Digital Interface

01: STARTUP mode, defined by following hardware behavior:

♦ Boost Control active, VHV set by Digital Interface

♦ Vout A, B, C disabled

10: LOW POWER mode is defined by following hardware behavior:

♦ Digital interface is active, while all other circuits are in low power mode

11: Reserved (State of hardware does not change)

Bit 5: Mask trigger 2 (only USID_2 write access)

0:Trigger 2 not masked. The DACs, which are configured in their DUR to be controlled by USID_2 have their active registers

updated after the Trigger 2 is written a value of 1.

1:Trigger 2 is masked. The DACs, which are configured in their DUR to be controlled by USID_2 have their active registers

updated as soon as their new DAC values are written in (default).

Bit 4: Mask trigger 1 (only USID_1 write access)

0:Trigger 1 not masked. The DACs, which are configured in their DUR to be controlled by USID_1 have their active registers

updated after the Trigger 1 is written a value of 1.

1:Trigger 2 is masked. The DACs, which are configured in their DUR to be controlled by USID_1 have their active registers

updated as soon as their new DAC values are written in (default).

Bit 3: Mask trigger 0 (only USID_0 write access)

0:Trigger 0 not masked. The DACs, which are configured in their DUR to be controlled by USID_0 have their active registers

updated after the Trigger 0 is written a value of 1.

1:Trigger 2 is masked. The DACs, which are configured in their DUR to be controlled by USID_0 have their active registers

updated as soon as their new DAC values are written in (default).

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TCC−303

Bit 2: Trigger 2 (USID_2 or broadcast write access)

Write 1 to this bit, to move data in DACs, which are configured in their DUR under USID_2 control, from shadow registers

into active registers. This trigger can be masked by bit 5. The read back of this field returns DACC pending trigger status

(from immediate or SW trigger).

Bit 1: Trigger 1 (USID_1 or broadcast write access)

Write 1 to this bit, to move data in DACs, which are configured in their DUR under USID_1 control, from shadow registers

into active registers. This trigger can be masked by bit 4. The read back of this field returns DACB pending trigger status

(from immediate or SW trigger).

Bit 0: Trigger 0 (USID_0 or broadcast write access)

Write 1 to this bit, to move data in DACs, which are configured in their DUR under USID_0 control, from shadow registers

into active registers. This trigger can be masked by bit 3. The read back of this field returns DACA pending trigger status

(from immediate or SW trigger).

Register RFFE:

RFFE_PRODUCT_ID

Address RFFE A[4:0]:

0x1D

Reset Source: N/A

7

PID7

0

6

PID6

0

5

PID5

0

4

PID4

1

3

PID3

0

2

PID2

0

1

PID1

0

Bits

PID0

0

Reset

Bits [7:1] are hardcoded in ASIC

Bit [0] depends on version – 0 for TCC−303A

PRODUCT Family ID History:

TCC−103A

TCC−106A

TCC−202A

TCC−206A

TCC−303A

0

1

0

1

0

1

0

1

0

1

0

IDB0 pin

0

Register RFFE:

RFFE_MANUFACTURER_ID

Address RFFE A[4:0]:

0x1E

Reset Source: N/A

7

6

MPN6

0

5

MPN5

1

4

MPN4

0

3

MPN3

1

2

1

0

MPN0

0

Bits

MPN7

0

MPN2

1

MPN1

1

Reset

The 10 MPN bits (MPN0 to MPN9 partially residing under USID registers) are manufacturing ID bits unique to

ON Semiconductor.

Register RFFE:

RFFE_USID_0 (default)

Address RFFE A[4:0]:

0x1F

Reset Source: nreset_dig or SWR = ‘1’ or PWR_MODE = ‘01’ (transition through STARTUP mode)

7

6

5

MPN9 (2)

0

4

MPN8 (2)

1

3

2

1

0

Bits

Reserved (2)

USID3 (1)

W−0

USID2 (1)

W−1

USID1 (1)

W−1

USID0 (1)

W−1

Reset

0

USID = Unique Slave Identifier Register

1. USID field can be changed by:

♦ MIPI−RFFE broadcast messages when USID field within the Register Write Command is 0b0000

♦ MIPI−RFFE individual messages when USID field within the Register Write Command equal with content of

RFFE_REG_0x1F[3:0]

2. In the sequence of writing USID field, the upper [7:4] must match the value 0b0001 hardcoded in the RFFE register

0x1F

NOTE: USID value is NOT retained during SHUTDOWN power mode.

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24

TCC−303

Register 0 Write Command Sequence

The Command Sequence starts with an SSC which is followed by the Register 0 Write Command Frame. This Frame contains

the Slave address, a logic one, and the seven bit word that will be written to Register 0. The Command Sequence is depicted

below.

Figure 14. Register 0 Write Command Sequence

Table 16. RFFE COMMAND FRAME FOR REGISTER 0 WRITE COMMAND SEQUENCE

Description

SSC

Command Frame

DAC Configuration

1

0

SA [3,0]

1

0

P

BP

Single Register Write Command Sequence

The Write Register command sequence may be used to access each register individually (addresses 0−31).

Figure 15. Single Register Write Command Sequence

Table 17. RFFE COMMAND FRAME for REGISTER WRITE COMMAND SEQUENCE for DACS LOADING PROCEDURE

Description

SSC

Command Frame

Data Frame

GL_A & DAC_A [6:0]

GL_B & DAC_B [6:0]

GL_C & DAC_C [6:0]

BP

Register Write DAC A

Register Write DAC B

Register Write DAC C

1

0

SA [3, 0]

0

1

0

1

0

1

0

1

0

P

1

This sequence can be used for Read/Write procedure for some other purposes as shown on the following table:

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TCC−303

Table 18. OTHER RFFE COMMAND SEQUENCES

Description

Active Mode

Startup Mode

Low Power

SSC

Command Frame

Data Frame

BP

1

0

SA [3, 0]

0

1

0

1

0

1

0

1

0

1

P

0

1

0

1

0

1

0

x

0

1

0

x

1

0

1

x

0

1

x

0

1

x

P

1

x

Reserved

x

0

x

Product ID

0/1

0

Manufacturer ID

Manufacturer USID

1

USID

Extended Register Write Command Sequence

In order to access more than one register in one sequence

this message could be used. Most commonly it will be used

for loading three DAC registers at the same time. The four

LSBs of the Extended Register Write Command Frame

determine the number of bytes that will be written by the

Command Sequence. A value of 0b0000 would write one

byte and a value of 0b1111 would write sixteen bytes.

If more than one byte is to be written, the register address

in the Command Sequence contains the address of the first

extended register that will be written to and the Slave’s local

extended register address shall be automatically

incremented by one for each byte written up to address 0x1F,

starting from the address indicated in the Address Frame.

Figure 16. Extended Register Write Command Sequence

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TCC−303

Table 19. RFFE Command Frame for Extended Register Write Command Sequence for DACs Loading Procedure

Bus

Park

Description

SSC

Command Frame

Address Frame

Data Frame

Extended

Register

1

0

SA [3, 0]

0

1

0

P

0

1

0

P

GL_A

P

GL_B &

DAC_B

[6:0]

P

GL_C &

DAC_C

P

BP

DAC_A

[6:0]

Write DAC

A&B&C

Extended or Single Register Read Command Sequence

MIPI−RFFE Read operation can access any register from address 0x00 to 0x1F without the need to enter testkey.

Both single Register Read and Extended Register Read commands are supported.

Figure 17. Single Register Read Command Sequence

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TCC−303

Figure 18. Extended Register Read Command Sequence

Changing USIDs

Change USID_1

Changing USID is according to MIPI RFFE

specifications. Same Manufacturer_ID and Product_ID

apply for USID_0/_1/_2. Note that USID can be changed

with broadcast commands, or commands targeting that

particular USID. For example to change USID_0, broadcast

commands or commands addressing USID_0 can be used.

• RFFE_WRITE_REG 0x1D [0x10 + OTP[31]]

• RFFE_WRITE_REG 0x1E 0x2E

• RFFE_WRITE_REG 0x18 0x1Z, where Z is the new

USID_1 value

Change USID_2

Change USID_0

• RFFE_WRITE_REG 0x1D [0x10 + OTP[31]]

• RFFE_WRITE_REG 0x1E 0x2E

• RFFE_WRITE_REG 0x1D [0x10 + OTP[31]]

• RFFE_WRITE_REG 0x1E 0x2E

• RFFE_WRITE_REG 0x19 0x1Z, where Z is the new

• RFFE_WRITE_REG 0x1F 0x1Z, where Z is the new

USID_2 value

USID_0 value

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28

TCC−303

EXAMPLE DEVICE OPERATION

Device Setup

Change DACs with Glide

1. Enable all three DACs – Write 0x07 to Register

• Keep DACA voltage at 6.8 V; Glide enabled – Write

0xA4 to Register 0x06 (Total Glide duration is

28 ms*256 ms = 7168 ms); No output change since

DAC_OLD = DAC_NEW

0x00

2. Change VHV voltage to 28 V (Default 24 V) –

Write 0xDF to Register 0x02

• Change DACB voltage to 16.4 V; Glide enabled –

Write 0xD7 to Register 0x07 (Total Glide duration is

20 ms*256 ms = 5120 ms); Transitions from 12 V to 16.4

V over 5.12 ms

Change DACs

• Change DACA voltage to 6.8 V; no Glide – Write 0x24

to Register 0x06

• Change DACB voltage to 12.0 V; no Glide – Write

0x40 to Register 0x07

• Change DACC Voltage to 20.5 V; Glide enabled –

Write 0xED to Register 0x08 (Total Glide Duration is

42 ms*256 ms = 10752 us); Transitions from 0.9 V to

20.5 V over 10.75 ms

• Change DACC voltage to 0.9 V; no Glide – Write 0x05

to Register 0x08

Setup Glide

NOTE: Any sequential registers (Eg. 0x03−0x08, as

mentioned in Setup Glide and Change DACs

with Glide sections) can be written with a single

extended MIPI write, rather than individual

write commands.

• Set DACA Glide step duration to 28 ms – Write 0x0E to

Register 0x03

• Set DACB Glide step duration to 20 ms – Write 0x0A to

Register 0x04

• Set DACC Glide step duration to 42 ms – Write 0x15 to

Register 0x05

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29

TCC−303

Following picture shows TCC−303 and all the necessary external components

Figure 19. TCC−303 with External Components

Table 20. RECOMMENDED EXTERNAL BOM

Component

Description

Boost Supply Capacitor, 10 V

Boost Inductor

Nominal Value

1 mF

Package

0402

Recommended P/N

TDK: C1005X5R1A105K

C

BOOST

L

15 mH

0603

TDK: VLS2010ET−150M, Sunlord

SPH201610H150MT

R

Filtering resistor, 5%

3.3 Ws

100 nF

1 mF

0402

0201

Vishay : CRCW04023R30JNED

Murata: GRM033R61A104ME15D

TDK: C1005X5R1A105K

FILT

C

V

Supply Decoupling, 10 V

VIO

IO

C

Supply Decoupling, 10 V

0402

VDDA

VREG

VDDA

VREG

C

220 nF

47 nF

0201

TDK: C0603X5R1A224M

C

Boost Tank Capacitor, 50 V

Decoupling Capacitor, 50 V (Note 8)

Rectifying Schottky Diode

1005

Murata: GRM155C71H473KE19

Murata: GRM0335C1H101JD01D

HV

dacA,B,C

C

100 pF

0201

D

SOD−923

ON Semiconductor: NSR0240P2T5G,

NSR0340HT1G (Note 9), RB521S030T1

(Note 9)

SCH

8. Recommended in noise reduction only− not essential but place next to PTIC if used

9. These devices have not been fully tested; performance cannot be guaranteed.

Table 21. ORDERING INFORMATION

†

Device

Marking

T33a

Package

Shipping

TCC−303A−RT

TCC−303B−RT

WLCSP12

(Pb−Free)

3000 / Tape & Reel

T33b

†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging

Specifications Brochure, BRD8011/D.

ASSEMBLY INSTRUCTIONS

Note: It is recommended that under normal circumstances, this device and associated components should be located in a

shielded enclosure.

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30

MECHANICAL CASE OUTLINE

PACKAGE DIMENSIONS

WLCSP12, 1.376x1.025x0.68

CASE 567MW

ISSUE A

SCALE 4:1

DATE 07 JUN 2017

NOTES:

1. DIMENSIONING AND TOLERANCING PER

ASME Y14.5M, 1994.

2. CONTROLLING DIMENSION: MILLIMETERS.

3. COPLANARITY APPLIES TO THE SPHERICAL

CROWNS OF THE SOLDER BALLS.

E

A

B

D

PIN A1

REFERENCE

MILLIMETERS

A3

BACKSIDE

COATING

DIM

A

A1

A2

A3

b

MIN

−−−

0.13

0.38 REF

0.025 REF

MAX

0.68

0.19

A2

2X

0.03

C

0.17

0.23

2X

0.03

C

TOP VIEW

D

E

e

1.376 BSC

1.025 BSC

0.35 BSC

DETAIL A

A

GENERIC

MARKING DIAGRAM*

0.10

C

XXXX

ALYWG

G

0.05

A1

SEATING

PLANE

C

NOTE 3

SIDE VIEW

A

L

Y

= Assembly Location

= Wafer Lot

= Year

12X

b

e

0.05

0.03

C

A

B

D

W

= Work Week

e/2

C

G

= Pb−Free Package

(Note: Microdot may be in either location)

C

B

A

*This information is generic. Please refer to

device data sheet for actual part marking.

Pb−Free indicator, “G” or microdot “ G”,

may or may not be present. Some products

may not follow the Generic Marking.

1

2

3

BOTTOM VIEW

RECOMMENDED

SOLDERING FOOTPRINT*

A1

PACKAGE

OUTLINE

12X

0.17

0.35

PITCH

0.35

PITCH

DIMENSIONS: MILLIMETERS

*For additional information on our Pb−Free strategy and soldering

details, please download the ON Semiconductor Soldering and

Mounting Techniques Reference Manual, SOLDERRM/D.

Electronic versions are uncontrolled except when accessed directly from the Document Repository.

Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.

DOCUMENT NUMBER:

DESCRIPTION:

98AON06764G

WLCSP12, 1.376X1.025X0.68

PAGE 1 OF 1

ON Semiconductor and

are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.

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1


型号：	TCC-303
厂家：	ONSEMI
描述：	Three-Output PTIC Control IC
文件：	总32页 (文件大小：583K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

TCC-303 [ONSEMI]

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