TCP-3082N-QT [ONSEMI]

8.2 pF Passive Tunable Integrated Circuits;


型号：	TCP-3082N-QT
厂家：	ONSEMI
描述：	8.2 pF Passive Tunable Integrated Circuits
文件：	总7页 (文件大小：240K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

TCP-3082N

8.2 pF Passive Tunable

Integrated Circuits (PTIC)

Introduction

ON Semiconductor’s PTICs have excellent RF performance and

power consumption, making them suitable for any mobile handset or

radio application. The fundamental building block of our PTIC

product line is a tunable material called ParaScant, based on Barium

Strontium Titanate (BST). PTICs have the ability to change their

capacitance from a supplied bias voltage generated by the Control IC.

The 8.2 pF PTICs are available as wafer-level chip scale packages

(WLCSP) and in QFN packages for easy mounting directly on printed

circuit boards.

http://onsemi.com

WLCSP12

1.18x0.72

QFN6

1.6x1.2

CASE 567KE

CASE 485DX

Key Features

• High Tuning Range and Operation up to 20 V

• Usable Frequency Range: from 700 MHz to 2.4 GHz

• High Quality Factor (Q) for Low Loss

MARKING DIAGRAM

• High Power Handling Capability

X.XN

• Compatible with PTIC Control IC TCC-103

• WLCSP Package: 0.722 x 1.179 x 0.611 mm (12 pillar)

• QFN Package: 1.200 x 1.600 x 0.950 mm

• QFN: MSL−2 Moisture Sensitivity Level (per J−STD−020)

• These devices are Pb−Free and RoHS Compliant

X.X = 8.2

= Normal Tuning

FUNCTIONAL BLOCK DIAGRAM

Typical Applications

• Multi-band, Multi-standard, Advanced and Simple Mobile Phones

• Tunable Antenna Matching Networks

• Tunable RF Filters

PTIC

RF1

RF2

• Active Antennas

Bias

PTIC Functional Block Diagram

ORDERING INFORMATION

†

Device

Package

Shipping

TCP−3082N−DT

WLCSP12

(Pb−Free)

4000 Units /

7” Reel

TCP−3082N−QT

QFN6

(Pb−Free)

8000 Units /

13“ Reel

†For information on tape and reel specifications,

including part orientation and tape sizes, please

refer to our Tape and Reel Packaging Specifications

Brochure, BRD8011/D.

Publication Order Number:

October, 2014 − Rev. 0

TCP−3082N/D

TCP−3082N

TYPICAL SPECIFICATIONS

Representative Performance Data at 255C

Table 1. PERFORMANCE DATA

Parameter

Min

2.0

Typ

Max

Units

Operating Bias Voltage

Capacitance (V

= 2 V)

7.05

2.23

3.00

2.80

8.20

2.34

3.50

3.30

9.02

2.46

4.05

4.0

bias

= 20 V)

Tuning Range (2 V - 20 V)

Tuning Range (20 V - 2 V)

Leakage Current (WLCSP)

Operating Frequency

700

2400

MHz

Quality Factor @ 700 MHz, 10 V

100

Quality Factor @ 2.4 GHz, 10 V

[1,3]

IP3 (V

= 2 V)

dBm

bias

[1,3]

IP3 (V

= 20 V)

[2,3]

2nd Harmonic (V

= 2 V)

-75

-85

-40

-70

bias

[2,3]

= 20 V)

[2,3]

3rd Harmonic (V

= 2 V)

[2,3]

= 20 V)

[4]

Transition Time (Cmin ³ Cmax)

Transition Time (Cmax ³ Cmin)

1. f = 850 MHz, f = 860 MHz, Pin 25 dBm/Tone

2. 850 MHz, Pin +34 dBm

3. IP3 and Harmonics are measured in the shunt configuration in a 50 W environment

4. RF1 and RF2 are both connected to DC ground

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TCP−3082N

Representative performance data at 255C for 8.2 pF WLCSP Package

Figure 1. Capacitance

Figure 2. Harmonic Power

Figure 3. IP3

Figure 4. Q

Table 2. ABSOLUTE MAXIMUM RATINGS

Parameter

Rating

Units

dBm

Input Power

+40

+25 (Note 5)

Bias Voltage

Operating Temperature Range

Storage Temperature Range

ESD − Human Body Model

−30 to +85

°C

−55 to +125

°C

Class 1A JEDEC HBM Standard (Note 6)

Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the

Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect

device reliability.

5. WLCSP: Recommended Bias Voltage not to exceed 20 V

6. Class 1A defined as passing 250 V, but may fail after exposure to 500 V ESD pulse

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TCP−3082N

ASSEMBLY CONSIDERATIONS AND REFLOW PROFILE

Molding

The following assembly considerations should be observed:

The PTIC die is compatible for over-molding or

under-fill.

Cleanliness

These chips should be handled in a clean environment.

Electro-static Sensitivity

ON Semiconductor’s PTICs are ESD Class 1A sensitive.

The proper ESD handling procedures should be used.

Mounting

The WLCSP PTIC is fabricated for Flip Chip solder

mounting. Connectivity to the RF and Bias terminations on

the PTIC die is established through copper pillar posts

(53 mm nominal height) topped with lead-free SAC351

solder caps (28 mm nominal height). The PTIC die is

RoHS-compliant and compatible with lead-free soldering

profile.

Post-reflow Cleaning

Use of ultrasonic cleaning is not recommended for

pillared devices as it may lead to premature fatigue failure

of the pillars.

Figure 5. Reflow Profile

ORIENTATION OF THE PTIC FOR OPTIMUM LOSSES

ANT

When configuring the PTIC in your specific circuit

RF1

(PTIC Pad)

design, at least one of the RF terminals must be connected

to DC ground. If minimum transition times are required, DC

ground on both RF terminals is recommended. To minimize

losses, the PTIC should be oriented such that RF2 is at the

lower RF impedance of the two RF nodes. A shunt PTIC, for

example, should have RF2 connected to RF ground.

RF2

(PTIC Pad)

Bias

Figure 6. PTIC Orientation Functional Block

Diagram

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TCP−3082N

PART NUMBER DEFINITION

Example: TCP−3082N−DT

TCP

Product

Family

Process Status

Process

Capacitor

Value

Tuning

Package /

Format

Packing

Generation

“blank” =

Production

10 = Gen 1.0

30 = Gen 3.0

T = T&R

27 = 2.7 pF

33 = 3.3 pF

39 = 3.9 pF

47 = 4.7 pF

56 = 5.6 pF

68 = 6.8 pF

82 = 8.2 pF

TCP

N = Normal

H = High

D = WLCSP

Q = QFN

X = Pilot

Production

S =

Special/Custom

P = Prototype

Table 3. PART NUMBERS

Capacitance

2 V

8.20

20 V

2.34

Part Number

TCP-3082N-DT

Package

12-Pillar WLCSP

6-Pin QFN

TCP-3082N-QT

http://onsemi.com

TCP−3082N

PACKAGE DIMENSIONS

WLCSP12, 1.18x0.72

CASE 567KE

ISSUE O

NOTES:

1. DIMENSIONING AND TOLERANCING PER

ASME Y14.5M, 1994.

2. CONTROLLING DIMENSION: MILLIMETERS.

3. COPLANARITY APPLIES TO SPHERICAL

CROWNS OF SOLDER BALLS.

PIN A1

REFERENCE

^10Xb1

^10Xb

0.05

0.03

MILLIMETERS

A B

DIM

MIN

0.590

0.069

0.079

0.044

MAX

0.639

0.093

0.129

0.094

DETAIL A

0.05

1.179 BSC

0.722 BSC

0.150 BSC

0.159 BSC

0.300 BSC

0.460 BSC

0.425 BSC

TOP VIEW

^2Xb

^2Xb1

0.05

A B

0.06

0.03

RECOMMENDED

SOLDERING FOOTPRINT*

DETAIL B

0.05

SIDE VIEW

SEATING

PLANE

0.57

NOTE 3

0.13

0.15

DETAIL A

PACKAGE

OUTLINE

0.52

0.51

0.75

0.13

0.59

DIMENSIONS: MILLIMETERS

*For additional information on our Pb−Free strategy and soldering

details, please download the ON Semiconductor Soldering and

Mounting Techniques Reference Manual, SOLDERRM/D.

DETAIL B

BOTTOM VIEW

http://onsemi.com

TCP−3082N

PACKAGE DIMENSIONS

QFN6 1.6x1.2, 0.5P

CASE 485DX

ISSUE O

NOTES:

1. DIMENSIONING AND TOLERANCING PER

ASME Y14.5M, 1994.

2. CONTROLLING DIMENSION: MILLIMETERS.

MILLIMETERS

DIM

MIN

0.90

0.00

0.15 REF

0.22

1.60 BSC

1.20 BSC

0.50 BSC

MAX

1.00

0.05

DETAIL A

ALTERNATE TERMINAL

CONSTRUCTIONS

PIN ONE

IDENTIFIER

0.28

0.05

EXPOSED Cu

MOLD CMPD

0.39

−−−

0.46

0.15

0.05

TOP VIEW

DETAIL B

0.10

ALTERNATE

CONSTRUCTIONS

0.05

RECOMMENDED

MOUNTING FOOTPRINT*

SEATING

PLANE

SIDE VIEW

0.60

6X b

PACKAGE

OUTLINE

DETAIL A

0.10

0.03

1.40

0.30

0.50

PITCH

DIMENSIONS: MILLIMETERS

*For additional information on our Pb−Free strategy and soldering

details, please download the ON Semiconductor Soldering and

Mounting Techniques Reference Manual, SOLDERRM/D.

BOTTOM VIEW

ParaScan is a trademark of Paratek Microwave, Inc.

ON Semiconductor and

are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC owns the rights to a number of patents, trademarks,

copyrights, trade secrets, and other intellectual property. A listing of SCILLC’s product/patent coverage may be accessed at www.onsemi.com/site/pdf/Patent−Marking.pdf. SCILLC

reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any

particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without

limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications

and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC

does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for

surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where

personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and

its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly,

any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture

of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.

PUBLICATION ORDERING INFORMATION

LITERATURE FULFILLMENT:

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USA/Canada

Europe, Middle East and Africa Technical Support:

Phone: 421 33 790 2910

Japan Customer Focus Center

Phone: 81−3−5817−1050

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Order Literature: http://www.onsemi.com/orderlit

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For additional information, please contact your local

Sales Representative

TCP−3082N/D

http://onsemi.com

TCP-3082N-QT [ONSEMI]

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