TCP-5068UB-DT [ONSEMI]
6.8 pF Passive Tunable Integrated Circuits (PTIC);
| 型号： | TCP-5068UB-DT |
| 厂家： | 
ONSEMI |
| 描述： | 6.8 pF Passive Tunable Integrated Circuits (PTIC) |
| 文件： | 总7页 (文件大小：229K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
TCP-5068UB
6.8 pF Passive Tunable
Integrated Circuits (PTIC)
Introduction
ON Semiconductor’s PTICs have excellent RF performance and
power consumption, making them suitable for any mobile handset or
radio application. The fundamental building block of our PTIC
product line is a tunable material called ParaScant, based on Barium
Strontium Titanate (BST). PTICs have the ability to change their
capacitance from a supplied bias voltage generated by the Control IC.
The 6.8 pF ultra−high tuning PTICs are available as wafer−level chip
scale packages (WLCSP).
www.onsemi.com
WLCSP6
1.097x0.622
CASE 567NZ
Key Features
• Ultra−High Tuning Range(5:1) and Operation up to 24 V
• Usable Frequency Range: from 700 MHz to 2.7 GHz
• High Quality Factor (Q) for Low Loss
MARKING DIAGRAM
HYW
• High Power Handling Capability
• Compatible with PTIC Control ICs from ON Semiconductor
• These devices are Pb−Free and RoHS Compliant
H
Y
= Specific Device Code
= Year
W
= Work Week
Typical Applications
• Multi−band, Multi−standard, Advanced and Simple Mobile Phones
• Tunable Antenna Matching Networks
• Tunable RF Filters
FUNCTIONAL BLOCK DIAGRAM
PTIC
• Active Antennas
RF1
RF2
Bias
PTIC Functional Block Diagram
ORDERING INFORMATION
†
Device
Package
Shipping
TCP−5068UB−DT WLCSP4
(Pb−Free)
4000 Units /
7” Tape & Reel
†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specifications
Brochure, BRD8011/D.
© Semiconductor Components Industries, LLC, 2016
1
Publication Order Number:
November, 2016 − Rev. 0
TCP−5068UB/D
TCP−5068UB
A1
A2
NC
DC Bias 1
B2
C2
B1
C1
RF1
RF1
RF2
RF2
Figure 1. PTIC Functional Block Diagram
(Top View)
Table 1. SIGNAL DESCRIPTIONS
Ball / Pad Number
Pin Name
DC Bias 1
RF2
Description
A1
B1
C1
A2
B2
C2
DC Bias Voltage
RF Output
RF2
RF Output
NC
Not Connected
RF Input
RF1
RF1
RF Input
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2
TCP−5068UB
TYPICAL SPECIFICATIONS
Representative Performance Data at 255C
Table 2. PERFORMANCE DATA
Parameter
Min
1.0
Typ
Max
24
Units
V
Operating Bias Voltage
Capacitance (V
Capacitance (V
= 2 V)
6.188
1.331
4.80
4.20
6.80
1.462
5.25
7.412
1.594
6.00
5.30
0.1
pF
bias
bias
= 24 V)
pF
Tuning Range (1 V − 24 V)
Tuning Range (2 V − 24 V)
4.65
Leakage Current (V
= 24 V)
mA
bias
Operating Frequency
700
2700
MHz
Quality Factor @ 700 MHz, 2 V (Note 5)
Quality Factor @ 700 MHz, 24 V (Note 5)
Quality Factor @ 2.4 GHz, 2 V (Note 5)
Quality Factor @ 2.7 GHz, 24 V (Note 5)
70
80
45
40
IP3 (V
IP3 (V
= 2 V) (Notes 1, 3 and 5)
= 24 V) (Notes 1, 3 and 5)
70
dB
dB
bias
bias
80
2nd Harmonic (V
2nd Harmonic (V
= 2 V) (Notes 2, 3 and 5)
= 24 V) (Notes 2, 3 and 5)
= 2 V) (Notes 2, 3 and 5)
= 24 V) (Notes 2, 3 and 5)
−70
−80
−45
−75
66
dBm
dBm
dBm
dBm
ms
bias
bias
bias
bias
3rd Harmonic (V
3rd Harmonic (V
Average Transition Time (Cmin ³ Cmax) (Notes 4
and 5)
Average Transition Time (Cmax ³ Cmin) (Notes 4
48
ms
and 5)
1. f = 850 MHz, f = 860 MHz, Pin 25 dBm/Tone
1
2
2. 850 MHz, Pin +34 dBm
3. IP3 and Harmonics are measured in the shunt configuration in a 50 W environment
4. RF and RF are both connected to DC ground
IN
OUT
5. Sample testing only. Average Transition Time for all start and stop voltage combinations between 2 V and 24 V is 50 ms.
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3
TCP−5068UB
Representative performance data at 255C for 6.8 pF WLCSP Package
Figure 2. Capacitance
Figure 3. Harmonic Power*
Figure 4. IP3*
Figure 5. Q*
*Data shown is representative only.
Table 3. ABSOLUTE MAXIMUM RATINGS
Parameter
Rating
+40
Units
dBm
V
Input Power
Bias Voltage
+30 (Note 6)
−30 to +85
−55 to +125
Operating Temperature Range
Storage Temperature Range
°C
°C
ESD − Human Body Model
Class 1B JEDEC HBM Standard (Note 7)
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
6. WLCSP: Recommended Bias Voltage not to exceed 24 V.
7. Class 1B defined as passing 500 V, but may fail after exposure to 1000 V ESD pulse.
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4
TCP−5068UB
ASSEMBLY CONSIDERATIONS AND REFLOW PROFILE
The following assembly considerations should be observed:
Cleanliness
These chips should be handled in a clean environment.
Electro−static Sensitivity
ON Semiconductor’s PTICs are ESD Class 1B sensitive.
The proper ESD handling procedures should be used.
Mounting
The WLCSP PTIC is fabricated for Flip Chip solder
mounting. Connectivity to the RF and Bias terminations on
the PTIC die is established through SAC305 solder balls
with 90 mm nominal height (65 mm to 115 mm height
variation). The PTIC die is RoHS−compliant and
compatible with lead−free soldering profile.
Molding
The PTIC die is compatible for over−molding or
under−fill.
Figure 6. Reflow Profile
ORIENTATION OF THE PTIC FOR OPTIMUM LOSSES
RF
ANT
When configuring the PTIC in your specific circuit
design, at least one of the RF terminals must be connected
to DC ground. If minimum transition times are required, DC
ground on both RF terminals is recommended. To minimize
losses, the PTIC should be oriented such that RF2 is at the
lower RF impedance of the two RF nodes. A shunt PTIC, for
example, should have RF2 connected to RF ground.
RF1
(PTIC Pad)
RF2
(PTIC Pad)
Bias
Figure 7. PTIC Orientation Functional Block
Diagram
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5
TCP−5068UB
PART NUMBER DEFINITION
Table 4. PART NUMBERS
Capacitance
Marking
Trace Code
YW**
2 V
24 V
Device ID
Part Number
Package*
TCP−5068UB−DT
6.80
1.462
H
6−bump WLCSP
*See PTIC package dimensions on following page.
**Refer to table below (Table 5) for YW trace code.
For information on device numbering and ordering codes, please download the Device Nomenclature technical note
(TND310/D) from www.onsemi.com.
Table 5. Two Digits Year and Work Week Date coding (YW) − In Process Product / Traceability Date Code Marking
Code
YW
Term
Definition
Two−character Alpha Code. Example: 2005, workweek 10 = GJ
Year and
Work Week
YEAR
2003
WORK
WEEK
CODE
YEAR
2004
WORK
WEEK
CODE
YEAR
2005
WORK
WEEK
CODE
1
CA
CZ
DA
DZ
1
EA
EZ
FA
FZ
1
GA
GZ
HA
HZ
26
27
52
26
27
52
26
27
52
2006
2009
2012
2015
1
IA
IZ
2007
2010
2013
2016
1
KA
KZ
LA
LZ
2008
2011
2014
2017
1
MA
MZ
NA
NZ
26
27
52
26
27
52
26
27
52
JA
JZ
1
PA
PZ
RA
RZ
1
SA
SZ
TA
TZ
1
UA
UZ
VA
VZ
26
27
52
26
27
52
26
27
52
1
WA
WZ
XA
XZ
1
YA
YZ
ZA
ZZ
1
AA
AZ
BA
BZ
26
27
52
26
27
52
26
27
52
1
CA
CZ
DA
DZ
1
EA
EZ
FA
FZ
1
GA
GZ
HA
HZ
26
27
52
26
27
52
26
27
52
For dates outside of the table: the first character of the code is incremented at the start of workweek 01 and workweek 27
each year. The second character begins with “A” in workweek 01 of each year and increments weekly. “A” follows “Z” to make
the code continuous.
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6
TCP−5068UB
PACKAGE DIMENSIONS
WLCSP6, 1.097x0.622
CASE 567NZ
ISSUE A
NOTES:
E
A
B
D
1. DIMENSIONING AND TOLERANCING PER
ASME Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS.
3. COPLANARITY APPLIES TO SPHERICAL
CROWNS OF SOLDER BALLS.
4. BACKSIDE TAPE APPLIED TO IMPROVE
PIN 1 MARKING.
PIN A1
REFERENCE
6X b1
6X b
0.05
0.03
C
C
A B
MILLIMETERS
DETAIL A
DIM
A
A1
A3
b
b1
D
E
MIN
0.295
0.065
NOM
0.335
0.090
0.025 REF
0.150
0.100
1.097
0.622
0.40 BSC
MAX
0.375
0.115
2X
0.05
0.05
C
NOTE 4
TAPE
2X
0.125
0.075
1.047
0.572
0.175
0.125
1.147
0.672
C
TOP VIEW
A3
DETAIL C
e
A
C
0.06
0.05
C
C
DETAIL C
A1
SEATING
PLANE
NOTE 3
SIDE VIEW
RECOMMENDED
SOLDERING FOOTPRINT*
e
0.40
e/2
DETAIL A
A1
e
PACKAGE
OUTLINE
C
B
A
0.40
PITCH
6X
0.20
1
2
DIMENSIONS: MILLIMETERS
BOTTOM VIEW
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
ParaScan is a trademark of Paratek Microwave, Inc.
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TCP−5068UB/D
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