TL431BVPG [ONSEMI]
Programmable Precision References; 可编程精密基准
| 型号： | TL431BVPG |
| 厂家： | 
ONSEMI |
| 描述： | Programmable Precision References |
| 文件： | 总18页 (文件大小：216K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
TL431, A, B Series,
NCV431A, B
Programmable
Precision References
The TL431, A, B integrated circuits are three−terminal
programmable shunt regulator diodes. These monolithic IC voltage
references operate as a low temperature coefficient zener which is
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TO−92 (TO−226)
LP SUFFIX
CASE 29
programmable from V to 36 V with two external resistors. These
ref
devices exhibit a wide operating current range of 1.0 mA to 100 mA
with a typical dynamic impedance of 0.22 W. The characteristics of
these references make them excellent replacements for zener diodes in
many applications such as digital voltmeters, power supplies, and op
amp circuitry. The 2.5 V reference makes it convenient to obtain a
stable reference from 5.0 V logic supplies, and since the TL431, A, B
operates as a shunt regulator, it can be used as either a positive or
negative voltage reference.
Pin 1. Reference
2. Anode
1
2
3
3. Cathode
PDIP−8
P SUFFIX
CASE 626
Features
8
1
• Programmable Output Voltage to 36 V
Micro8E
DM SUFFIX
CASE 846A
• Voltage Reference Tolerance: 0.4%, Typ @ 25°C (TL431B)
• Low Dynamic Output Impedance, 0.22 W Typical
• Sink Current Capability of 1.0 mA to 100 mA
8
1
• Equivalent Full−Range Temperature Coefficient of 50 ppm/°C Typical
1
2
3
4
8
7
6
5
Cathode
N/C
Reference
N/C
• Temperature Compensated for Operation over Full Rated Operating
Temperature Range
N/C
Anode
N/C
• Low Output Noise Voltage
• These are Pb−Free and Halide−Free Devices
N/C
(Top View)
SOIC−8
D SUFFIX
CASE 751
8
1
1
8
Cathode
Reference
Anode
2
3
4
7
6
5
Anode
N/C
N/C
(Top View)
This is an internally modified SOIC−8 package. Pins 2, 3, 6 and
7 are electrically common to the die attach flag. This internal
lead frame modification increases power dissipation capability
when appropriately mounted on a printed circuit board. This
modified package conforms to all external dimensions of the
standard SOIC−8 package.
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 13 of this data sheet.
DEVICE MARKING INFORMATION
See general marking information in the device marking
section on page 14 of this data sheet.
© Semiconductor Components Industries, LLC, 2012
1
Publication Order Number:
April, 2012 − Rev. 34
TL431/D
TL431, A, B Series, NCV431A, B
Symbol
Representative Schematic Diagram
Component values are nominal
Cathode
(K)
Cathode (K)
Reference
(R)
800
800
Reference
(R)
Anode
(A)
20 pF
Representative Block Diagram
150
3.28 k
7.2 k
4.0 k
20 pF
Reference
(R)
Cathode
(K)
10 k
2.4 k
+
-
1.0 k
2.5 V
ref
800
Anode (A)
Anode (A)
This device contains 12 active transistors.
MAXIMUM RATINGS (Full operating ambient temperature range applies, unless otherwise noted.)
Rating Symbol
Value
Unit
V
Cathode to Anode Voltage
V
KA
37
Cathode Current Range, Continuous
I
−100 to +150
−0.05 to +10
150
mA
mA
°C
K
Reference Input Current Range, Continuous
Operating Junction Temperature
I
ref
T
J
Operating Ambient Temperature Range
TL431I, TL431AI, TL431BI
TL431C, TL431AC, TL431BC
NCV431AI, NCV431B, TL431BV
T
A
°C
−40 to +85
0 to +70
−40 to +125
Storage Temperature Range
T
stg
−65 to +150
°C
Total Power Dissipation @ T = 25°C
P
D
W
A
Derate above 25°C Ambient Temperature
D, LP Suffix Plastic Package
P Suffix Plastic Package
0.70
1.10
0.52
DM Suffix Plastic Package
Total Power Dissipation @ T = 25°C
P
W
V
C
D
Derate above 25°C Case Temperature
D, LP Suffix Plastic Package
P Suffix Plastic Package
1.5
3.0
ESD Rating
HBM
MM
>2000
>200
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
RECOMMENDED OPERATING CONDITIONS
Condition
Symbol
Min
Max
36
Unit
V
Cathode to Anode Voltage
Cathode Current
V
KA
V
ref
I
K
1.0
100
mA
THERMAL CHARACTERISTICS
D, LP Suffix
Package
P Suffix
Package
DM Suffix
Package
Characteristic
Symbol
Unit
°C/W
°C/W
Thermal Resistance, Junction−to−Ambient
Thermal Resistance, Junction−to−Case
R
178
83
114
41
240
q
JA
R
−
q
JC
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2
TL431, A, B Series, NCV431A, B
ELECTRICAL CHARACTERISTICS (T = 25°C, unless otherwise noted.)
A
TL431I
Typ
TL431C
Typ
Min
Max
Min
Max
Characteristic
Symbol
Unit
Reference Input Voltage (Figure 1)
V
ref
V
V
= V , I = 10 mA
KA
ref K
T = 25°C
A
2.44
2.41
2.495
−
2.55
2.58
2.44
2.423
2.495
−
2.55
2.567
A
T = T
to T
(Note 1)
low
high
Reference Input Voltage Deviation Over
Temperature Range (Figure 1, Notes 1, 2)
= V = 10 mA
DV
−
7.0
30
−
3.0
17
mV
ref
V
KA
I
ref, K
Ratio of Change in Reference Input Voltage to Change
in Cathode to Anode Voltage
mV/V
DV
ref
DV
I
= 10 mA (Figure 2),
KA
K
DV = 10 V to V
−
−
−1.4
−1.0
−2.7
−2.0
−
−
−1.4
−1.0
−2.7
−2.0
KA
ref
DV = 36 V to 10 V
KA
Reference Input Current (Figure 2)
= 10 mA, R1 = 10 k, R2 = ∞
I
mA
mA
ref
I
K
T = 25°C
−
−
1.8
4.0
6.5
−
−
1.8
4.0
5.2
A
A
T = T
to T (Note 1)
high
−
−
low
Reference Input Current Deviation Over
Temperature Range (Figure 2, Note 1, 4)
DI
−
0.8
2.5
−
0.4
1.2
ref
I
K
= 10 mA, R1 = 10 k, R2 = ∞
Minimum Cathode Current For Regulation
= V (Figure 1)
I
−
−
−
0.5
20
1.0
1000
0.5
−
−
−
0.5
20
1.0
1000
0.5
mA
nA
W
min
V
KA
ref
Off−State Cathode Current (Figure 3)
= 36 V, V = 0 V
I
off
V
KA
ref
Dynamic Impedance (Figure 1, Note 3)
|Z
|
0.22
0.22
KA
V
KA
= V , DI = 1.0 mA to 100 mA
ref K
f ≤ 1.0 kHz
1. T
T
=
=
−40°C for TL431AIP TL431AILP, TL431IP, TL431ILP, TL431BID, TL431BIP, TL431BILP, TL431AIDM, TL431IDM, TL431BIDM;
0°C for TL431ACP, TL431ACLP, TL431CP, TL431CLP, TL431CD, TL431ACD, TL431BCD, TL431BCP, TL431BCLP, TL431CDM,
TL431ACDM, TL431BCDM
+85°C for TL431AIP, TL431AILP, TL431IP, TL431ILP, TL431BID, TL431BIP, TL431BILP, TL431IDM, TL431AIDM, TL431BIDM
+70°C for TL431ACP, TL431ACLP, TL431CP, TL431ACD, TL431BCD, TL431BCP, TL431BCLP, TL431CDM, TL431ACDM,
TL431BCDM
low
=
=
high
2. The deviation parameter DV is defined as the difference between the maximum and minimum values obtained over the full operating
ref
ambient temperature range that applies.
V
max
min
ref
DV = V max
ref
ref
-V min
ref
DT = T - T
A
2
1
V
ref
T1
T2
Ambient Temperature
D V
ref
6
X 10
ǒ
Ǔ
V
@ 25_C
6
D V x 10
ref
ref
ppm
_C
V
+
+
The average temperature coefficient of the reference input voltage, aV is defined as:
ref
ref
D T
D T (V @ 25_C)
A
A
ref
aV can be positive or negative depending on whether V Min or V Max occurs at the lower ambient temperature. (Refer to Figure 6.)
ref
ref
ref
Example : DV + 8.0 mV and slope is positive,
ref
6
0.008 x 10
V
@ 25_C + 2.495 V, DT + 70_C
a V
+
+ 45.8 ppmń_C
ref
A
ref
70 (2.495)
D V
KA
|Z | +
3. The dynamic impedance Z is defined as:
. When the device is programmed with two external resistors, R1 and R2,
R1
KA
KA
D I
K
KA| ǒ1 )
Ǔ
|Z Ȁ| [ |Z
(refer to Figure 2) the total dynamic impedance of the circuit is defined as:
KA
R2
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3
TL431, A, B Series, NCV431A, B
ELECTRICAL CHARACTERISTICS (T = 25°C, unless otherwise noted.)
A
TL431BC / TL431BI /
TL431BV /
NCV431BV
TL431AI / NCV431AI
Min Typ Max
TL431AC
Typ
Min
Max
Min
Typ
Max
Characteristic
Symbol
Unit
Reference Input Voltage (Figure 1)
V
ref
V
V
= V , I = 10 mA
KA
ref K
T = 25°C
A
2.47 2.495 2.52 2.47 2.495 2.52 2.485 2.495 2.505
A
T = T
to T
high
2.44
−
2.55 2.453
−
2.537 2.475 2.495 2.515
low
Reference Input Voltage Deviation Over
Temperature Range (Figure 1, Notes 4, 5)
= V = 10 mA
DV
−
7.0
30
−
3.0
17
−
3.0
17
mV
ref
V
KA
I
ref, K
Ratio of Change in Reference Input Voltage to
Change in Cathode to Anode Voltage
mV/V
DV
DV
ref
I
= 10 mA (Figure 2),
KA
K
DV = 10 V to V
−
−
−1.4
−1.0
−2.7
−2.0
−
−
−1.4
−1.0
−2.7
−2.0
−
−
−1.4 −2.7
−1.0 −2.0
KA
ref
DV = 36 V to 10 V
KA
Reference Input Current (Figure 2)
= 10 mA, R1 = 10 k, R2 = ∞
I
mA
mA
ref
I
K
T = 25°C
−
−
1.8
4.0
6.5
−
−
1.8
4.0
5.2
−
−
1.1
2.0
4.0
A
A
T = T
to T (Note 4)
high
−
−
−
low
Reference Input Current Deviation Over
Temperature Range (Figure 2, Note 4)
DI
−
0.8
2.5
−
0.4
1.2
−
0.8
2.5
ref
I
K
= 10 mA, R1 = 10 k, R2 = ∞
Minimum Cathode Current For Regulation
= V (Figure 1)
I
−
−
−
0.5
20
1.0
1000
0.5
−
−
−
0.5
20
1.0
1000
0.5
−
−
−
0.5
1.0
500
0.3
mA
nA
W
min
V
KA
ref
Off−State Cathode Current (Figure 3)
= 36 V, V = 0 V
I
0.23
0.14
off
V
KA
ref
Dynamic Impedance (Figure 1, Note 6)
|Z
|
0.22
0.22
KA
V
KA
= V , DI = 1.0 mA to 100 mA
ref K
f ≤ 1.0 kHz
4. T
=
=
−40°C for TL431AIP TL431AILP, TL431IP, TL431ILP, TL431BID, TL431BIP, TL431BILP, TL431BV, TL431AIDM, TL431IDM,
TL431BIDM, NCV431AIDMR2G, NCV431AIDR2G, NCV431BVDR2G
0°C for TL431ACP, TL431ACLP, TL431CP, TL431CLP, TL431CD, TL431ACD, TL431BCD, TL431BCP, TL431BCLP, TL431CDM,
TL431ACDM, TL431BCDM
low
T
high
=
=
+85°C for TL431AIP, TL431AILP, TL431IP, TL431ILP, TL431BID, TL431BIP, TL431BILP, TL431IDM, TL431AIDM, TL431BIDM
+70°C for TL431ACP, TL431ACLP, TL431CP, TL431ACD, TL431BCD, TL431BCP, TL431BCLP, TL431CDM, TL431ACDM,
TL431BCDM
=
+125°C TL431BV, NCV431AIDMR2G, NCV431AIDR2G, NCV431BVDMR2G, NCV431BVDR2G
5. The deviation parameter DV is defined as the difference between the maximum and minimum values obtained over the full operating
ref
ambient temperature range that applies.
V
max
min
ref
DV = V max
ref
ref
-V min
ref
DT = T - T
A
2
1
V
ref
T1
T2
D V
Ambient Temperature
ref
6
X 10
ǒ
Ǔ
V
@ 25_C
6
D V x 10
ref
ref
ppm
_C
The average temperature coefficient of the reference input voltage, aV is defined as:
V
+
+
ref
ref
D T
D T (V @ 25_C)
A
A
ref
aV can be positive or negative depending on whether V Min or V Max occurs at the lower ambient temperature. (Refer to Figure 6.)
ref
ref
ref
Example : DV + 8.0 mV and slope is positive,
ref
6
0.008 x 10
V
@ 25_C + 2.495 V, DT + 70_C
a V
+
+ 45.8 ppmń_C
ref
A
ref
70 (2.495)
D V
KA
|Z | +
6. The dynamic impedance Z is defined as
When the device is programmed with two external resistors, R1 and R2, (refer
R1
KA
KA
D I
K
KA| ǒ1 )
Ǔ
|Z Ȁ| [ |Z
to Figure 2) the total dynamic impedance of the circuit is defined as:
KA
R2
7. NCV431AIDMR2G, NCV431AIDR2G, NCV431BVDMR2G, NCV431BVDR2G T
= −40°C, T
= +125°C. Guaranteed by design.
low
high
NCV prefix is for automotive and other applications requiring unique site and control change requirements.
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4
TL431, A, B Series, NCV431A, B
Input
R1
V
KA
Input
V
KA
Input
V
KA
I
off
I
K
I
K
I
ref
V
ref
R2
R1
R2
ꢀǒꢀ1 ) ꢀǓ) I
V
+ V
ꢀSꢀR1
KA
ref
ref
V
ref
Figure 1. Test Circuit for VKA = Vref
Figure 2. Test Circuit for VKA > Vref
Figure 3. Test Circuit for Ioff
150
800
V
KA
= V
ref
V
KA
= V
ref
T = 25°C
T = 25°C
A
A
I
100
50
600
400
200
0
Input
V
KA
K
Min
Input
V
KA
I
I
K
0
-50
-100
-200
-2.0
-1.0
0
1.0
2.0
3.0
-1.0
0
1.0
V , CATHODE VOLTAGE (V)
KA
2.0
3.0
V
KA
, CATHODE VOLTAGE (V)
Figure 4. Cathode Current versus
Cathode Voltage
Figure 5. Cathode Current versus
Cathode Voltage
2600
2580
2560
2540
2520
2500
3.0
V
KA
Input
I
K V = V
KA
= 10 mA
ref
V
ref
Max = 2550 mV
2.5
2.0
1.5
1.0
0.5
0
I
K
V
ref
V
ref
Typ = 2495 mV
I
= 10 mA
I
2480
2460
2440
K
V
KA
Input
10k
I
ref
K
V
Min = 2440 mV
100
ref
2420
2400
-55
-25
0
25
50
75
125
-55
-25
0
25
50
75
100
125
T , AMBIENT TEMPERATURE (°C)
A
T , AMBIENT TEMPERATURE (°C)
A
Figure 6. Reference Input Voltage versus
Ambient Temperature
Figure 7. Reference Input Current versus
Ambient Temperature
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TL431, A, B Series, NCV431A, B
0
-8.0
-16
-24
-32
1.0 k
I
= 10 mA
K
T = 25°C
A
100
10
V
KA
V
ref
= 36 V
= 0 V
Input
R1
V
KA
1.0
I
K
V
KA
Input
I
off
R2
V
ref
0.1
0.01
-55
-25
0
25
50
75
100
125
0
10
20
, CATHODE VOLTAGE (V)
30
40
V
T , AMBIENT TEMPERATURE (5C)
KA
A
Figure 8. Change in Reference Input
Voltage versus Cathode Voltage
Figure 9. Off−State Cathode Current
versus Ambient Temperature
100
0.320
0.300
T = 25°C
K
A
1.0 k
V
KA
= V
ref
Output
K
D I = 1.0 mA to 100 mA
D I = 1.0 mA to 100 mA
K
I
f ≤ 1.0 kHz
50
-
+
Output
K
0.280
0.260
0.240
0.220
0.200
GND
10
1.0
0.1
1.0ꢀk
50
I
-
+
GND
1.0 k
10 k
100 k
f, FREQUENCY (MHz)
1.0 M
10 M
-55
-25
0
25
50
75
100
125
T , AMBIENT TEMPERATURE (°C)
A
Figure 10. Dynamic Impedance
versus Frequency
Figure 11. Dynamic Impedance
versus Ambient Temperature
80
60
40
20
0
60
Output
I
K
50
40
30
20
10
0
15ꢀk
9.0 mF
230
8.25ꢀk
GND
V
= V
ref
KA
I = 10 mA
K
T = 25°C
A
Input
Output
I
= 10 mA
K
I
K
T = 25°C
A
-10
1.0 k
10 k
100 k
f, FREQUENCY (MHz)
1.0 M
10 M
10
100
1.0 k
f, FREQUENCY (Hz)
10 k
100 k
Figure 12. Open−Loop Voltage Gain
Figure 13. Spectral Noise Density
versus Frequency
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TL431, A, B Series, NCV431A, B
140
T = 25°C
A
Unstable Programmed
Input
Monitor
3.0
2.0
1.0
T = 25°C
A
Area
V (V)
KA
C
120
Output
GND
A
B
C
D
V
ref
220
50
5.0
10
15
Output
100
80
Pulse
Generator
f = 100 kHz
60
Stable
A
Stable
D
0
5.0
0
B
40
20
0
B
A
Input
0
4.0
8.0
12
16
20
1.0 nF
10 nF
100 nF
1.0 mF
10 mF
100 mF
t, TIME (ms)
C , LOAD CAPACITANCE
L
Figure 14. Pulse Response
Figure 15. Stability Boundary Conditions
150
150
I
K
I
K
10 k
V+
V+
C
C
L
L
Figure 16. Test Circuit For Curve A
of Stability Boundary Conditions
Figure 17. Test Circuit For Curves B, C, And D
of Stability Boundary Conditions
TYPICAL APPLICATIONS
V+
V
out
V+
V
out
R1
R2
R1
R2
R1
R2
+ꢀ ǒ1 ) ǓꢀV
V
out
ref
R1
R2
+ꢀ ǒ1 ) ǓꢀV
V
out
ref
Figure 18. Shunt Regulator
Figure 19. High Current Shunt Regulator
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TL431, A, B Series, NCV431A, B
V+
V
out
MC7805
Out
Common
R1
R2
V+
V
out
In
R1
R2
R1
R2
+ꢀ ǒ1 ) ǓꢀV
V
V
out
ref
be
R1
R2
+ꢀ ǒ1 ) ǓꢀV
out(min)
V
out
ref
+ V ) V
out
in(min)
V
+ V ) 5.0ꢀV
ref
V
+ V
out(min)
ref
Figure 20. Output Control for a
Three−Terminal Fixed Regulator
Figure 21. Series Pass Regulator
R
CL
I
V+
sink
V+
I
out
V
ref
I
+
Sink
R
S
V
R
ref
CL
I
+
out
R
S
Figure 22. Constant Current Source
Figure 23. Constant Current Sink
V+
V+
V
out
V
out
R1
R2
R1
R2
R1
R2
+ꢀ ǒ1 ) ǓꢀV
V
out(trip)
ref
R1
R2
+ꢀ ǒ1 ) ǓꢀV
V
out(trip)
ref
Figure 24. TRIAC Crowbar
Figure 25. SRC Crowbar
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TL431, A, B Series, NCV431A, B
V+
V
out
V+
l
R1
R2
R3
V
out
V
in
R4
V
V
out
in
V
th
= V
ref
L.E.D. indicator is `on' when V+ is between the
upper and lower limits.
< V
> V
V+
≈ 2.0 V
ref
ref
R1
R2
LowerꢀLimit +ꢀ ǒ1 ) ǓꢀV
ref
ref
R3
UpperꢀLimit +ꢀ ǒ1 ) ǓꢀV
R4
Figure 26. Voltage Monitor
Figure 27. Single−Supply Comparator with
Temperature−Compensated Threshold
25 V
1N5305
38 V
2.0 mA
330
T = 330 to 8.0 W
l
T
5.0 k
1%
50 k 500 k
5.0 M
1%
10 k
Calibrate
I
+
1%
1%
470 mF
8.0 W
10 kW
V
360 k
100 kW
V
25 V
1.0 MW
V
1.0 mF
1.0 kW
V
-
*
LM11
V
out
Range
Volume
47 k
+
0.05 mF
Tone
*Thermalloy
*THM 6024
*Heatsink on
*LP Package
-5.0 V
R
X
56 k
10 k
25 k
W
V
R
x
+ V ꢀDꢀꢀ ꢀ Range
out
Figure 28. Linear Ohmmeter
Figure 29. Simple 400 mW Phono Amplifier
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9
TL431, A, B Series, NCV431A, B
150 mH @ 2.0 A
V
in
= 10 V to 20 V
TIP115
V
= 5.0 V
= 1.0 A
out
I
out
1.0 k
1N5823
4.7 k
4.7 k
100 k
MPSA20
4.7 k
0.01mF
+
2200 mF
+
470 mF
0.1 mF
2.2 k
10
51 k
Figure 30. High Efficiency Step−Down Switching Converter
Test
Conditions
= 10 V to 20 V, I = 1.0 A
Results
53 mV (1.1%)
25 mV (0.5%)
50 mVpp P.A.R.D.
100 mVpp P.A.R.D.
82%
Line Regulation
Load Regulation
Output Ripple
Output Ripple
Efficiency
V
in
V
in
V
in
V
in
V
in
o
= 15 V, I = 0 A to 1.0 A
o
= 10 V, I = 1.0 A
o
= 20 V, I = 1.0 A
o
= 15 V, I = 1.0 A
o
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10
TL431, A, B Series, NCV431A, B
APPLICATIONS INFORMATION
The TL431 is a programmable precision reference which
1
1
P2 +
+
+
+ 60 kHz
2p R
C
2p * 10 M * 0.265 pF
is used in a variety of ways. It serves as a reference voltage
in circuits where a non−standard reference voltage is
needed. Other uses include feedback control for driving an
optocoupler in power supplies, voltage monitor, constant
current source, constant current sink and series pass
regulator. In each of these applications, it is critical to
maintain stability of the device at various operating currents
and load capacitances. In some cases the circuit designer can
estimate the stabilization capacitance from the stability
boundary conditions curve provided in Figure 15. However,
these typical curves only provide stability information at
specific cathode voltages and at a specific load condition.
Additional information is needed to determine the
capacitance needed to optimize phase margin or allow for
process variation.
P2 P2
1
1
Z1 +
+ 500 kHz
2p R
C
2p * 15.9 k * 20 pF
Z1 P1
In addition, there is an external circuit pole defined by the
load:
1
P
+
L
2p R C
L L
Also, the transfer dc voltage gain of the TL431 is:
G + G R
GoR
M GM
L
Example 1:
A simplified model of the TL431 is shown in Figure 31.
When tested for stability boundaries, the load resistance is
150 W. The model reference input consists of an input
transistor and a dc emitter resistance connected to the device
anode. A dependent current source, Gm, develops a current
whose amplitude is determined by the difference between
the 1.78 V internal reference voltage source and the input
transistor emitter voltage. A portion of Gm flows through
I
+10mA, R + 230 W, C + 0. Define the transfer gain.
C
L
L
The DC gain is:
G + G R
GoR +
M GM
L
(2.138)(1.0 M)(1.25 m)(230) + 615 + 56 dB
8.25 k
8.25 k ) 15 k
compensation capacitance, C . The voltage across C
P2
P2
Loop gain + G
+ 218 + 47 dB
drives the output dependent current source, Go, which is
connected across the device cathode and anode.
The resulting transfer function Bode plot is shown in
Figure 32. The asymptotic plot may be expressed as the
following equation:
Model component values are:
V
= 1.78 V
ref
Gm = 0.3 + 2.7 exp (−I /26 mA)
C
where IC is the device cathode current and Gm is in mhos
jf
ǒ1 )
Ǔ
500 kHz
Go = 1.25 (V 2) mmhos.
Av + 615
cp
jf
jf
ǒ
1 )
Ǔǒ1 )
Ǔ
Resistor and capacitor typical values are shown on the
model. Process tolerances are 20% for resistors, 10% for
capacitors, and 40% for transconductances.
An examination of the device model reveals the location
of circuit poles and zeroes:
8.0 kHz
60 kHz
The Bode plot shows a unity gain crossover frequency of
approximately 600 kHz. The phase margin, calculated from
the equation, would be 55.9 degrees. This model matches the
Open−Loop Bode Plot of Figure 12. The total loop would
have a unity gain frequency of about 300 kHz with a phase
margin of about 44 degrees.
1
1
P1 +
+
+ 7.96 kHz
2p R
C
2p * 1.0 M * 20 pF
GM P1
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11
TL431, A, B Series, NCV431A, B
V
CC
R
L
C
L
Input
3
15 k
Cathode
9.0 mF
Go
1.0 mmho
R
10 M
P2
Ref
V
ref
1.78 V
1
C
20 pF
G
M
P1
C
+
P2
R
R
1.0 M
ref
16
GM
0.265 pF
R
Z1
500 k
-
15.9 k
8.25 k
Anode
2
Figure 31. Simplified TL431 Device Model
TL431 OPEN-LOOP VOLTAGE GAIN VERSUS FREQUENCY
Note that the transfer function now has an extra pole
formed by the load capacitance and load resistance.
Note that the crossover frequency in this case is about
250 kHz, having a phase margin of about −46 degrees.
Therefore, instability of this circuit is likely.
60
50
40
30
20
10
0
TL431 OPEN-LOOP BODE PLOT WITH LOAD CAP
80
60
40
20
-10
-20
1
2
3
4
5
6
7
10
10
10
10
10
10
10
f, FREQUENCY (Hz)
Figure 32. Example 1 Circuit Open Loop Gain Plot
Example 2.
0
I = 7.5 mA, R = 2.2 kW, C = 0.01 mF. Cathode tied to
C
L
L
reference input pin. An examination of the data sheet
stability boundary curve (Figure 15) shows that this value of
load capacitance and cathode current is on the boundary.
Define the transfer gain.
-20
1
2
3
4
5
6
10
10
10
10
10
10
f, FREQUENCY (Hz)
Figure 33. Example 2 Circuit Open Loop Gain Plot
The DC gain is:
With three poles, this system is unstable. The only hope
for stabilizing this circuit is to add a zero. However, that can
only be done by adding a series resistance to the output
capacitance, which will reduce its effectiveness as a noise
filter. Therefore, practically, in reference voltage
applications, the best solution appears to be to use a smaller
value of capacitance in low noise applications or a very
large value to provide noise filtering and a dominant pole
rolloff of the system.
G + G R
GoR +
M GM
L
(2.323)(1.0 M)(1.25 m)(2200) + 6389 + 76 dB
The resulting open loop Bode plot is shown in Figure 33.
The asymptotic plot may be expressed as the following
equation:
jf
ǒ1 )
Ǔ
500 kHz
Av + 615
jf
jf
jf
ǒ
1 )
Ǔǒ1 ) Ǔǒ1 )
Ǔ
8.0 kHz
60 kHz
7.2 kHz
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12
TL431, A, B Series, NCV431A, B
ORDERING INFORMATION
Marking
†
Code
Device
Operating Temperature Range
Package Code
Shipping Information
Tolerance
1.0%
0.4%
2.2%
1.0%
0.4%
2.2%
1.0%
0.4%
2.2%
1.0%
0.4%
2.2%
1.0%
0.4%
2.2%
1.0%
0.4%
2.2%
1.0%
0.4%
2.2%
TL431ACDG
AC
SOIC−8
TL431BCDG
BC
98 Units / Rail
(Pb−Free)
TL431CDG
C
TL431ACDR2G
TL431BCDR2G
TL431CDR2G
TL431ACDMR2G
TL431BCDMR2G
TL431CDMR2G
TL431ACPG
AC
SOIC−8
(Pb−Free)
BC
2500 Units / Tape & Reel
4000 Units / Tape & Reel
50 Units / Rail
C
TAC
TBC
T−C
ACP
BCP
CP
Micro8
(Pb−Free)
PDIP−8
(Pb−Free)
TL431BCPG
TL431CPG
TL431ACLPG
TL431BCLPG
TL431CLPG
ACLP
BCLP
CLP
ACLP
BCLP
CLP
ACLP
BCLP
CLP
0°C to 70°C
TO−92
(Pb−Free)
2000 Units / Bag
TL431ACLPRAG
TL431BCLPRAG
TL431CLPRAG
TL431ACLPREG
TL431BCLPREG
TL431CLPREG
TL431ACLPRPG
TO−92
(Pb−Free)
2000 Units / Tape & Reel
TO−92
(Pb−Free)
ACLP
2000 / Tape & Ammo Box
1.0%
TL431BCLPRMG
TL431CLPRMG
TL431CLPRPG
TL431AIDG
BCLP
CLP
CLP
AI
0.4%
2.2%
2.2%
1.0%
0.4%
2.2%
1.0%
0.4%
2.2%
1.0%
0.4%
2.2%
1.0%
0.4%
2.2%
1.0%
0.4%
2.2%
1.0%
0.4%
2.2%
2.2%
1.0%
1.0%
2.2%
TO−92
2000 Units / Fan−Fold
(Pb−Free)
SOIC−8
(Pb−Free)
TL431BIDG
BI
98 Units / Rail
2500 Units / Tape & Reel
4000 Units / Tape & Reel
50 Units / Rail
TL431IDG
I
TL431AIDR2G
TL431BIDR2G
TL431IDR2G
TL431AIDMR2G
TL431BIDMR2G
TL431IDMR2G
TL431AIPG
AI
SOIC−8
(Pb−Free)
BI
I
TAI
TBI
T−I
AIP
BIP
IP
Micro8
(Pb−Free)
PDIP−8
(Pb−Free)
TL431BIPG
−40°C to 85°C
TL431IPG
TL431AILPG
TL431BILPG
TL431ILPG
AILP
BILP
ILP
AILP
BILP
ILP
ILP
TO−92
(Pb−Free)
2000 Units / Bag
TL431AILPRAG
TL431BILPRAG
SC431ILPRAG
TL431ILPRAG
TL431AILPRMG
TL431AILPRPG
TL431ILPRPG
TO−92
(Pb−Free)
2000 Units / Tape & Reel
AILP
ILP
TO−92
(Pb−Free)
2000 / Tape & Ammo Box
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
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13
TL431, A, B Series, NCV431A, B
ORDERING INFORMATION
Marking
†
Code
Device
Operating Temperature Range
Package Code
Shipping Information
Tolerance
0.4%
TL431BVDG
98 Units / Rail
SOIC−8
BV
(Pb−Free)
TL431BVDR2G
TL431BVDMR2G
2500 Units / Tape & Reel
0.4%
Micro8
(Pb−Free)
TBV
4000 Units / Tape & Reel
0.4%
TL431BVLPG
TL431BVLPRAG
TL431BVPG
2000 Units / Bag
0.4%
0.4%
TO−92
BVLP
(Pb−Free)
2000 Units / Tape & Reel
PDIP−8
(Pb−Free)
BVP
RAN
AV
50 Units / Rail
0.4%
1%
−40°C to 125°C
NCV431AIDMR2G
NCV431AIDR2G
NCV431BVDMR2G
NCV431BVDR2G
Micro8
(Pb−Free)
4000 Units / Tape & Reel
2500 Units / Tape & Reel
4000 Units / Tape & Reel
2500 Units / Tape & Reel
SOIC−8
(Pb−Free)
1%
Micro8
(Pb−Free)
NVB
BV
0.4%
0.4%
SOIC−8
(Pb−Free)
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
MARKING DIAGRAMS
SOIC−8
D SUFFIX
CASE 751
Micro8
CASE 846A
PDIP−8
CASE 626
TO−92 (TO−226)
CASE 29
8
8
8
1
TL431
xxxx
431xx
ALYW
G
TL431xxx
AWL
YYWWG
xxx
AYWG
G
YWW G
G
1
8
1
xxxx
A
Y, YY
= See Specific Marking Code
= Assembly Location
= Year
TL431
ALYWx
G
WW, W = Work Week
1
G or G
= Pb−Free Package
(Note: Microdot may be in either location)
(Exception for the TL431CD
and TL431ID only)
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14
TL431, A, B Series, NCV431A, B
PACKAGE DIMENSIONS
TO−92 (TO−226)
CASE 29−11
ISSUE AM
1
1
2
2
3
3
STRAIGHT LEAD
BULK PACK
BENT LEAD
TAPE & REEL
AMMO PACK
NOTES:
A
STRAIGHT LEAD
BULK PACK
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
3. CONTOUR OF PACKAGE BEYOND DIMENSION R
IS UNCONTROLLED.
B
R
4. LEAD DIMENSION IS UNCONTROLLED IN P AND
BEYOND DIMENSION K MINIMUM.
P
L
INCHES
DIM MIN MAX
MILLIMETERS
SEATING
PLANE
K
MIN
4.45
4.32
3.18
0.407
1.15
2.42
0.39
12.70
6.35
2.04
---
MAX
5.20
5.33
4.19
0.533
1.39
2.66
0.50
---
A
B
C
D
G
H
J
0.175
0.170
0.125
0.016
0.045
0.095
0.015
0.500
0.250
0.080
---
0.205
0.210
0.165
0.021
0.055
0.105
0.020
---
D
X X
G
J
H
K
L
---
---
V
N
P
R
V
0.105
0.100
---
2.66
2.54
---
C
SECTION X−X
0.115
0.135
2.93
3.43
1
N
---
---
N
NOTES:
A
BENT LEAD
TAPE & REEL
AMMO PACK
1. DIMENSIONING AND TOLERANCING PER
ASME Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS.
3. CONTOUR OF PACKAGE BEYOND
DIMENSION R IS UNCONTROLLED.
B
R
4. LEAD DIMENSION IS UNCONTROLLED IN P
AND BEYOND DIMENSION K MINIMUM.
P
T
MILLIMETERS
SEATING
PLANE
DIM MIN
MAX
5.20
5.33
4.19
0.54
2.80
0.50
---
K
A
B
C
D
G
J
4.45
4.32
3.18
0.40
2.40
0.39
12.70
2.04
1.50
2.93
3.43
D
X X
G
K
N
P
R
V
J
2.66
4.00
---
V
C
---
SECTION X−X
1
N
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15
TL431, A, B Series, NCV431A, B
PACKAGE DIMENSIONS
PDIP−8
P SUFFIX
CASE 626−05
ISSUE M
NOTES:
D
1. DIMENSIONING AND TOLERANCING PER ASME
A
Y14.5M, 1994.
2. CONTROLLING DIMENSION: INCHES.
3. DIMENSION E IS MEASURED WITH THE LEADS RE-
STRAINED PARALLEL AT WIDTH E2.
4. DIMENSION E1 DOES NOT INCLUDE MOLD FLASH.
5. ROUNDED CORNERS OPTIONAL.
D1
E
8
5
4
INCHES
NOM
−−−− 0.210
MILLIMETERS
E1
DIM MIN
−−−−
A1 0.015
b
C
D
MAX
MIN
NOM
−−−−
MAX
5.33
A
−−−−
0.38
0.35
0.20
9.02
0.13
7.62
6.10
1
−−−− −−−−
−−−− −−−−
0.014 0.018 0.022
0.008 0.010 0.014
0.355 0.365 0.400
0.46
0.25
0.56
0.36
NOTE 5
9.27 10.02
F
c
D1 0.005
0.300 0.310 0.325
E1 0.240 0.250 0.280
−−−− −−−−
−−−− −−−−
E
7.87
6.35
8.26
7.11
E2
TOP VIEW
END VIEW
E2
E3
e
0.300 BSC
−−−− 0.430
0.100 BSC
7.62 BSC
NOTE 3
−−−−
−−−−
−−−− 10.92
2.54 BSC
3.30 3.81
e/2
L
0.115 0.130 0.150
2.92
A
L
A1
SEATING
PLANE
C
E3
e
8X
b
M
0.010
C A
END VIEW
SIDE VIEW
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16
TL431, A, B Series, NCV431A, B
PACKAGE DIMENSIONS
Micro8
DM SUFFIX
CASE 846A−02
ISSUE G
NOTES:
D
1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE
BURRS. MOLD FLASH, PROTRUSIONS OR GATE BURRS SHALL NOT EXCEED
0.15 (0.006) PER SIDE.
4. DIMENSION B DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSION.
INTERLEAD FLASH OR PROTRUSION SHALL NOT EXCEED 0.25 (0.010) PER SIDE.
5. 846A-01 OBSOLETE, NEW STANDARD 846A-02.
H
E
E
MILLIMETERS
INCHES
NOM
−−
0.003
0.013
0.007
0.118
DIM
A
A1
b
c
D
MIN
−−
0.05
0.25
0.13
2.90
2.90
NOM
−−
MAX
MIN
−−
0.002
0.010
0.005
0.114
0.114
MAX
0.043
0.006
0.016
0.009
0.122
0.122
PIN 1 ID
1.10
0.15
0.40
0.23
3.10
3.10
e
0.08
b 8 PL
0.33
M
S
S
0.08 (0.003)
T
B
A
0.18
3.00
E
3.00
0.118
e
L
0.65 BSC
0.55
4.90
0.026 BSC
0.021
0.193
0.40
4.75
0.70
5.05
0.016
0.187
0.028
0.199
SEATING
PLANE
H
E
−T−
A
0.038 (0.0015)
L
A1
c
SOLDERING FOOTPRINT*
1.04
0.38
8X
8X 0.041
0.015
3.20
4.24
5.28
0.126
0.167 0.208
0.65
6X0.0256
SCALE 8:1
mm
inches
ǒ
Ǔ
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
http://onsemi.com
17
TL431, A, B Series, NCV431A, B
PACKAGE DIMENSIONS
SOIC−8
D SUFFIX
CASE 751−07
ISSUE AK
NOTES:
−X−
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
A
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A AND B DO NOT INCLUDE
MOLD PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 (0.005) TOTAL
IN EXCESS OF THE D DIMENSION AT
MAXIMUM MATERIAL CONDITION.
6. 751−01 THRU 751−06 ARE OBSOLETE. NEW
STANDARD IS 751−07.
8
5
4
S
M
M
B
0.25 (0.010)
Y
1
K
−Y−
G
MILLIMETERS
DIM MIN MAX
INCHES
MIN
MAX
0.197
0.157
0.069
0.020
C
N X 45
_
A
B
C
D
G
H
J
K
M
N
S
4.80
3.80
1.35
0.33
5.00 0.189
4.00 0.150
1.75 0.053
0.51 0.013
SEATING
PLANE
−Z−
1.27 BSC
0.050 BSC
0.10 (0.004)
0.10
0.19
0.40
0
0.25 0.004
0.25 0.007
1.27 0.016
0.010
0.010
0.050
8
0.020
0.244
M
J
H
D
8
0
_
_
_
_
M
S
S
0.25 (0.010)
Z
Y
X
0.25
5.80
0.50 0.010
6.20 0.228
SOLDERING FOOTPRINT*
1.52
0.060
7.0
4.0
0.275
0.155
0.6
0.024
1.270
0.050
mm
inches
ǒ
Ǔ
SCALE 6:1
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
Micro8 is a trademark of International Rectifier.
ON Semiconductor and
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All
operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights
nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications
intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should
Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates,
and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death
associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal
Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
PUBLICATION ORDERING INFORMATION
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For additional information, please contact your local
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TL431/D
相关型号：
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