UC2842ANG [ONSEMI]
1A SWITCHING CONTROLLER, 500kHz SWITCHING FREQ-MAX, PDIP8, LEAD FREE, PLASTIC, DIP-8;
| 型号： | UC2842ANG |
| 厂家： | 
ONSEMI |
| 描述： | 1A SWITCHING CONTROLLER, 500kHz SWITCHING FREQ-MAX, PDIP8, LEAD FREE, PLASTIC, DIP-8 开关 光电二极管 |
| 文件： | 总18页 (文件大小：365K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
UC3842A, UC3843A,
UC2842A, UC2843A
High Performance
Current Mode Controllers
The UC3842A, UC3843A series of high performance fixed
frequency current mode controllers are specifically designed for
off−line and DC−to−DC converter applications offering the designer a
cost effective solution with minimal external components. These
integrated circuits feature a trimmed oscillator for precise duty cycle
control, a temperature compensated reference, high gain error
amplifier, current sensing comparator, and a high current totem pole
output ideally suited for driving a power MOSFET.
Also included are protective features consisting of input and
reference undervoltage lockouts each with hysteresis, cycle−by−cycle
current limiting, programmable output deadtime, and a latch for single
pulse metering.
http://onsemi.com
PDIP−8
N SUFFIX
CASE 626
8
1
SOIC−14
D SUFFIX
CASE 751A
14
These devices are available in an 8−pin dual−in−line plastic package
as well as the 14−pin plastic surface mount (SOIC−14). The SOIC−14
package has separate power and ground pins for the totem pole output
stage.
The UCX842A has UYLO thresholds of 16 V (on) and 10 V (off),
ideally suited for off−line converters. The UCX843A is tailored for
lower voltage applications having UVLO thresholds of 8.5 V (on) and
7.6 V (off).
1
SOIC−8
D1 SUFFIX
CASE 751
8
1
PIN CONNECTIONS
Features
• Trimmed Oscillator Discharge Current for Precise Duty Cycle
Control
• Current Mode Operation to 500 kHz
• Automatic Feed Forward Compensation
Compensation
Voltage Feedback
Current Sense
1
8
V
V
ref
2
3
4
7
6
5
CC
Output
GND
R /C
T
T
• Latching PWM for Cycle−By−Cycle Current Limiting
• Internally Trimmed Reference with Undervoltage Lockout
• High Current Totem Pole Output
(Top View)
1
14
13
Compensation
NC
V
ref
• Undervoltage Lockout with Hysteresis
2
NC
• Low Startup and Operating Current
• Direct Interface with ON Semiconductor SENSEFET™ Products
• Pb−Free Packages are Available
3
4
12
11
Voltage Feedback
NC
V
CC
V
C
5
6
7
10
9
Current Sense
NC
Output
GND
R /C
T
8
Power Ground
T
(Top View)
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 15 of this data sheet.
DEVICE MARKING INFORMATION
See general marking information in the device marking
section on page 16 of this data sheet.
©
Semiconductor Components Industries, LLC, 2005
1
Publication Order Number:
November, 2005 − Rev. 8
UC3842A/D
UC3842A, UC3843A, UC2842A, UC2843A
V
7(12)
CC
V
V
CC
ref
5.0V
Reference
Undervoltage
Lockout
8(14)
R
R
V
ref
V
C
Undervoltage
Lockout
7(11)
R C
T
Output
T
Oscillator
6(10)
4(7)
Latching
PWM
Power
Ground
5(8)
Voltage
Feedback
Input
+
−
2(3)
Error
Amplifier
Current
Sense
Input
Output
Compensation
1(1)
3(5)
GND 5(9)
Pin numbers in parenthesis are for the D suffix SOIC−14 package.
Figure 1. Simplified Block Diagram
MAXIMUM RATINGS
Rating
Symbol
, V
Value
Unit
V
Bias and Driver Voltages (Zero Series Impedance, see also Total Device spec)
Total Power Supply and Zener Current
V
30
CC
C
(I + I )
30
mA
A
CC
Z
Output Current, Source or Sink (Note 1)
I
1.0
5.0
O
Output Energy (Capacitive Load per Cycle)
Current Sense and Voltage Feedback Inputs
Error Amp Output Sink Current
W
ꢀ J
V
V
in
− 0.3 to + 5.5
10
I
mA
O
Power Dissipation and Thermal Characteristics
D Suffix, Plastic Package
Maximum Power Dissipation @ T = 25°C
Thermal Resistance, Junction−to−Air
N Suffix, Plastic Package
P
862
145
mW
°C/W
A
D
R
ꢁ
JA
Maximum Power Dissipation @ T = 25°C
P
1.25
100
W
°C/W
A
D
Thermal Resistance, Junction−to−Air
R
ꢁ
JA
Operating Junction Temperature
T
+ 150
°C
°C
J
Operating Ambient Temperature
UC3842A, UC3843A
T
A
0 to + 70
UC2842A, UC2843A
− 25 to + 85
Storage Temperature Range
T
stg
− 65 to + 150
°C
Maximum ratings are those values beyond which device damage can occur. Maximum ratings applied to the device are individual stress limit
values (not normal operating conditions) and are not valid simultaneously. If these limits are exceeded, device functional operation is not implied,
damage may occur and reliability may be affected.
1. Maximum Package power dissipation limits must be observed.
http://onsemi.com
2
UC3842A, UC3843A, UC2842A, UC2843A
ELECTRICAL CHARACTERISTICS (V = 15 V, [Note 2], R = 10 k, C = 3.3 nF, T = T to T
[Note 3],
CC
T
T
A
low
high
unless otherwise noted.)
UC284XA
UC384XA
Typ
Min
Typ
Max
Min
Max
Characteristics
REFERENCE SECTION
Reference Output Voltage (I = 1.0 mA, T = 25°C)
Symbol
Unit
V
ref
4.95
−
5.0
2.0
3.0
0.2
−
5.05
20
25
−
4.9
−
5.0
2.0
3.0
0.2
−
5.1
20
25
−
V
mV
mV
mV/°C
V
O
J
Line Regulation (V = 12 V to 25 V)
Reg
line
CC
Load Regulation (I = 1.0 mA to 20 mA)
Reg
T
−
−
O
load
Temperature Stability
−
−
S
Total Output Variation over Line, Load, Temperature
V
ref
4.9
−
5.1
−
4.82
−
5.18
−
Output Noise Voltage (f = 10 Hz to 10 kHz,
V
50
50
ꢀ
V
n
T = 25°C)
J
Long Term Stability (T = 125°C for 1000 Hours)
S
−
5.0
−
−
5.0
−
mV
mA
A
Output Short Circuit Current
I
− 30
− 85
− 180
− 30
− 85
− 180
SC
OSCILLATOR SECTION
Frequency
f
kHz
osc
T = 25°C
47
46
52
−
57
60
47
46
52
−
57
60
J
T = T
to T
A
low
high
Frequency Change with Voltage (V = 12 V to 25 V)
ꢂ f
ꢂ f
ꢂ
−
−
0.2
5.0
1.0
−
−
−
0.2
5.0
1.0
−
%
%
CC
osc/
V
T
Frequency Change with Temperature
ꢂ
osc/
T = T
A
to T
high
low
Oscillator Voltage Swing (Peak−to−Peak)
V
osc
−
1.6
−
−
1.6
−
V
Discharge Current (V
= 2.0 V)
I
mA
osc
dischg
T = 25°C
7.5
7.2
8.4
−
9.3
9.5
7.5
7.2
8.4
−
9.3
9.5
J
T = T
to T
high
A
low
ERROR AMPLIFIER SECTION
Voltage Feedback Input (V = 2.5 V)
V
2.45
−
2.5
−0.1
90
2.55
−1.0
−
2.42
−
2.5
−0.1
90
2.58
−2.0
−
V
ꢀ A
O
FB
Input Bias Current (V = 2.7 V)
I
FB
IB
Open Loop Voltage Gain (V = 2.0 V to 4.0 V)
A
VOL
65
65
dB
O
Unity Gain Bandwidth (T = 25°C)
BW
0.7
60
1.0
70
−
0.7
60
1.0
70
−
MHz
dB
J
Power Supply Rejection Ratio (V = 12 V to 25 V)
PSRR
−
−
CC
Output Current
mA
Sink (V = 1.1 V, V = 2.7 V)
2.0
−0.5
12
−1.0
−
−
2.0
−0.5
12
−1.0
−
−
I
O
FB
Sink
Source (V = 5.0 V, V = 2.3 V)
O
FB
I
Source
Output Voltage Swing
V
High State (R = 15 k to ground, V = 2.3 V)
5.0
−
6.2
0.8
−
1.1
5.0
−
6.2
0.8
−
1.1
V
L
FB
OH
Low State (R = 15 k to V , V = 2.7 V)
L
ref
FB
V
OL
2. Adjust V above the Startup threshold before setting to 15 V.
CC
3. Low duty cycle pulse techniques are used during test to maintain junction temperature as close to ambient as possible.
T
= 0°C for UC3842A, UC3843A
−25°C for UC2842A, UC2843A
T
= +70°C for UC3842A, UC3843A
+85°C for UC2842A, UC2843A
low
high
http://onsemi.com
3
UC3842A, UC3843A, UC2842A, UC2843A
ELECTRICAL CHARACTERISTICS (V = 15 V, [Note 4], R = 10 k, C = 3.3 nF, T = T to T
[Note 5],
CC
T
T
A
low
high
unless otherwise noted.)
UC284XA
UC384XA
Typ
Characteristics
CURRENT SENSE SECTION
Symbol
Min
Typ
Max
Min
Max
Unit
Current Sense Input Voltage Gain (Notes 6 & 7)
Maximum Current Sense Input Threshold (Note 6)
Power Supply Rejection Ratio
A
2.85
0.9
3.0
1.0
3.15
1.1
2.85
0.9
3.0
1.0
3.15
1.1
V/V
V
V
V
th
PSRR
dB
V
= 12 to 25 V (Note 6)
−
−
−
70
−
−
−
−
70
−
CC
Input Bias Current
I
−2.0
150
−10
300
−2.0
150
−10
300
ꢀ
A
IB
Propagation Delay (Current Sense Input to Output)
t
ns
PLH(in/out)
OUTPUT SECTION
Output Voltage
V
Low State (I
Low State (I
High State (I
High State (I
= 20 mA)
= 200 mA)
= 20 mA)
= 200 mA)
V
−
−
13
12
0.1
1.6
13.5
13.4
0.4
2.2
−
−
−
13
12
0.1
1.6
13.5
13.4
0.4
2.2
−
Sink
Sink
Sink
Sink
OL
V
OH
−
−
Output Voltage with UVLO Activated
= 6.0 V, I = 1.0 mA
V
V
OL(UVLO)
V
−
−
−
0.1
50
50
1.1
150
150
−
−
−
0.1
50
50
1.1
150
150
CC
Sink
Output Voltage Rise Time (C = 1.0 nF, T = 25°C)
t
ns
ns
L
J
r
Output Voltage Fall Time (C = 1.0 nF, T = 25°C)
t
L
J
f
UNDERVOLTAGE LOCKOUT SECTION
Startup Threshold
UCX842A
UCX843A
V
V
V
th
15
7.8
16
8.4
17
9.0
14.5
7.8
16
8.4
17.5
9.0
Minimum Operating Voltage After Turn−On
V
CC(min)
UCX842A
UCX843A
9.0
7.0
10
7.6
11
8.2
8.5
7.0
10
7.6
11.5
8.2
PWM SECTION
Duty Cycle
Maximum
Minimum
%
DC
DC
94
−
96
−
−
0
94
−
96
−
−
0
max
min
TOTAL DEVICE
Power Supply Current (Note 4)
Startup:
I
mA
V
CC
(V = 6.5 V for UCX843A,
−
−
0.5
12
1.0
17
−
−
0.5
12
1.0
17
CC
(V = 14 V for UCX842A) Operating
CC
Power Supply Zener Voltage (I = 25 mA)
V
30
36
−
30
36
−
CC
Z
4. Adjust V above the Startup threshold before setting to 15 V.
CC
5. Low duty cycle pulse techniques are used during test to maintain junction temperature as close to ambient as possible.
T
= 0°C for UC3842A, UC3843A
T
= +70°C for UC3842A, UC3843A
low
high
−25°C for UC2842A, UC2843A
+85°C for UC2842A, UC2843A
6. This parameter is measured at the latch trip point with V = 0 V.
FB
ꢂ
V
O
u
t
p
u
t
C
o
m
p
e
n
s
a
t
i
o
n
7. Comparator gain is defined as: A
V
ꢂ
V
C
u
r
r
e
n
t
S
e
n
s
e
I
n
p
u
t
http://onsemi.com
4
UC3842A, UC3843A, UC2842A, UC2843A
80
50
100
V
= 15 V
CC
50
20
T = 25°C
A
20
8.0
5.0
10
5.0
V
= 15 V
2.0
0.8
CC
2.0
1.0
T = 25°C
A
10 k
20 k
50 k
100 k
200 k
500 k
1.0 M
10 k
20 k
50 k
100 k
200 k
500 k
1.0 M
f , OSCILLATOR FREQUENCY (Hz)
OSC
f , OSCILLATOR FREQUENCY (Hz)
OSC
Figure 2. Timing Resistor versus
Oscillator Frequency
Figure 3. Output Deadtime versus
Oscillator Frequency
9.0
8.5
8.0
7.5
7.0
100
90
80
70
60
V
= 15 V
C = 3.3 nF
CC
V
V
= 15 V
= 2.0 V
CC
T
OSC
T = 25°C
A
I
= 7.2 mA
dischg
50
40
I
= 9.5 mA
dischg
800 1.0 k
2.0 k
3.0 k 4.0 k
6.0 k 8.0 k
−55
−25
0
25
50
75
100
125
T , AMBIENT TEMPERATURE (°C)
A
R , TIMING RESISTOR (ꢃ)
T
Figure 4. Oscillator Discharge Current
versus Temperature
Figure 5. Maximum Output Duty Cycle
versus Timing Resistor
V
A = −1.0
T = 25°C
A
= 15 V
V
A = −1.0
T = 25°C
A
= 15 V
CC
CC
3.0 V
2.5 V
2.0 V
V
V
2.55 V
2.5 V
2.45 V
0.5 ꢀ s/DIV
0.1 ꢀ s/DIV
Figure 6. Error Amp Small Signal
Transient Response
Figure 7. Error Amp Large Signal
Transient Response
http://onsemi.com
5
UC3842A, UC3843A, UC2842A, UC2843A
100
80
60
40
20
1.2
1.0
0.8
0.6
0.4
0.2
0
0
V
V
= 15 V
= 2.0 V to 4.0 V
CC
V
= 15 V
CC
O
30
60
90
120
R = 100 K
L
T = 25°C
A
Gain
T = 25°C
A
T = 125°C
A
Phase
T = −55°C
A
0
150
180
−ꢀ20
10
100
1.0 k
10 k
100 k
1.0 M
10 M
0
2.0
4.0
6.0
8.0
f, FREQUENCY (Hz)
V , ERROR AMP OUTPUT VOLTAGE (V)
O
Figure 8. Error Amp Open Loop Gain and
Phase versus Frequency
Figure 9. Current Sense Input Threshold
versus Error Amp Output Voltage
0
−4.0
−8.0
−12
−16
−20
−24
110
90
V
= 15 V
CC
V
= 15 V
ꢃ
CC
R ≤ 0.1
L
70
T = 125°C
A
T = 55°C
A
T = 25°C
A
50
0
20
I
40
60
80
100
120
−55
−25
0
25
50
75
100
125
, REFERENCE SOURCE CURRENT (mA)
T , AMBIENT TEMPERATURE (°C)
ref
A
Figure 10. Reference Voltage Change
versus Source Current
Figure 11. Reference Short Circuit Current
versus Temperature
V
= 15 V
I = 1.0 mA to 20 mA
CC
V
= 12 V to 25 V
CC
O
T = 25°C
A
T = 25°C
A
2.0 ms/DIV
2.0 ms/DIV
Figure 13. Reference Line Regulation
Figure 12. Reference Load Regulation
http://onsemi.com
6
UC3842A, UC3843A, UC2842A, UC2843A
0
−1.0
−2.0
Source Saturation
(Load to Ground)
V
= 15 V
CC
80 ꢀ s Pulsed Load
V
CC
V
= 15 V
CC
C = 1.0 nF
T
= 25°C
90%
120 Hz Rate
L
A
T = 25°C
A
T
= −55°C
A
3.0
2.0
1.0
0
T
A
= −55°C
T
= 25°C
A
10%
Sink Saturation
)
GND
(Load to V
CC
50 ns/DIV
0
200
400
600
800
I , OUTPUT LOAD CURRENT (mA)
O
Figure 14. Output Saturation Voltage
versus Load Current
Figure 15. Output Waveform
25
20
V
= 30 V
C = 15 pF
CC
L
T = 25°C
A
15
10
R = 10 k
T
C = 3.3 nF
T
V
= 0 V
FB
5
0
I
= 0 V
Sense
T = 25°C
A
0
10
20
30
40
100 ns/DIV
V
, SUPPLY VOLTAGE
CC
Figure 16. Output Cross Conduction
Figure 17. Supply Current versus
Supply Voltage
http://onsemi.com
7
UC3842A, UC3843A, UC2842A, UC2843A
V
in
V
CC
V
CC
7(12)
36V
V
+
−
ref
Reference
Regulator
8(14)
V
CC
UVLO
+
R
R
Internal
Bias
−
2.5V
+
V
C
−
+
R
T
7(11)
V
ref
UVLO
3.6V
−
Q1
Output
6(10)
Oscillator
4(7)
T Q
+
C
T
1.0mA
Power Ground
5(8)
S
R
+
−
Q
−
+
Voltage Feedback
Input
PWM
Latch
2R
2(3)
Error
Amplifier
R
Current Sense Input
3(5)
1.0V
Output
Compensation
1(1)
Current Sense
Comparator
R
S
GND 5(9)
+
−
Sink Only
Positive True Logic
=
Pin numbers in parenthesis are for the D suffix SOIC−14 package.
Figure 18. Representative Block Diagram
Capacitor C
T
Latch
‘‘Set’’ Input
Output/
Compensation
Current Sense
Input
Latch
‘‘Reset’’ Input
Output
Large R /Small C
T
Small R /Large C
T T
T
Figure 19. Timing Diagram
http://onsemi.com
8
UC3842A, UC3843A, UC2842A, UC2843A
OPERATING DESCRIPTION
The UC3842A, UC3843A series are high performance,
is removed, or at the beginning of a soft−start interval
(Figures 24, 25). The Error Amp minimum feedback
resistance is limited by the amplifier’s source current
fixed frequency, current mode controllers. They are
specifically designed for Off−Line and DC−to−DC
converter applications offering the designer a cost effective
(0.5 mA) and the required output voltage (V ) to reach the
OH
solution with minimal external components.
representative block diagram is shown in Figure 18.
A
comparator’s 1.0 V clamp level:
3.0 (1.0 V) + 1.4 V
Rf(min)
≈
= 8800 ꢃ
0.5 mA
Oscillator
The oscillator frequency is programmed by the values
selected for the timing components R and C . Capacitor C
Current Sense Comparator and PWM Latch
T
T
T
The UC3842A, UC3843A operate as a current mode
controller, whereby output switch conduction is initiated by
the oscillator and terminated when the peak inductor current
reaches the threshold level established by the Error
Amplifier Output/Compensation (Pin 1). Thus the error
is charged from the 5.0 V reference through resistor R to
T
approximately 2.8 V and discharged to 1.2 V by an internal
current sink. During the discharge of C , the oscillator
T
generates and internal blanking pulse that holds the center
input of the NOR gate high. This causes the Output to be in
a low state, thus producing a controlled amount of output
signal controls the peak inductor current on
a
cycle−by−cyclebasis. The current Sense Comparator PWM
Latch configuration used ensures that only a single pulse
appears at the Output during any given oscillator cycle. The
inductor current is converted to a voltage by inserting the
deadtime. Figure 2 shows R versus Oscillator Frequency
T
and Figure 3, Output Deadtime versus Frequency, both for
given values of C . Note that many values of R and C will
T
T
T
give the same oscillator frequency but only one combination
will yield a specific output deadtime at a given frequency.
The oscillator thresholds are temperature compensated, and
the discharge current is trimmed and guaranteed to within
ground referenced sense resistor R in series with the source
S
of output switch Q1. This voltage is monitored by the
Current Sense Input (Pin 3) and compared a level derived
from the Error Amp Output. The peak inductor current under
normal operating conditions is controlled by the voltage at
pin 1 where:
10% at T = 25°C. These internal circuit refinements
J
minimize variations of oscillator frequency and maximum
output duty cycle. The results are shown in Figures 4 and 5.
In many noise sensitive applications it may be desirable to
frequency−lock the converter to an external system clock.
This can be accomplished by applying a clock signal to the
circuit shown in Figure 21. For reliable locking, the
free−running oscillator frequency should be set about 10%
less than the clock frequency. A method for multi unit
synchronization is shown in Figure 22. By tailoring the
clock waveform, accurate Output duty cycle clamping can
be achieved.
V(Pin 1) − 1.4 V
Ipk
=
3 RS
Abnormal operating conditions occur when the power
supply output is overloaded or if output voltage sensing is
lost. Under these conditions, the Current Sense Comparator
threshold will be internally clamped to 1.0 V. Therefore the
maximum peak switch current is:
1.0 V
RS
Ipk(max)
=
When designing a high power switching regulator it
becomes desirable to reduce the internal clamp voltage in
Error Amplifier
A fully compensated Error Amplifier with access to the
inverting input and output is provided. It features a typical
dc voltage gain of 90 dB, and a unity gain bandwidth of
1.0 MHz with 57 degrees of phase margin (Figure 8). The
noninverting input is internally biased at 2.5 V and is not
pinned out. The converter output voltage is typically divided
down and monitored by the inverting input. The maximum
input bias current is −2.0 ꢀ A which can cause an output
voltage error that is equal to the product of the input bias
current and the equivalent input divider source resistance.
The Error Amp Output (Pin 1) is provide for external loop
compensation (Figure 31). The output voltage is offset by
two diode drops (≈ 1.4 V) and divided by three before it
connects to the inverting input of the Current Sense
Comparator. This guarantees that no drive pulses appear at
order to keep the power dissipation of R to a reasonable
S
level. A simple method to adjust this voltage is shown in
Figure 23. The two external diodes are used to compensate
the internal diodes yielding a constant clamp voltage over
temperature. Erratic operation due to noise pickup can result
if there is an excessive reduction of the I
voltage.
clamp
pk(max)
A narrow spike on the leading edge of the current
waveform can usually be observed and may cause the power
supply to exhibit an instability when the output is lightly
loaded. This spike is due to the power transformer
interwinding capacitance and output rectifier recovery time.
The addition of an RC filter on the Current Sense Input with
a time constant that approximates the spike duration will
usually eliminate the instability; refer to Figure 27.
the Output (Pin 6) when Pin 1 is at its lowest state (V ).
OL
This occurs when the power supply is operating and the load
http://onsemi.com
9
UC3842A, UC3843A, UC2842A, UC2843A
PIN FUNCTION DESCRIPTION
Pin
8−Pin
14−Pin
Function
Description
1
2
1
3
Compensation
This pin is Error Amplifier output and is made available for loop compensation.
Voltage
Feedback
This is the inverting input of the Error Amplifier. It is normally connected to the switching pow-
er supply output through a resistor divider.
3
4
5
7
Current Sense
A voltage proportional to inductor current is connected to this input. The PWM uses this infor-
mation to terminate the output switch conduction.
R /C
The Oscillator frequency and maximum Output duty cycle are programmed by connecting
T
T
resistor R to V and capacitor C to ground. Operation to 500 kHz is possible.
T
ref
T
5
6
−
GND
This pin is the combined control circuitry and power ground (8−pin package only).
10
Output
This output directly drives the gate of a power MOSFET. Peak currents up to 1.0 A are
sourced and sunk by this pin.
7
8
12
14
V
This pin is the positive supply of the control IC.
CC
V
This is the reference output. It provides charging current for capacitor C through
T
ref
resistor R .
T
−
−
8
Power Ground
This pin is a separate power ground return (14−pin package only) that is connected back
to the power source. It is used to reduce the effects of switching transient noise on the control
circuitry.
11
V
The Output high state (V ) is set by the voltage applied to this pin (14−pin package only).
C
OH
With a separate power source connection, it can reduce the effects of switching transient
noise on the control circuitry.
−
−
9
GND
NC
This pin is the control circuitry ground return (14−pin package only) and is connected back to
the power source ground.
2,4,6,13
No connection (14−pin package only). These pins are not internally connected.
Undervoltage Lockout
and has a typical rise and fall time of 50 ns with a 1.0 nF load.
Two undervoltage lockout comparators have been
incorporated to guarantee that the IC is fully functional
before the output stage is enabled. The positive power
supply terminal (V ) and the reference output (V ) are
Additional internal circuitry has been added to keep the
Output in a sinking mode whenever an undervoltage lockout
is active. This characteristic eliminates the need for an
external pull−down resistor.
CC
ref
each monitored by separate comparators. Each has built−in
hysteresis to prevent erratic output behavior as their
The SOIC−14 surface mount package provides separate
pins for V (output supply) and Power Ground. Proper
C
respective thresholds are crossed. The V
upper and lower thresholds are 16 V/10 V for the UCX842A,
comparator
implementation will significantly reduce the level of
switching transient noise imposed on the control circuitry.
CC
and 8.4 V/7.6 V for the UCX843A. The V comparator
This becomes particularly useful when reducing the I
ref
pk(max)
upper and lower thresholds are 3.6V/3.4 V. The large
hysteresis and low startup current of the UCX842A makes
it ideally suited in off−line converter applications where
efficient bootstrap startup techniques are required
(Figure 34). The UCX843A is intended for lower voltage dc
to dc converter applications. A 36 V zener is connected as
clamp level. The separate V supply input allows the
designer added flexibility in tailoring the drive voltage
C
independent of V . A zener clamp is typically connected
CC
to this input when driving power MOSFETs in systems
where V is greater than 20 V. Figure 26 shows proper
CC
power and control ground connections in a current sensing
power MOSFET application.
a shunt regulator form V to ground. Its purpose is to
CC
protect the IC from excessive voltage that can occur during
system startup. The minimum operating voltage for the
UCX842A is 11 V and 8.2 V for the UCX843A.
Reference
The 5.0 V bandgap reference is trimmed to 1.0%
tolerance at T = 25°C on the UC284XA, and 2.0% on the
UC384XA. Its primary purpose is to supply charging current
to the oscillator timing capacitor. The reference has short
circuit protection and is capable of providing in excess of
20 mA for powering additional control system circuitry.
J
Output
These devices contain a single totem pole output stage that
was specifically designed for direct drive of power
MOSFETs. It is capable of up to 1.0 A peak drive current
http://onsemi.com
10
UC3842A, UC3843A, UC2842A, UC2843A
DESIGN CONSIDERATIONS
Do not attempt to construct the converter on
wire−wrap or plug−in prototype boards. High Frequency
circuit layout techniques are imperative to prevent pulse
width jitter. This is usually caused by excessive noise
pick−up imposed on the Current Sense or Voltage Feedback
inputs. Noise immunity can be improved by lowering circuit
impedances at these points. The printed circuit layout should
contain a ground plane with low−current signal and
high−current switch and output grounds returning on
separate paths back to the input filter capacitor. Ceramic
(t ) decreases to (ꢂI + I m /m ) (m /m ). This perturbation
3 ꢂ 2 1 2 1
is multiplied by m .m on each succeeding cycle, alternately
2
1
increasing and decreasing the inductor current at switch
turn−on. Several oscillator cycles may be required before
the inductor current reaches zero causing the process to
commence again. If m /m is greater than 1, the converter
2
1
will be unstable. Figure 20B shows that by adding an
artificial ramp that is synchronized with the PWM clock to
the control voltage, the ꢂI perturbation will decrease to zero
on succeeding cycles. This compensation ramp (m ) must
3
bypass capacitors (0.1 ꢀ F) connected directly to V , V ,
have a slope equal to or slightly greater than m /2 for
CC
C
2
and V may be required depending upon circuit layout.
stability. With m /2 slope compensation, the average
ref
2
This provides a low impedance path for filtering the high
frequency noise. All high current loops should be kept as
short as possible using heavy copper runs to minimize
radiated EMI. The Error Amp compensation circuitry and
the converter output voltage divider should be located close
to the IC and as far as possible from the power switch and
other noise generating components.
inductor current follows the control voltage yielding true
current mode operation. The compensating ramp can be
derived from the oscillator and added to either the Voltage
Feedback or Current Sense inputs (Figure 33).
(A)
ꢂ I
Control Voltage
Current mode converters can exhibit subharmonic
oscillations when operating at a duty cycle greater than 50%
with continuous inductor current. This instability is
independent of the regulators closed−loop characteristics
and is caused by the simultaneous operating conditions of
fixed frequency and peak current detecting. Figure 20A
m2
m1
m
m
2
1
ꢂ I + ꢂ I
Inductor
Current
m
m
m
m
2
2
1
ꢂ I + ꢂ I
1
Oscillator Period
t
3
t
1
t
2
t
0
shows the phenomenon graphically. At t , switch
conduction begins, causing the inductor current to rise at a
0
(B)
Control Voltage
m3
slope of m . This slope is a function of the input voltage
1
divided by the inductance. At t , the Current Sense Input
reaches the threshold established by the control voltage.
This causes the switch to turn off and the current to decay at
1
ꢂ I
m1
m2
Inductor
Current
a slope of m until the next oscillator cycle. The unstable
2
Oscillator Period
condition can be shown if a perturbation is added to the
control voltage, resulting in a small ꢂI (dashed line). With
a fixed oscillator period, the current decay time is reduced,
t
t
t
6
4
5
Figure 20. Continuous Current Waveforms
and the minimum current at switch turn−on (t ) is increased
2
by ꢂI + ꢂI m2/m1. The minimum current at the next cycle
http://onsemi.com
11
UC3842A, UC3843A, UC2842A, UC2843A
V
ref
8(14)
R
8(14)
4(7)
R
R
Bias
R
A
R
T
R
Bias
4
8
R
B
5.0k
6
Osc
+
−
External
Sync
Input
Osc
+
4(7)
R
S
C
T
3
0.01
+
5
2
Q
+
+
−
−
+
2R
7
EA
47
−
2(3)
1(1)
2R
R
5.0k
1
EA
2(3)
1(1)
C
MC1455
R
5(9)
5(9)
To
Additional
UCX84XA’s
R
B
1.44
(R + 2R )C
The diode clamp is required if the Sync amplitude is large enough to
cause the bottom side of CT to go more than 300 mV below ground.
f =
D
max
=
R
A
+ 2R
B
A
B
Figure 22. External Duty Cycle Clamp and
Multi Unit Synchronization
Figure 21. External Clock Synchronization
V
CC
V
in
7(12)
+
5.0V
ref
−
+
8(14)
4(7)
R
R
−
Bias
+
−
+
7(11)
6(10)
5(8)
5.0V
ref
−
Q1
8(14)
R
R
Osc
Bias
+
+
V
−
Clamp
+
1.0mA
2R
S
R
+
−
Q
−
−
R2
+
Osc
EA
2(3)
1(1)
Comp/Latch
R
+
4(7)
2(3)
1.0V
3(5)
S
R
1.0mA
2R
+
Q
−
R
S
−
R1
+
EA
5(9)
R
1.0M
1.0V
1.67
2
R
R
2
1(1)
t
1
VClamp
RS
C
V
=
+ 0.33 x 10 −
3
I
=
Clamp
pk(max)
R
+ R
2
1
R
R
5(9)
+ 1
ꢀ 3600C in ꢀF
Soft−Start
Where: 0 ≤ V
≤ 1.0 V
Clamp
1
Figure 23. Adjustable Reduction of Clamp Level
Figure 24. Soft−Start Circuit
V
CC
R
I
r
pk DS(on)
S
V
in
V
CC
V
5 =
Pin
V
in
(12)
r
+ R
S
DM(on)
7(12)
If: SENSEFET = MTP10N10M
= 200
+
R
S
5.0V
−
+
ref
+
5.0V
ref
−
Then: V 5 = 0.075 I
pin
+
pk
8(14)
4(7)
R
R
−
+
D
SENSEFET
−
Bias
−
+
+
−
(11)
(10)
(8)
+
S
7(11)
6(10)
5(8)
−
−
Q1
Osc
G
K
M
+
V
Clamp
S
R
S
R
Q
1.0mA
2R
−
+
Q
+
−
−
Power Ground
To Input Source
Return
+
Comp/Latch
EA
2(3)
1(1)
Comp/Latch
R
R2
(5)
R
1.0V
S
3(5)
1/4 W
R
S
Control CIrcuitry
Ground:
To Pin (9)
5(9)
=
MPSA63
C
R1
1.67
2
VClamp
RS
V
=
Clamp
I
Where: 0 ≤ V
≤ 1.0 V
pk(max)
Clamp
R
R
Virtually lossless current sensing can be achieved with the implementation of a
SENSEFET power switch. For proper operation during over current conditions, a
+ 1
V
R R
1 2
C
1
t
= − In
1 −
C
Softstart
3V
R + R
1 2
reduction of the I
clamp level must be implemented. Refer to Figures 23 and 25.
Clamp
pk(max)
Figure 25. Adjustable Buffered Reduction of
Clamp Level with Soft−Start
Figure 26. Current Sensing Power MOSFET
http://onsemi.com
12
UC3842A, UC3843A, UC2842A, UC2843A
V
CC
V
V
in
CC
V
in
7(12)
7(12)
+
5.0V
+
ref
−
5.0V
+
ref
−
+
−
+
−
+
−
+
−
+
7(11)
6(10)
5(8)
7(11)
6(10)
5(8)
R
g
−
Q1
−
Q1
S
R
S
R
Q
−
Q
−
+
+
Comp/Latch
R
Comp/Latch
3(5)
3(5)
R
S
C
R
S
Series gate resistor R will damp any high frequency parasitic oscillations
g
caused by the MOSFET input capacitance and any series wiring inductance
in the gate−source circuit.
The addition of the RC filter will eliminate instability caused by the leading
edge spike on the current waveform.
Figure 27. Current Waveform Spike Suppression
Figure 28. MOSFET Parasitic Oscillations
I
B
V
in
+
V
V
in
CC
7(12)
0
Base
Charge
Removal
+
Isolation
Boundary
−
5.0V
ref
−
+
C
1
−
+
V
Waveforms
GS
−
Q1
+
7(11)
6(1)
5(8)
Q1
+
0
−
+
0
−
−
6(1)
5(8)
50% DC
25% DC
S
R
V
− 1.4
N
N
(pin 1)
P
Q
−
I
=
pk
+
S
3 R
S
R
Comp/Latch
3(5)
R
S
3(5)
C
N
S
R
S
N
p
The totem−pole output can furnish negative base current for enhanced
transistor turn−off, with the addition of capacitor C .
1
Figure 29. Bipolar Transistor Drive
Figure 30. Isolated MOSFET Drive
From V
O
2.5V
+
R
1.0mA
2R
i
2(3)
+
−
8(14)
4(7)
R
R
EA
R
d
C
I
Bias
R
f
R
1(1)
Osc
5(9)
+
1.0mA
2R
Error Amp compensation circuit for stabilizing any current−mode topology except
for boost and flyback converters operating with continuous inductor current.
+
−
EA
2(3)
1(1)
R
From V
O
2.5V
+
1.0mA
2R
R
p
2N
3905
2(3)
5(9)
MCR
101
R
i
+
−
EA
2N
3903
C
I
R
R
f
d
R
C
p
1(1)
5(9)
The MCR101 SCR must be selected for a holding of less than 0.5 mA at T
The simple two transistor circuit can be used in place of the SCR as shown. All
resistors are 10 k.
.
A(min)
Error Amp compensation circuit for stabilizing current−mode boost and flyback
topologies operating with continuous inductor current.
Figure 31. Latched Shutdown
Figure 32. Error Amplifier Compensation
http://onsemi.com
13
UC3842A, UC3843A, UC2842A, UC2843A
V
CC
V
in
7(12)
8(14)
+
−
5.0V
ref
+
R
R
R
T
Bias
−
+
−
MPS3904
+
7(11)
6(10)
5(8)
−
4(7)
R
O
Slope
Osc
From V
C
T
+
−m
1.0mA
S
R
R
i
2(3)
+
−
Q
−
+
2R
R
EA
Comp/Latch
C
f
1.0V
R
f
R
d
m
3(5)
R
S
1(1)
−3.0 m
5(9)
The buffered oscillator ramp can be resistively summed with either the voltage feedback or current sense inputs to provide slope compensation.
Figure 33. Slope Compensation
L1
MBR1635
+
4.7ꢃ
3300pF
1N4935
MDA
202
4.7k
250
5.0V/4.0A
T1
+
+
+
+
2200
1000
56k
115Va
c
5.0V RTN
12V/0.3A
MUR110
1000
1N4935
68
L2
10
7(12)
+
+
12V RTN
47
100
1000
10
L3
8(14)
+
−
+
+
5.0V
ref
−12V/0.3A
+
0.01
MUR110
680pF
1N4937
Bias
+
−
+
10k
7(11)
1N4937
2.7k
4(7)
2(3)
22ꢃ
Osc
6(10)
4700pF
+
MTP
4N50
L1 − 15 ꢀH at 5.0 A, Coilcraft Z7156.
L2, L3 − 25 ꢀH at 1.0 A, Coilcraft Z7157.
18k
S
+
−
Q
−
+
5(8)
3(5)
R
EA
Comp/Latch
4.7k
1.0k
T1 − Primary: 45 Turns # 26 AWG
T1 − Secondary 12 V: 9 Turns # 30 AWG
ꢁT1 − (2 strands) Bifiliar Wound
470pF
1(1)
0.5ꢃ
T1 − Secondary 5.0 V: 4 Turns (six strands)
ꢁT1 − #26 Hexfiliar Wound
5(9)
T1 − Secondary Feedback: 10 Turns #30 AWG
ꢁT1 − (2 strands) Bifiliar Wound
T1 − Core: Ferroxcube EC35−3C8
T1 − Bobbin: Ferroxcube EC35PCB1
T1 − Gap ≈ 0.01" for a primary inductance of 1.0 mH
Figure 34. 27 Watt Off−Line Flyback Regulator
Test
Conditions
Results
Line Regulation: 5.0 V
12 V
V
in
= 95 Vac to 130 Vac
ꢂ = 50 mV or 0.5%
ꢂ = 24 mV or 0.1%
Load Regulation: 5.0 V
12 V
V
V
= 115 Vac, I = 1.0 A to 4.0 A
ꢂ = 300 mV or 3.0%
ꢂ = 60 mV or 0.25%
in
out
= 115 Vac, I = 100 mA to 300 mA
in
out
Output Ripple:
5.0 V
12 V
V
in
= 115 Vac
40 mV
80 mV
pp
pp
Efficiency
V
in
= 115 Vac
70%
All outputs are at nominal load currents, unless otherwise noted.
http://onsemi.com
14
UC3842A, UC3843A, UC2842A, UC2843A
ORDERING INFORMATION
Device
†
Operating Temperature Range
Package
Shipping
UC3842AN
PDIP−8
UC3842ANG
PDIP−8
(Pb−Free)
50 Units / Rail
UC3842AN2
PDIP−8
UC3842AN2G
PDIP−8
(Pb−Free)
UC3842AD
SOIC−14
55 Units / Rail
55 Units / Rail
UC3842ADG
SOIC−14
(Pb−Free)
UC3842ADR2
SOIC−14
2500 / Tape & Reel
2500 / Tape & Reel
UC3842ADR2G
SOIC−14
(Pb−Free)
UC3843AN
PDIP−8
UC3843ANG
PDIP−8
(Pb−Free)
50 Units / Rail
UC3843AN2
PDIP−8
T = 0° to +70°C
A
UC3843AN2G
PDIP−8
(Pb−Free)
UC3843AD
SOIC−14
55 Units / Rail
55 Units / Rail
UC3843ADG
SOIC−14
(Pb−Free)
UC3843ADR2
SOIC−14
2500 / Tape & Reel
2500 / Tape & Reel
UC3843ADR2G
SOIC−14
(Pb−Free)
UC3843AD1
SOIC−8
98 Units / Rail
98 Units / Rail
UC3843AD1G
SOIC−8
(Pb−Free)
UC3843AD1R2
SOIC−8
UC3843AD1R2G
SOIC−8
(Pb−Free)
2500 / Tape & Reel
UC3843AD2R2
SOIC−14
UC3843AD2R2G
SOIC−14
(Pb−Free)
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
http://onsemi.com
15
UC3842A, UC3843A, UC2842A, UC2843A
ORDERING INFORMATION
Device
†
Operating Temperature Range
Package
Shipping
UC2842AN
PDIP−8
50 Units / Rail
50 Units / Rail
UC2842ANG
PDIP−8
(Pb−Free)
UC2842AD
SOIC−14
55 Units / Rail
55 Units / Rail
UC2842ADG
SOIC−14
(Pb−Free)
UC2842ADR2
SOIC−14
2500 / Tape & Reel
2500 / Tape & Reel
UC2842ADR2G
SOIC−14
(Pb−Free)
UC2843AN
PDIP−8
50 Units / Rail
50 Units / Rail
UC2843ANG
PDIP−8
(Pb−Free)
T = −25° to +85°C
A
UC2843AD
SOIC−14
55 Units / Rail
55 Units / Rail
UC2843ADG
SOIC−14
(Pb−Free)
UC2843ADR2
SOIC−14
2500 / Tape & Reel
2500 / Tape & Reel
UC2843ADR2G
SOIC−14
(Pb−Free)
UC2843AD1
SOIC−8
98 Units / Rail
98 Units / Rail
UC2843AD1G
SOIC−8
(Pb−Free)
UC2843AD1R2
SOIC−8
2500 / Tape & Reel
2500 / Tape & Reel
UC2843AD1R2G
SOIC−8
(Pb−Free)
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
MARKING DIAGRAMS
PDIP−8
N SUFFIX
CASE 626
SOIC−14
D SUFFIX
CASE 751A
SOIC−8
D1 SUFFIX
CASE 751
8
14
8
UCx84xAN
AWL
YYWWG
x843
ALYW
G
UCx84xADG
AWLYWW
1
1
1
x
= 2 or 3
A
= Assembly Location
WL, L = Wafer Lot
YY, Y = Year
WW, W = Work Week
G or G = Pb−Free Package
http://onsemi.com
16
UC3842A, UC3843A, UC2842A, UC2843A
PACKAGE DIMENSIONS
PDIP−8
N SUFFIX
CASE 626−05
ISSUE L
NOTES:
1. DIMENSION L TO CENTER OF LEAD WHEN
FORMED PARALLEL.
8
5
2. PACKAGE CONTOUR OPTIONAL (ROUND OR
SQUARE CORNERS).
−B−
3. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
1
4
MILLIMETERS
INCHES
DIM MIN
MAX
10.16
6.60
4.45
0.51
1.78
MIN
MAX
0.400
0.260
0.175
0.020
0.070
A
B
C
D
F
9.40
6.10
3.94
0.38
1.02
0.370
0.240
0.155
0.015
0.040
F
−A−
NOTE 2
L
G
H
J
2.54 BSC
0.100 BSC
0.76
0.20
2.92
1.27
0.30
3.43
0.030
0.008
0.115
0.050
0.012
0.135
K
L
C
7.62 BSC
0.300 BSC
M
N
−−−
0.76
10
_
1.01
−−−
0.030
10
0.040
_
J
−T−
SEATING
PLANE
N
M
D
K
G
H
M
M
M
B
0.13 (0.005)
T A
SOIC−14
D SUFFIX
CASE 751A−03
ISSUE G
NOTES:
−A−
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS A AND B DO NOT INCLUDE
MOLD PROTRUSION.
14
8
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.
−B−
P 7 PL
5. DIMENSION D DOES NOT INCLUDE
DAMBAR PROTRUSION. ALLOWABLE
DAMBAR PROTRUSION SHALL BE 0.127
(0.005) TOTAL IN EXCESS OF THE D
DIMENSION AT MAXIMUM MATERIAL
CONDITION.
M
M
B
0.25 (0.010)
7
1
G
F
R X 45
_
C
MILLIMETERS
DIM MIN MAX
INCHES
MIN MAX
A
B
C
D
F
G
J
K
M
P
R
8.55
3.80
1.35
0.35
0.40
8.75 0.337 0.344
4.00 0.150 0.157
1.75 0.054 0.068
0.49 0.014 0.019
1.25 0.016 0.049
0.050 BSC
0.25 0.008 0.009
0.25 0.004 0.009
−T−
SEATING
PLANE
J
M
K
D 14 PL
M
S
S
0.25 (0.010)
T B
A
1.27 BSC
0.19
0.10
0
7
0
7
_
_
_
_
5.80
0.25
6.20 0.228 0.244
0.50 0.010 0.019
http://onsemi.com
17
UC3842A, UC3843A, UC2842A, UC2843A
PACKAGE DIMENSIONS
SOIC−8
D1 SUFFIX
CASE 751−07
ISSUE AG
NOTES:
−X−
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
A
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A AND B DO NOT INCLUDE
MOLD PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 (0.005) TOTAL
IN EXCESS OF THE D DIMENSION AT
MAXIMUM MATERIAL CONDITION.
6. 751−01 THRU 751−06 ARE OBSOLETE. NEW
STANDARD IS 751−07.
8
5
4
S
M
M
B
0.25 (0.010)
Y
1
K
−Y−
G
MILLIMETERS
DIM MIN MAX
INCHES
MIN
MAX
0.197
0.157
0.069
0.020
C
N X 45
_
A
B
C
D
G
H
J
K
M
N
S
4.80
3.80
1.35
0.33
5.00 0.189
4.00 0.150
1.75 0.053
0.51 0.013
SEATING
PLANE
−Z−
0.10 (0.004)
1.27 BSC
0.050 BSC
M
0.10
0.19
0.40
0
0.25 0.004
0.25 0.007
1.27 0.016
0.010
0.010
0.050
8
0.020
0.244
J
H
D
8
0
_
_
_
_
M
S
S
X
0.25 (0.010)
Z
Y
0.25
5.80
0.50 0.010
6.20 0.228
SOLDERING FOOTPRINT*
1.52
0.060
7.0
0.275
4.0
0.155
0.6
0.024
1.270
0.050
mm
inches
ǒ
Ǔ
SCALE 6:1
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
SENSEFET is a trademark of Semiconductor Components Industries, LLC.
ON Semiconductor and
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All
operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights
nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications
intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should
Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates,
and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death
associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal
Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
PUBLICATION ORDERING INFORMATION
LITERATURE FULFILLMENT:
N. American Technical Support: 800−282−9855 Toll Free
USA/Canada
ON Semiconductor Website: http://onsemi.com
Order Literature: http://www.onsemi.com/litorder
Literature Distribution Center for ON Semiconductor
P.O. Box 61312, Phoenix, Arizona 85082−1312 USA
Phone: 480−829−7710 or 800−344−3860 Toll Free USA/Canada
Fax: 480−829−7709 or 800−344−3867 Toll Free USA/Canada
Email: orderlit@onsemi.com
Japan: ON Semiconductor, Japan Customer Focus Center
2−9−1 Kamimeguro, Meguro−ku, Tokyo, Japan 153−0051
Phone: 81−3−5773−3850
For additional information, please contact your
local Sales Representative.
UC3842A/D
相关型号：
UC2842AY
Switching Controller, Current-mode, 1A, 500kHz Switching Freq-Max, BIPolar, CDIP8, CERAMIC, DIP-8
MICROSEMI
©2020 ICPDF网 联系我们和版权申明