UC2842BD1G 概述
High Performance Current Mode Controllers 高性能电流模式控制器 AC-DC转换器 开关式稳压器或控制器
UC2842BD1G 规格参数
是否无铅: | 不含铅 | 是否Rohs认证: | 符合 |
生命周期: | Active | 零件包装代码: | SOIC |
包装说明: | HALOGEN AND LEAD FREE, PLASTIC, SOIC-8 | 针数: | 8 |
Reach Compliance Code: | compliant | ECCN代码: | EAR99 |
HTS代码: | 8542.39.00.01 | Factory Lead Time: | 1 week |
风险等级: | 1.02 | Is Samacsys: | N |
模拟集成电路 - 其他类型: | SWITCHING CONTROLLER | 控制模式: | CURRENT-MODE |
控制技术: | PULSE WIDTH MODULATION | 最大输入电压: | 25 V |
最小输入电压: | 12 V | 标称输入电压: | 15 V |
JESD-30 代码: | R-PDSO-G8 | JESD-609代码: | e3 |
长度: | 4.9 mm | 湿度敏感等级: | 1 |
功能数量: | 1 | 端子数量: | 8 |
最高工作温度: | 85 °C | 最低工作温度: | -25 °C |
最大输出电流: | 1 A | 封装主体材料: | PLASTIC/EPOXY |
封装代码: | SOP | 封装等效代码: | SOP8,.25 |
封装形状: | RECTANGULAR | 封装形式: | SMALL OUTLINE |
峰值回流温度(摄氏度): | 260 | 认证状态: | Not Qualified |
座面最大高度: | 1.75 mm | 子类别: | Switching Regulator or Controllers |
表面贴装: | YES | 切换器配置: | SINGLE |
最大切换频率: | 500 kHz | 技术: | BIPOLAR |
温度等级: | OTHER | 端子面层: | Tin (Sn) |
端子形式: | GULL WING | 端子节距: | 1.27 mm |
端子位置: | DUAL | 处于峰值回流温度下的最长时间: | 40 |
宽度: | 3.9 mm | Base Number Matches: | 1 |
UC2842BD1G 数据手册
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PDF下载UC3842B, UC3843B,
UC2842B, UC2843B,
NCV3843BV
High Performance Current
Mode Controllers
The UC3842B, UC3843B series are high performance fixed
frequency current mode controllers. They are specifically designed for
Off−Line and DC−DC converter applications offering the designer a
cost−effective solution with minimal external components. These
integrated circuits feature a trimmed oscillator for precise duty cycle
control, a temperature compensated reference, high gain error
amplifier, current sensing comparator, and a high current totem pole
output ideally suited for driving a power MOSFET.
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PDIP−8
N SUFFIX
CASE 626
8
1
Also included are protective features consisting of input and
reference undervoltage lockouts each with hysteresis, cycle−by−cycle
current limiting, programmable output deadtime, and a latch for single
pulse metering.
These devices are available in an 8−pin dual−in−line and surface
mount (SOIC−8) plastic package as well as the 14−pin plastic surface
mount (SOIC−14). The SOIC−14 package has separate power and
ground pins for the totem pole output stage.
SOIC−14
D SUFFIX
CASE 751A
14
1
SOIC−8
D1 SUFFIX
8
The UCX842B has UVLO thresholds of 16 V (on) and 10 V (off),
ideally suited for off−line converters. The UCX843B is tailored for
lower voltage applications having UVLO thresholds of 8.5 V (on) and
7.6 V (off).
CASE 751
1
PIN CONNECTIONS
Features
• Trimmed Oscillator for Precise Frequency Control
• Oscillator Frequency Guaranteed at 250 kHz
• Current Mode Operation to 500 kHz
• Automatic Feed Forward Compensation
• Latching PWM for Cycle−By−Cycle Current Limiting
• Internally Trimmed Reference with Undervoltage Lockout
• High Current Totem Pole Output
1
2
3
4
8
7
6
5
Compensation
Voltage Feedback
Current Sense
V
V
ref
CC
Output
GND
R /C
T
T
(Top View)
Compensation
1
2
3
4
5
6
7
14
13
12
11
10
9
V
ref
NC
Voltage Feedback
NC
NC
• Undervoltage Lockout with Hysteresis
• Low Startup and Operating Current
• Pb−Free Packages are Available
V
V
CC
C
Current Sense
NC
Output
GND
V
7(12)
CC
8
R /C
T
Power Ground
T
V
V
CC
ref
5.0V
Reference
(Top View)
Undervoltage
Lockout
8(14)
R
R
V
ref
V
C
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 17 of this data sheet.
Undervoltage
Lockout
7(11)
R /C
T
Output
T
Oscillator
6(10)
4(7)
Latching
PWM
DEVICE MARKING INFORMATION
See general marking information in the device marking
section on page 19 of this data sheet.
Power
Ground
5(8)
Voltage
Feedback
Input
+
−
2(3)
Output
Compensation
Error
Amplifier
Current
Sense
Input
3(5)
1(1)
GND 5(9)
Pin numbers in parenthesis are for the D suffix SOIC−14 package.
Figure 1. Simplified Block Diagram
©
Semiconductor Components Industries, LLC, 2007
1
Publication Order Number:
February, 2007 − Rev. 9
UC3842B/D
UC3842B, UC3843B, UC2842B, UC2843B, NCV3843BV
MAXIMUM RATINGS
Rating
Symbol
, V
Value
Unit
Bias and Driver Voltages (Zero Series Impedance, see also Total Device spec)
Total Power Supply and Zener Current
V
30
V
CC
C
(I + I )
30
mA
A
CC
Z
Output Current, Source or Sink
I
1.0
5.0
O
Output Energy (Capacitive Load per Cycle)
Current Sense and Voltage Feedback Inputs
Error Amp Output Sink Current
W
mJ
V
V
in
− 0.3 to + 5.5
10
I
mA
O
Power Dissipation and Thermal Characteristics
D Suffix, Plastic Package, SOIC−14 Case 751A
Maximum Power Dissipation @ T = 25°C
P
862
145
mW
°C/W
A
D
Thermal Resistance, Junction−to−Air
R
q
JA
D1 Suffix, Plastic Package, SOIC−8 Case 751
Maximum Power Dissipation @ T = 25°C
Thermal Resistance, Junction−to−Air
N Suffix, Plastic Package, Case 626
P
702
178
mW
°C/W
A
D
R
q
JA
Maximum Power Dissipation @ T = 25°C
1.25
100
W
°C/W
P
A
D
Thermal Resistance, Junction−to−Air
R
q
JA
Operating Junction Temperature
T
+150
°C
°C
J
Operating Ambient Temperature
T
A
UC3842B, UC3843B
0 to 70
UC2842B, UC2843B
UC3842BV, UC3843BV
NCV3843BV
− 25 to + 85
−40 to +105
−40 to +125
Storage Temperature Range
T
stg
− 65 to +150
°C
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
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UC3842B, UC3843B, UC2842B, UC2843B, NCV3843BV
ELECTRICAL CHARACTERISTICS (V = 15 V [Note 1], R = 10 k, C = 3.3 nF. For typical values T = 25°C, for min/max values
CC
T
T
A
T is the operating ambient temperature range that applies [Note 2], unless otherwise noted.)
A
UC284XB
UC384XB, XBV
Characteristics
REFERENCE SECTION
Reference Output Voltage (I = 1.0 mA, T = 25°C)
Symbol
Min
Typ
Max
Min
Typ
Max
Unit
V
ref
4.95
−
5.0
2.0
3.0
0.2
−
5.05
20
25
−
4.9
−
5.0
2.0
3.0
0.2
−
5.1
20
V
mV
mV
mV/°C
V
O
J
Line Regulation (V = 12 V to 25 V)
Reg
line
CC
Load Regulation (I = 1.0 mA to 20 mA)
Reg
T
−
−
25
O
load
Temperature Stability
−
−
−
S
Total Output Variation over Line, Load, and Temperature
V
ref
4.9
−
5.1
−
4.82
−
5.18
−
Output Noise Voltage (f = 10 Hz to 10 kHz, T = 25°C)
V
50
50
mV
J
n
Long Term Stability (T = 125°C for 1000 Hours)
S
−
5.0
− 85
−
−
5.0
− 85
−
mV
mA
A
Output Short Circuit Current
I
− 30
−180
− 30
−180
SC
OSCILLATOR SECTION
Frequency
f
kHz
OSC
49
48
225
52
−
250
55
56
275
49
48
225
52
−
250
55
56
275
T = 25°C
J
T = T
to T
A
low
high
T = 25°C (R = 6.2 k, C = 1.0 nF)
J
T
T
Frequency Change with Voltage (V = 12 V to 25 V)
Df
Df
/DV
/DT
−
−
−
0.2
1.0
1.6
1.0
−
−
−
−
0.2
0.5
1.6
1.0
−
%
%
CC
OSC
Frequency Change with Temperature, T = T
to T
high
A
low
OSC
Oscillator Voltage Swing (Peak−to−Peak)
V
−
−
V
OSC
Discharge Current (V
= 2.0 V)
I
mA
OSC
low
dischg
7.8
7.5
−
8.3
−
−
8.8
8.8
−
7.8
7.6
7.2
8.3
−
−
8.8
8.8
8.8
T = 25°C, T = T
to T
J
A
high
UC284XB, UC384XB
to T UC384XBV
T = T
A
low
high
ERROR AMPLIFIER SECTION
Voltage Feedback Input (V = 2.5 V)
V
2.45
−
2.5
− 0.1
90
2.55
−1.0
−
2.42
−
2.5
− 0.1
90
2.58
− 2.0
−
V
mA
O
FB
Input Bias Current (V = 5.0 V)
I
FB
IB
Open Loop Voltage Gain (V = 2.0 V to 4.0 V)
A
VOL
65
65
dB
O
Unity Gain Bandwidth (T = 25°C)
BW
0.7
60
1.0
−
0.7
60
1.0
−
MHz
dB
J
Power Supply Rejection Ratio (V = 12 V to 25 V)
PSRR
70
−
70
−
CC
Output Current
mA
I
2.0
− 0.5
12
−1.0
−
−
2.0
− 0.5
12
−1.0
−
−
Sink (V = 1.1 V, V = 2.7 V)
Sink
O
FB
I
Source (V = 5.0 V, V = 2.3 V)
Source
O
FB
Output Voltage Swing
V
V
5.0
6.2
−
5.0
6.2
−
High State (R = 15 k to ground, V = 2.3 V)
OH
L
FB
V
Low State (R = 15 k to V , V = 2.7 V)
OL
L
ref
FB
−
−
0.8
−
1.1
−
−
−
0.8
0.8
1.1
1.2
UC284XB, UC384XB
UC384XBV
CURRENT SENSE SECTION
Current Sense Input Voltage Gain (Notes 3 and 4)
UC284XB, UC384XB
UC384XBV
A
V/V
V
V
2.85
−
3.0
−
3.15
−
2.85
2.85
3.0
3.0
3.15
3.25
Maximum Current Sense Input Threshold (Note 3)
V
th
0.9
−
1.0
−
1.1
−
0.9
0.85
1.0
1.0
1.1
1.1
UC284XB, UC384XB
UC384XBV
Power Supply Rejection Ratio (V = 12 V to 25 V, Note 3)
PSRR
−
−
−
70
−
−
−
−
70
−
dB
mA
ns
CC
Input Bias Current
I
− 2.0
150
−10
300
− 2.0
150
−10
300
IB
t
PLH(In/Out)
Propagation Delay (Current Sense Input to Output)
1. Adjust V above the Startup threshold before setting to 15 V.
CC
2. Low duty cycle pulse techniques are used during test to maintain junction temperature as close to ambient as possible.
T
T
= 0°C for UC3842B, UC3843B; −25°C for UC2842B, UC2843B; −40°C for UC3842BV, UC3843BV
low
high
= +70°C for UC3842B, UC3843B; +85°C for UC2842B, UC2843B; +105°C for UC3842BV, UC3843BV
NCV3843BV: T = −40°C, T
= +105°C. Guaranteed by design. NCV prefix is for automotive and other applications requiring site and
low
high
change control.
3. This parameter is measured at the latch trip point with V = 0 V.
FB
DV Output Compensation
DV Current Sense Input
4. Comparator gain is defined as: A
V
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UC3842B, UC3843B, UC2842B, UC2843B, NCV3843BV
ELECTRICAL CHARACTERISTICS (V = 15 V [Note 5], R = 10 k, C = 3.3 nF. For typical values T = 25°C, for min/max values
CC
T
T
A
T is the operating ambient temperature range that applies [Note 6], unless otherwise noted.)
A
UC284XB
Typ
UC384XB, XBV
Characteristics
Symbol
Min
Max
Min
Typ
Max
Unit
OUTPUT SECTION
Output Voltage
V
V
−
−
−
13
−
12
0.1
1.6
−
13.5
−
0.4
2.2
−
−
−
−
−
−
13
12.9
12
0.1
1.6
1.6
13.5
13.5
13.4
0.4
2.2
2.3
−
−
−
Low State (I
= 20 mA)
= 200 mA)
OL
Sink
(I
High State (I
(I
UC284XB, UC384XB
UC384XBV
UC284XB, UC384XB
UC384XBV
Sink
V
OH
= 20 mA)
Source
13.4
−
= 200 mA)
Source
Output Voltage with UVLO Activated (V = 6.0 V, I
= 1.0 mA)
V
−
−
−
0.1
50
50
1.1
150
150
−
−
−
0.1
50
50
1.1
150
150
V
CC
Sink
OL(UVLO)
Output Voltage Rise Time (C = 1.0 nF, T = 25°C)
t
ns
ns
L
J
r
Output Voltage Fall Time (C = 1.0 nF, T = 25°C)
t
L
J
f
UNDERVOLTAGE LOCKOUT SECTION
Startup Threshold (V
)
V
V
V
CC
th
15
7.8
16
8.4
17
9.0
14.5
7.8
16
8.4
17.5
9.0
UCX842B, BV
UCX843B, BV
Minimum Operating Voltage After Turn−On (V
)
CC
V
CC(min)
9.0
7.0
10
7.6
11
8.2
8.5
7.0
10
7.6
11.5
8.2
UCX842B, BV
UCX843B, BV
PWM SECTION
Duty Cycle
%
DC
94
−
−
96
−
−
−
−
0
94
93
−
96
96
−
−
−
0
Maximum UC284XB, UC384XB
Maximum UC384XBV
Minimum
(max)
DC
(min)
TOTAL DEVICE
Power Supply Current
I
+ I
mA
V
CC
C
−
−
0.3
12
36
0.5
17
−
−
−
0.3
12
36
0.5
17
−
Startup (V = 6.5 V for UCX843B,
CC
Startup V 14 V for UCX842B, BV)
CC
(Note 5)
Power Supply Zener Voltage (I = 25 mA)
V
30
30
CC
Z
5. Adjust V above the Startup threshold before setting to 15 V.
CC
6. Low duty cycle pulse techniques are used during test to maintain junction temperature as close to ambient as possible.
T
T
= 0°C for UC3842B, UC3843B; −25°C for UC2842B, UC2843B; −40°C for UC3842BV, UC3843BV
high
low
= +70°C for UC3842B, UC3843B; +85°C for UC2842B, UC2843B; +105°C for UC3842BV, UC3843BV
NCV3843BV: T = −40°C, T
change control.
= +125°C. Guaranteed by design. NCV prefix is for automotive and other applications requiring site and
low
high
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UC3842B, UC3843B, UC2842B, UC2843B, NCV3843BV
80
50
100
1. C = 10 nF
T
2. C = 5.0 nF
4
50
T
3. C = 2.0 nF
3
T
4. C = 1.0 nF
2
T
5. C = 500 pF
20
20
10
T
6. C = 200 pF
1
T
7. C = 100 pF
T
8.0
5.0
7
6
5
5.0
V
T
= 15 V
CC
= 25°C
2.0
0.8
V
T
A
= 15 V
CC
= 25°C
2.0
1.0
A
10 k
20 k
50 k
100 k
200 k
500 k
1.0 M
10 k
20 k
50 k
100 k
200 k
500 k
1.0 M
f , OSCILLATOR FREQUENCY (kHz)
OSC
f , OSCILLATOR FREQUENCY (kHz)
OSC
Ǔ )1ǒCt
Ǔ
Idis*I
Rt
Where: Vosc = 1.7 V
= Vref/Rt
Freq +
Vosc
Vosc
ǒ
Ct
I
Rt
I
Rt
Idis = 8.3 mA
Figure 2. Timing Resistor
versus Oscillator Frequency
Figure 3. Output Deadtime
versus Oscillator Frequency
9.0
8.5
8.0
7.5
7.0
100
90
80
70
60
50
40
V
V
= 15 V
= 2.0 V
CC
OSC
I
= 7.5 mA
dischg
I
= 8.8 mA
dischg
V
C
T
= 15 V
= 3.3 nF
= 25°C
CC
T
A
−ꢀ55
−ꢀ25
0
25
50
75
100
125
0.8 1.0
2.0
3.0
4.0 5.0 6.0 7.0 8.0
T , AMBIENT TEMPERATURE (°C)
A
R , TIMING RESISTOR (kW)
T
Figure 4. Oscillator Discharge Current
versus Temperature
Figure 5. Maximum Output Duty Cycle
versus Timing Resistor
2.55 V
V
A
V
= 15 V
= −1.0
V
A
V
= 15 V
CC
= −1.0
CC
3.0 V
T
A
= 25°C
T
A
= 25°C
2.50 V
2.45 V
2.5 V
2.0 V
0.5 ms/DIV
1.0 ms/DIV
Figure 6. Error Amp Small Signal
Transient Response
Figure 7. Error Amp Large Signal
Transient Response
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UC3842B, UC3843B, UC2842B, UC2843B, NCV3843BV
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UC3842B, UC3843B, UC2842B, UC2843B, NCV3843BV
100
80
60
40
20
1.2
1.0
0.8
0.6
0.4
0.2
0
0
V
V
= 15 V
= 2.0 V to 4.0 V
CC
V
= 15 V
CC
O
30
60
90
120
R = 100 K
L
T
A
Gain
= 25°C
T
= 25°C
A
T
= 125°C
Phase
A
T
A
= −55°C
0
150
180
−ꢀ20
10
100
1.0 k
10 k
100 k
1.0 M
10 M
0
2.0
4.0
6.0
8.0
f, FREQUENCY (Hz)
V , ERROR AMP OUTPUT VOLTAGE (V)
O
Figure 8. Error Amp Open Loop Gain and
Phase versus Frequency
Figure 9. Current Sense Input Threshold
versus Error Amp Output Voltage
0
−ꢀ4.0
−ꢀ8.0
−12
110
V
= 15 V
CC
V
= 15 V
CC
R ≤ 0.1 W
L
90
70
50
T
A
= −55°C
T
A
= 125°C
−16
−ꢀ20
−ꢀ24
T
= 25°C
A
0
20
I
40
60
80
100
120
−ꢀ55
−ꢀ25
0
25
50
75
100
125
, REFERENCE SOURCE CURRENT (mA)
T , AMBIENT TEMPERATURE (°C)
ref
A
Figure 10. Reference Voltage Change
versus Source Current
Figure 11. Reference Short Circuit Current
versus Temperature
V
= 15 V
= 1.0 mA to 20 mA
= 25°C
CC
V
T
= 12 V to 25
CC
= 25°C
I
O
A
T
A
2.0 ms/DIV
2.0 ms/DIV
Figure 12. Reference Load Regulation
Figure 13. Reference Line Regulation
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UC3842B, UC3843B, UC2842B, UC2843B, NCV3843BV
0
−1.0
−ꢀ2.0
Source Saturation
(Load to Ground)
V
= 15 V
80 ms Pulsed Load
CC
V
CC
T
= 25°C
A
120 Hz Rate
V
= 15 V
C = 1.0 nF
= 25°C
CC
90%
L
T
A
T
= −ꢀ55°C
A
3.0
2.0
1.0
0
T
A
= −ꢀ55°C
T
= 25°C
A
Sink Saturation
)
GND
600
10%
(Load to V
CC
0
200
400
800
50 ns/DIV
I , OUTPUT LOAD CURRENT (mA)
O
Figure 14. Output Saturation Voltage
versus Load Current
Figure 15. Output Waveform
25
20
15
10
5
V
= 30 V
C = 15 pF
= 25°C
CC
L
T
A
R = 10 k
T
C
= 3.3 nF
= 0 V
T
V
FB
I
T
= 0 V
Sense
= 25°C
A
0
0
10
20
, SUPPLY VOLTAGE (V)
30
40
100 ns/DIV
V
CC
Figure 16. Output Cross Conduction
Figure 17. Supply Current versus Supply Voltage
PIN FUNCTION DESCRIPTION
8−Pin
14−Pin
Function
Description
1
2
1
3
Compensation
This pin is the Error Amplifier output and is made available for loop compensation.
Voltage
Feedback
This is the inverting input of the Error Amplifier. It is normally connected to the switching power
supply output through a resistor divider.
3
4
5
7
Current
Sense
A voltage proportional to inductor current is connected to this input. The PWM uses this
information to terminate the output switch conduction.
R /C
The Oscillator frequency and maximum Output duty cycle are programmed by connecting resistor
T
T
R to V and capacitor C to ground. Operation to 500 kHz is possible.
T
ref
T
5
6
GND
This pin is the combined control circuitry and power ground.
10
Output
This output directly drives the gate of a power MOSFET. Peak currents up to 1.0 A are sourced
and sunk by this pin.
7
8
12
14
8
V
This pin is the positive supply of the control IC.
CC
V
This is the reference output. It provides charging current for capacitor C through resistor R .
T T
ref
Power
Ground
This pin is a separate power ground return that is connected back to the power source. It is used
to reduce the effects of switching transient noise on the control circuitry.
11
V
The Output high state (V ) is set by the voltage applied to this pin. With a separate power
C
OH
source connection, it can reduce the effects of switching transient noise on the control circuitry.
This pin is the control circuitry ground return and is connected back to the power source ground.
No connection. These pins are not internally connected.
9
GND
NC
2,4,6,1
3
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8
UC3842B, UC3843B, UC2842B, UC2843B, NCV3843BV
OPERATING DESCRIPTION
The UC3842B, UC3843B series are high performance,
This occurs when the power supply is operating and the load
is removed, or at the beginning of a soft−start interval
(Figures 24, 25). The Error Amp minimum feedback
resistance is limited by the amplifier’s source current
fixed frequency, current mode controllers. They are
specifically designed for Off−Line and DC−to−DC
converter applications offering the designer a cost−effective
solution with minimal external components.
representative block diagram is shown in Figure 18.
A
(0.5 mA) and the required output voltage (V ) to reach the
comparator’s 1.0 V clamp level:
OH
3.0 (1.0 V) + 1.4 V
Rf(min)
≈
= 8800 W
Oscillator
0.5 mA
The oscillator frequency is programmed by the values
selected for the timing components R and C . Capacitor C
is charged from the 5.0 V reference through resistor R to
approximately 2.8 V and discharged to 1.2 V by an internal
current sink. During the discharge of C , the oscillator
generates an internal blanking pulse that holds the center
input of the NOR gate high. This causes the Output to be in
a low state, thus producing a controlled amount of output
deadtime. Figure 2 shows R versus Oscillator Frequency
and Figure 3, Output Deadtime versus Frequency, both for
T
T
T
Current Sense Comparator and PWM Latch
T
The UC3842B, UC3843B operate as a current mode
controller, whereby output switch conduction is initiated by
the oscillator and terminated when the peak inductor current
reaches the threshold level established by the Error
Amplifier Output/Compensation (Pin 1). Thus the error
T
signal controls the peak inductor current on
a
T
cycle−by−cyclebasis. The Current Sense Comparator PWM
Latch configuration used ensures that only a single pulse
appears at the Output during any given oscillator cycle. The
inductor current is converted to a voltage by inserting the
given values of C . Note that many values of R and C will
T
T
T
give the same oscillator frequency but only one combination
will yield a specific output deadtime at a given frequency.
The oscillator thresholds are temperature compensated to
within 6% at 50 kHz. Also because of industry trends
moving the UC384X into higher and higher frequency
applications, the UC384XB is guaranteed to within 10% at
250 kHz. These internal circuit refinements minimize
variations of oscillator frequency and maximum output duty
cycle. The results are shown in Figures 4 and 5.
ground−referenced sense resistor R in series with the
S
source of output switch Q1. This voltage is monitored by the
Current Sense Input (Pin 3) and compared to a level derived
from the Error Amp Output. The peak inductor current under
normal operating conditions is controlled by the voltage at
pin 1 where:
V(Pin 1) − 1.4 V
Ipk
=
3 RS
In many noise−sensitive applications it may be desirable
to frequency−lock the converter to an external system clock.
This can be accomplished by applying a clock signal to the
circuit shown in Figure 21. For reliable locking, the
free−running oscillator frequency should be set about 10%
less than the clock frequency. A method for multi−unit
synchronization is shown in Figure 22. By tailoring the
clock waveform, accurate Output duty cycle clamping can
be achieved.
Abnormal operating conditions occur when the power
supply output is overloaded or if output voltage sensing is
lost. Under these conditions, the Current Sense Comparator
threshold will be internally clamped to 1.0 V. Therefore the
maximum peak switch current is:
1.0 V
RS
Ipk(max)
=
When designing a high power switching regulator it
becomes desirable to reduce the internal clamp voltage in
Error Amplifier
order to keep the power dissipation of R to a reasonable
S
A fully compensated Error Amplifier with access to the
inverting input and output is provided. It features a typical
DC voltage gain of 90 dB, and a unity gain bandwidth of
1.0 MHz with 57 degrees of phase margin (Figure 8). The
non−inverting input is internally biased at 2.5 V and is not
pinned out. The converter output voltage is typically divided
down and monitored by the inverting input. The maximum
input bias current is −2.0 mA which can cause an output
voltage error that is equal to the product of the input bias
current and the equivalent input divider source resistance.
The Error Amp Output (Pin 1) is provided for external
loop compensation (Figure 32). The output voltage is offset
by two diode drops (≈1.4 V) and divided by three before it
connects to the non−inverting input of the Current Sense
Comparator. This guarantees that no drive pulses appear at
level. A simple method to adjust this voltage is shown in
Figure 23. The two external diodes are used to compensate
the internal diodes, yielding a constant clamp voltage over
temperature. Erratic operation due to noise pickup can result
if there is an excessive reduction of the I
voltage.
clamp
pk(max)
A narrow spike on the leading edge of the current
waveform can usually be observed and may cause the power
supply to exhibit an instability when the output is lightly
loaded. This spike is due to the power transformer
interwinding capacitance and output rectifier recovery time.
The addition of an RC filter on the Current Sense Input with
a time constant that approximates the spike duration will
usually eliminate the instability (refer to Figure 27).
the Output (Pin 6) when pin 1 is at its lowest state (V ).
OL
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9
UC3842B, UC3843B, UC2842B, UC2843B, NCV3843BV
V
V
in
CC
V
CC 7(12)
36V
V
ref
Reference
Regulator
8(14)
(See
Text)
+
−
V
CC
UVLO
R
R
V
Internal
Bias
C
2.5V
R
C
T
7(11)
+
3.6V
V
ref
UVLO
−
Output
Q1
Oscillator
4(7)
6(10)
T
+
1.0mA
S
Power Ground
2R
Q
Voltage
Feedback
Input
PWM
Latch
R
5(8)
2(3)
1(1)
R
Error
Amplifier
1.0V
Current Sense Input
Output/
Compensation
Current Sense
Comparator
3(5)
R
S
GND 5(9)
Pin numbers adjacent to terminals are for the 8−pin dual−in−line package.
Pin numbers in parenthesis are for the D suffix SOIC−14 package.
= Sink Only Positive True Logic
Figure 18. Representative Block Diagram
Capacitor C
T
Latch
ꢁSet" Input
Output/
Compensation
Current Sense
Input
Latch
ꢁReset" Input
Output
Small R /Large C
T
T
Large R /Small C
T
T
Figure 19. Timing Diagram
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10
UC3842B, UC3843B, UC2842B, UC2843B, NCV3843BV
Undervoltage Lockout
Design Considerations
Two undervoltage lockout comparators have been
incorporated to guarantee that the IC is fully functional
before the output stage is enabled. The positive power
Do not attempt to construct the converter on
wire−wrap or plug−in prototype boards. High frequency
circuit layout techniques are imperative to prevent
pulse−width jitter. This is usually caused by excessive noise
pick−up imposed on the Current Sense or Voltage Feedback
inputs. Noise immunity can be improved by lowering circuit
impedances at these points. The printed circuit layout should
contain a ground plane with low−current signal and
high−current switch and output grounds returning on
separate paths back to the input filter capacitor. Ceramic
supply terminal (V ) and the reference output (V ) are
CC
ref
each monitored by separate comparators. Each has built−in
hysteresis to prevent erratic output behavior as their
respective thresholds are crossed. The V
comparator
CC
upper and lower thresholds are 16 V/10 V for the UCX842B,
and 8.4 V/7.6 V for the UCX843B. The V comparator
ref
upper and lower thresholds are 3.6 V/3.4 V. The large
hysteresis and low startup current of the UCX842B makes
it ideally suited in off−line converter applications where
efficient bootstrap startup techniques are required
(Figure 34). The UCX843B is intended for lower voltage
DC−to−DC converter applications. A 36 V Zener is
bypass capacitors (0.1 mF) connected directly to V , V ,
CC
C
and V may be required depending upon circuit layout.
ref
This provides a low impedance path for filtering the high
frequency noise. All high current loops should be kept as
short as possible using heavy copper runs to minimize
radiated EMI. The Error Amp compensation circuitry and
the converter output voltage divider should be located close
to the IC and as far as possible from the power switch and
other noise−generating components.
connected as a shunt regulator from V to ground. Its
CC
purpose is to protect the IC from excessive voltage that can
occur during system startup. The minimum operating
voltage (V ) for the UCX842B is 11 V and 8.2 V for the
CC
UCX843B.
Current mode converters can exhibit subharmonic
oscillations when operating at a duty cycle greater than 50%
with continuous inductor current. This instability is
independent of the regulator’s closed loop characteristics
and is caused by the simultaneous operating conditions of
fixed frequency and peak current detecting. Figure 20A
These devices contain a single totem pole output stage that
was specifically designed for direct drive of power
MOSFETs. It is capable of up to 1.0 A peak drive current
and has a typical rise and fall time of 50 ns with a 1.0 nF load.
Additional internal circuitry has been added to keep the
Output in a sinking mode whenever an undervoltage lockout
is active. This characteristic eliminates the need for an
external pull−down resistor.
shows the phenomenon graphically. At t , switch
0
conduction begins, causing the inductor current to rise at a
slope of m . This slope is a function of the input voltage
1
The SOIC−14 surface mount package provides separate
divided by the inductance. At t , the Current Sense Input
1
pins for V (output supply) and Power Ground. Proper
implementation will significantly reduce the level of
switching transient noise imposed on the control circuitry.
reaches the threshold established by the control voltage.
This causes the switch to turn off and the current to decay at
C
a slope of m , until the next oscillator cycle. The unstable
2
This becomes particularly useful when reducing the I
condition can be shown if a perturbation is added to the
control voltage, resulting in a small DI (dashed line). With
a fixed oscillator period, the current decay time is reduced,
pk(max)
clamp level. The separate V supply input allows the
C
designer added flexibility in tailoring the drive voltage
independent of V . A Zener clamp is typically connected
and the minimum current at switch turn−on (t ) is increased
CC
2
to this input when driving power MOSFETs in systems
by DI + DI m /m . The minimum current at the next cycle
2
1
where V is greater than 20 V. Figure 26 shows proper
(t ) decreases to (DI + DI m /m ) (m /m ). This perturbation
CC
3
2
1
2
1
power and control ground connections in a current−sensing
power MOSFET application.
is multiplied by m /m on each succeeding cycle, alternately
2
1
increasing and decreasing the inductor current at switch
turn−on. Several oscillator cycles may be required before
the inductor current reaches zero causing the process to
Reference
The 5.0 V bandgap reference is trimmed to 1.0%
commence again. If m /m is greater than 1, the converter
2
1
tolerance at T = 25°C on the UC284XB, and 2.0% on the
J
will be unstable. Figure 20B shows that by adding an
artificial ramp that is synchronized with the PWM clock to
the control voltage, the DI perturbation will decrease to zero
UC384XB. Its primary purpose is to supply charging current
to the oscillator timing capacitor. The reference has short−
circuit protection and is capable of providing in excess of
20 mA for powering additional control system circuitry.
on succeeding cycles. This compensating ramp (m ) must
3
have a slope equal to or slightly greater than m /2 for
2
stability. With m /2 slope compensation, the average
2
inductor current follows the control voltage, yielding true
current mode operation. The compensating ramp can be
derived from the oscillator and added to either the Voltage
Feedback or Current Sense inputs (Figure 33).
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11
UC3842B, UC3843B, UC2842B, UC2843B, NCV3843BV
(A)
DI
Control Voltage
m
m
2
1
Inductor
Current
m
m
2
1
Dl ) Dl
V
m
m
m
m
2
1
2
1
ref
Dl ) Dl ꢀꢀꢀ
8(14)
R
R
Oscillator Period
Bias
R
T
t
0
t
1
t
2
t
3
(B)
External
Sync
Input
Osc
4(7)
C
Control Voltage
T
+
m
3
0.01
2R
DI
R
2(3)
1(1)
EA
47
m
1
m
2
Inductor
Current
5(9)
Oscillator Period
The diode clamp is required if the Sync amplitude is large enough to cause the bottom
side of C to go more than 300 mV below ground.
T
t
4
t
5
t
6
Figure 20. Continuous Current Waveforms
Figure 21. External Clock Synchronization
V
CC
V
in
7(12)
5.0V Ref
8(14)
R
R
+
−
Bias
8(14)
R
R
R
A
B
7(11)
6(10)
Bias
+
−
R
8
4
Q1
Osc
5.0k
5.0k
5.0k
3
7
6
4(7)
V
+
Clamp
Osc
R
R
S
2
S
R
4(7)
1.0 mA
2R
+
5
2
Q
Q
5(8)
3(5)
2R
EA
2(3)
1(1)
R
Comp/Latch
1.0V
R
2(3)
1(1)
EA
C
MC1455
R
S
1
R
1
5(9)
1.67
R R
Where: 0 ≤ V
≤ 1.0 V
1
2
−3
+ 0.33x10
Clamp
5(9)
ǒ
Ǔ
) R
2
V
Clamp
≈
To Additional
UCX84XBs
R
1
R
R
2
1
ǒ
) 1Ǔ
V
Clamp
1.44
(R ꢀ )ꢀ 2R )C
R
B
fꢀ +ꢀ
D
ꢀ+ꢀ
I
ꢀ [ꢀ
(max)
pk(max)
R
A
ꢀ)ꢀ 2R
R
S
A
B
B
Figure 22. External Duty Cycle Clamp and
Multi−Unit Synchronization
Figure 23. Adjustable Reduction of Clamp Level
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12
UC3842B, UC3843B, UC2842B, UC2843B, NCV3843BV
V
CC
V
in
7(12)
5.0V Ref
8(14)
R
+
−
Bias
5.0V Ref
R
7(11)
6(10)
+
−
8(14)
R
R
Q1
Bias
Osc
4(7)
V
+
Clamp
+
−
S
R
1.0 mA
2R
Q
Osc
5(8)
3(5)
4(7)
2(3)
EA
2(3)
1(1)
R
+
Comp/Latch
1.0V
5(9)
R
2
S
R
1.0mA
Q
R
S
2R
R
1
C
MPSA63
R
1.0V
EA
1.0M
1.67
Where: 0 ≤ V
≤ 1.0 V
V
ꢀ[ꢀ
Clamp
Clamp
R
R
2
ǒ
) 1Ǔ
1(1)
+ * Inƪ11 *ꢀ
ƫꢀC
C
V
V
R ꢀR
1 2
Clamp
R
S
C
5(9)
t
I
ꢀ [ꢀ
Soft-Start
pk(max)
t
≈ 3600C in mF
Soft−Start
R
ꢀ)ꢀ R
3ꢀV
Clamp
1
2
Figure 24. Soft−Start Circuit
Figure 25. Adjustable Buffered Reduction of
Clamp Level with Soft−Start
V
CC
V
in
R
I
r
S pk DS(on)
) R
V
CC
V
in
V
[
(12)
Pin 5
r
DM(on)
S
If: SENSEFET = MTP10N10M
= 200
7(12)
R
S
5.0V Ref
Then :ꢀ V
ꢀ [ꢀ 0.075ꢀI
pk
Pinꢀ5
+
5.0V Ref
−
+
−
D
SENSEFET
(11)
(10)
+
−
7(11)
S
K
+
−
G
Q1
M
6(10)
5(8)
S
R
Q
S
R
(8)
(5)
Q
Comp/Latch
Power Ground:
To Input Source
Return
3(5)
R
Comp/Latch
R
1/4 W
S
C
R
S
Control Circuitry Ground:
To Pin (9)
Virtually lossless current sensing can be achieved with the implementation of a
SENSEFET power switch. For proper operation during over−current conditions,
reduction of the I clamp level must be implemented. Refer to Figures 23 and 25.
a
The addition of the RC filter will eliminate instability caused by the leading
edge spike on the current waveform.
pk(max)
Figure 26. Current Sensing Power MOSFET
Figure 27. Current Waveform Spike Suppression
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13
UC3842B, UC3843B, UC2842B, UC2843B, NCV3843BV
V
CC
V
in
I
B
7(12)
V
in
+
0
5.0V Ref
Base Charge
Removal
+
−
−
7(11)
+
−
C1
R
g
Q1
Q1
6(10)
6(10)
S
R
Q
5(8)
3(5)
5(8)
3(5)
Comp/Latch
R
S
R
S
Series gate resistor R will damp any high frequency parasitic oscillations
g
The totem pole output can furnish negative base current for enhanced
transistor turn−off, with the addition of capacitor C .
1
caused by the MOSFET input capacitance and any series wiring inductance in
the gate−source circuit.
Figure 28. MOSFET Parasitic Oscillations
Figure 29. Bipolar Transistor Drive
V
in
V
CC
8(14)
R
Bias
7(12)
R
Isolation
Boundary
5.0V Ref
Osc
4(7)
+
−
+
V
Waveforms
+
GS
1.0 mA
2R
+
0
−
7(11)
Q1
+
−
R
EA
2(3)
1(1)
0
−
50% DC
25% DC
6(10)
5(8)
S
R
MCR
101
2N
3905
V
* 1.4
(Pin1)
3ꢀR
N
S
N
5(9)
Q
ꢀ ǒ Ǔ
I k +
p
S
p
2N
3903
R
3(5)
Comp/Latch
C
R
N
S
S
N
P
The MCR101 SCR must be selected for a holding of < 0.5 mA @ T
. The simple two
A(min)
transistor circuit can be used in place of the SCR as shown. All resistors are 10 k.
Figure 30. Isolated MOSFET Drive
Figure 31. Latched Shutdown
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14
UC3842B, UC3843B, UC2842B, UC2843B, NCV3843BV
From V
O
2.5V
+
1.0mA
R
2R
i
2(3)
EA
R
C
f
R
f
R
d
1(1)
R ≥ 8.8 k
f
5(9)
Error Amp compensation circuit for stabilizing any current mode topology except for boost and flyback
converters operating with continuous inductor current.
From V
2.5V
O
+
1.0mA
R
p
2R
R
2(3)
i
R
EA
C
C
f
R
f
p
R
d
1(1)
5(9)
Error Amp compensation circuit for stabilizing current mode boost and flyback
topologies operating with continuous inductor current.
Figure 32. Error Amplifier Compensation
V
V
in
CC
7(12)
36V
5.0V Ref
+
−
8(14)
R
R
R
T
Bias
MPS3904
+
−
7(11)
6(10)
Osc
R
Slope
From V
4(7)
2(3)
O
C
T
+
−m
S
R
1.0mA
R
R
i
2R
Q
5(8)
3(5)
EA
R
C
1.0V
f
Comp/Latch
R
f
d
m
R
1(1)
S
− 3.0m
5(9)
The buffered oscillator ramp can be resistively summed with either the voltage
feedback or current sense inputs to provide slope compensation.
Figure 33. Slope Compensation
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15
UC3842B, UC3843B, UC2842B, UC2843B, NCV3843BV
L1
MBR1635
5.0V/4.0A
4.7W
+
T1
4.7k
+
+
250
MDA
202
3300
pF
2200
1000
56k
115 Vac
5.0V RTN
12V/0.3A
MUR110
1000
1N4935 1N4935
L2
10
+
+
+
+
68
+
7(12)
+
47
12V RTN
100
1000
10
L3
1N4937
5.0V Ref
−12V/0.3A
0.01
8(14)
10k
R
R
+
−
MUR110
680pF
Bias
7(11)
+
−
1N4937
2.7k
22
Osc
4(7)
2(3)
MTP
4N50
4700pF
6(10)
+
1N5819
S
R
18k
L1 − 15 mH at 5.0 A, Coilcraft Z7156
L2, L3
− 25 mH at 5.0 A, Coilcraft Z7157
Q
5(8)
3(5)
EA
100
pF
150k
1(1)
1.0k
Comp/Latch
4.7k
T1 − Primary: 45 Turns #26 AWG
Secondary 12 V: 9 Turns #30 AWG
(2 Strands) Bifiliar Wound
0.5
470pF
5(9)
Secondary 5.0 V: 4 Turns (six strands)
#26 Hexfiliar Wound
Secondary Feedback: 10 Turns
#30 AWG (2 strands) Bifiliar Wound
Core: Ferroxcube EC35−3C8
Bobbin: Ferroxcube EC35PCB1
Gap: ≈ 0.10" for a primary inductance
of 1.0 mH
Figure 34. 27 W Off−Line Flyback Regulator
Test
Conditions
Results
Line Regulation: 5.0 V
12V
V
in
= 95 to 130 Vac
D = 50 mV or 0.5%
D = 24 mV or 0.1%
Load Regulation: 5.0 V
12V
V
V
= 115 Vac,
D = 300 mV or 3.0%
D = 60 mV or 0.25%
in
I
= 1.0 A to 4.0 A
out
= 115 Vac,
in
I
= 100 mA to 300 mA
out
Output Ripple:
5.0 V
12V
V
in
= 115 Vac
40 mV
80 mV
pp
pp
Efficiency
V
in
= 115 Vac
70%
All outputs are at nominal load currents, unless otherwise noted
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16
UC3842B, UC3843B, UC2842B, UC2843B, NCV3843BV
ORDERING INFORMATION
†
Device
Operating Temperature Range
Package
Shipping
SOIC−14
UC2842BD
55 Units/Rail
55 Units/Rail
SOIC−14
(Pb−Free)
UC2842BDG
SOIC−8
UC2842BD1
98 Units/Rail
98 Units/Rail
SOIC−8
UC2842BD1G
(Pb−Free)
T = −25° to +85°C
A
SOIC−8
UC2842BD1R2
2500 Tape & Reel
2500 Tape & Reel
SOIC−8
UC2842BD1R2G
(Pb−Free)
PDIP−8
UC2842BN
PDIP−8
UC2842BNG
(Pb−Free)
1000 Units/Rail
PDIP−8
UC3842BN
PDIP−8
UC3842BNG
(Pb−Free)
SOIC−14
UC3842BD
55 Units/Rail
55 Units/Rail
SOIC−14
(Pb−Free)
UC3842BDG
SOIC−14
UC3842BDR2
2500 Tape & Reel
2500 Tape & Reel
T = 0° to +70°C
A
SOIC−14
(Pb−Free)
UC3842BDR2G
SOIC−8
UC3842BD1
98 Units/Rail
98 Units/Rail
SOIC−8
UC3842BD1G
(Pb−Free)
SOIC−8
UC3842BD1R2
SOIC−8
UC3842BD1R2G
(Pb−Free)
2500 Tape & Reel
SOIC−14
UC3842BVDR2
SOIC−14
(Pb−Free)
UC3842BVDR2G
SOIC−8
UC3842BVD1
98 Units/Rail
98 Units/Rail
T = −40° to +105°C
A
SOIC−8
UC3842BVD1G
(Pb−Free)
SOIC−8
UC3842BVD1R2
2500 Tape & Reel
2500 Tape & Reel
SOIC−8
UC3842BVD1R2G
(Pb−Free)
SOIC−14
UC2843BD
55 Units/Rail
55 Units/Rail
SOIC−14
(Pb−Free)
UC2843BDG
SOIC−14
UC2843BDR2
2500 Tape & Reel
2500 Tape & Reel
T = −25° to +85°C
A
SOIC−14
(Pb−Free)
UC2843BDR2G
SOIC−8
UC2843BD1
98 Units/Rail
98 Units/Rail
SOIC−8
UC2843BD1G
(Pb−Free)
SOIC−8
UC2843BD1R2
2500 Tape & Reel
2500 Tape & Reel
SOIC−8
UC2843BD1R2G
(Pb−Free)
T = −25° to +85°C
A
PDIP−8
UC2843BN
1000 Units/Rail
1000 Units/Rail
PDIP−8
UC2843BNG
(Pb−Free)
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
http://onsemi.com
17
UC3842B, UC3843B, UC2842B, UC2843B, NCV3843BV
ORDERING INFORMATION
†
Device
Operating Temperature Range
Package
Shipping
UC3843BD
SOIC−14
55 Units/Rail
55 Units/Rail
UC3843BDG
SOIC−14
(Pb−Free)
UC3843BDR2
SOIC−14
2500 Tape & Reel
2500 Tape & Reel
UC3843BDR2G
SOIC−14
(Pb−Free)
UC3843BD1
SOIC−8
98 Units/Rail
98 Units/Rail
UC3843BD1G
SOIC−8
(Pb−Free)
T = 0° to +70°C
A
UC3843BD1R2
SOIC−8
UC3843BD1R2G
SOIC−8
(Pb−Free)
2500 Tape & Reel
UC3843BDR2
SOIC−14
UC3843BDR2G
SOIC−14
(Pb−Free)
UC3843BN
PDIP−8
1000 Units/Rail
1000 Units/Rail
UC3843BNG
PDIP−8
(Pb−Free)
UC3843BVD
SOIC−14
55 Units/Rail
55 Units/Rail
UC3843BVDG
SOIC−14
(Pb−Free)
UC3843BVDR2
SOIC−14
2500 Tape & Reel
2500 Tape & Reel
UC3843BVDR2G
SOIC−14
(Pb−Free)
UC3843BVD1
SOIC−8
98 Units/Rail
98 Units/Rail
T = −40° to +105°C
A
UC3843BVD1G
SOIC−8
(Pb−Free)
UC3843BVD1R2
SOIC−8
2500 Tape & Reel
2500 Tape & Reel
UC3843BVD1R2G
SOIC−8
(Pb−Free)
UC3843BVN
PDIP−8
1000 Units/Rail
1000 Units/Rail
UC3843BVNG
PDIP−8
(Pb−Free)
NCV3843BVDR2
SOIC−14
2500 Tape & Reel
2500 Tape & Reel
T = −40° to +125°C
A
NCV3843BVDR2G
SOIC−14
(Pb−Free)
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
http://onsemi.com
18
UC3842B, UC3843B, UC2842B, UC2843B, NCV3843BV
MARKING DIAGRAMS
PDIP−8
N SUFFIX
CASE 626
8
1
8
1
8
1
UC384xBN
AWL
YYWWG
UC3843BVN
AWL
UC284xBN
AWL
YYWWG
YYWWG
SOIC−14
D SUFFIX
CASE 751A
14
14
14
*
UC384xBDG
AWLYWW
UC384xBVDG
AWLYWW
UC284xBDG
AWLYWW
1
1
1
SOIC−8
D1 SUFFIX
CASE 751
8
8
8
1
384xB
384xB
ALYWV
G
284xB
ALYW
G
ALYW
G
1
1
x
= 2 or 3
A
= Assembly Location
WL, L = Wafer Lot
YY, Y = Year
WW, W = Work Week
G or G = Pb−Free Package
*This marking diagram also applies to NCV3843BV.
http://onsemi.com
19
UC3842B, UC3843B, UC2842B, UC2843B, NCV3843BV
PACKAGE DIMENSIONS
PDIP−8
N SUFFIX
CASE 626−05
ISSUE L
NOTES:
1. DIMENSION L TO CENTER OF LEAD WHEN
FORMED PARALLEL.
8
5
2. PACKAGE CONTOUR OPTIONAL (ROUND OR
SQUARE CORNERS).
−B−
3. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
1
4
MILLIMETERS
INCHES
DIM MIN
MAX
10.16
6.60
4.45
0.51
1.78
MIN
MAX
0.400
0.260
0.175
0.020
0.070
A
B
C
D
F
9.40
6.10
3.94
0.38
1.02
0.370
0.240
0.155
0.015
0.040
F
−A−
NOTE 2
L
G
H
J
2.54 BSC
0.100 BSC
0.76
0.20
2.92
1.27
0.30
3.43
0.030
0.008
0.115
0.050
0.012
0.135
K
L
C
7.62 BSC
0.300 BSC
M
N
−−−
0.76
10
_
1.01
−−−
0.030
10
0.040
_
J
−T−
SEATING
PLANE
N
M
D
K
G
H
M
M
M
B
0.13 (0.005)
T
A
SOIC−14
D SUFFIX
CASE 751A−03
ISSUE G
NOTES:
−A−
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS A AND B DO NOT INCLUDE
MOLD PROTRUSION.
14
8
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.
−B−
P 7 PL
5. DIMENSION D DOES NOT INCLUDE
DAMBAR PROTRUSION. ALLOWABLE
DAMBAR PROTRUSION SHALL BE 0.127
(0.005) TOTAL IN EXCESS OF THE D
DIMENSION AT MAXIMUM MATERIAL
CONDITION.
M
M
B
0.25 (0.010)
7
1
G
F
R X 45
_
C
MILLIMETERS
DIM MIN MAX
INCHES
MIN MAX
A
B
C
D
F
G
J
K
M
P
R
8.55
3.80
1.35
0.35
0.40
8.75 0.337 0.344
4.00 0.150 0.157
1.75 0.054 0.068
0.49 0.014 0.019
1.25 0.016 0.049
0.050 BSC
0.25 0.008 0.009
0.25 0.004 0.009
−T−
SEATING
PLANE
J
M
K
D 14 PL
M
S
S
0.25 (0.010)
T
B
A
1.27 BSC
0.19
0.10
0
7
0
7
_
_
_
_
5.80
0.25
6.20 0.228 0.244
0.50 0.010 0.019
http://onsemi.com
20
UC3842B, UC3843B, UC2842B, UC2843B, NCV3843BV
PACKAGE DIMENSIONS
SOIC−8
D1 SUFFIX
CASE 751−07
ISSUE AG
NOTES:
−X−
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
A
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A AND B DO NOT INCLUDE
MOLD PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 (0.005) TOTAL
IN EXCESS OF THE D DIMENSION AT
MAXIMUM MATERIAL CONDITION.
6. 751−01 THRU 751−06 ARE OBSOLETE. NEW
STANDARD IS 751−07.
8
5
4
S
M
M
B
0.25 (0.010)
Y
1
K
−Y−
G
MILLIMETERS
DIM MIN MAX
INCHES
MIN
MAX
0.197
0.157
0.069
0.020
C
N X 45
_
A
B
C
D
G
H
J
K
M
N
S
4.80
3.80
1.35
0.33
5.00 0.189
4.00 0.150
1.75 0.053
0.51 0.013
SEATING
PLANE
−Z−
0.10 (0.004)
1.27 BSC
0.050 BSC
M
0.10
0.19
0.40
0
0.25 0.004
0.25 0.007
1.27 0.016
0.010
0.010
0.050
8
0.020
0.244
J
H
D
8
0
_
_
_
_
M
S
S
X
0.25 (0.010)
Z
Y
0.25
5.80
0.50 0.010
6.20 0.228
SOLDERING FOOTPRINT*
1.52
0.060
7.0
0.275
4.0
0.155
0.6
0.024
1.270
0.050
mm
inches
ǒ
Ǔ
SCALE 6:1
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
SENSEFET is a trademark of Semiconductor Components Industries, LLC.
ON Semiconductor and
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All
operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights
nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications
intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should
Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates,
and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death
associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal
Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
PUBLICATION ORDERING INFORMATION
LITERATURE FULFILLMENT:
N. American Technical Support: 800−282−9855 Toll Free
USA/Canada
Europe, Middle East and Africa Technical Support:
Phone: 421 33 790 2910
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Phone: 81−3−5773−3850
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Order Literature: http://www.onsemi.com/orderlit
Literature Distribution Center for ON Semiconductor
P.O. Box 5163, Denver, Colorado 80217 USA
Phone: 303−675−2175 or 800−344−3860 Toll Free USA/Canada
Fax: 303−675−2176 or 800−344−3867 Toll Free USA/Canada
Email: orderlit@onsemi.com
For additional information, please contact your local
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UC3842B/D
UC2842BD1G 替代型号
型号 | 制造商 | 描述 | 替代类型 | 文档 |
UC3842BD1G | ONSEMI | High Performance Current Mode Controllers | 类似代替 | |
UC3842BD1R2G | ONSEMI | High Performance Current Mode Controllers | 类似代替 | |
UC2842BD1R2G | ONSEMI | High Performance Current Mode Controllers | 类似代替 |
UC2842BD1G 相关器件
型号 | 制造商 | 描述 | 价格 | 文档 |
UC2842BD1R2 | ONSEMI | High Performance Current Mode Controllers | 获取价格 | |
UC2842BD1R2 | MOTOROLA | 1A SWITCHING CONTROLLER, 500kHz SWITCHING FREQ-MAX, PDSO8, PLASTIC, SO-8 | 获取价格 | |
UC2842BD1R2G | ONSEMI | High Performance Current Mode Controllers | 获取价格 | |
UC2842BDG | ONSEMI | High Performance Current Mode Controllers | 获取价格 | |
UC2842BDR2 | MOTOROLA | 1A SWITCHING CONTROLLER, 500kHz SWITCHING FREQ-MAX, PDSO14, PLASTIC, SO-14 | 获取价格 | |
UC2842BDR2 | ONSEMI | 1A SWITCHING CONTROLLER, 500kHz SWITCHING FREQ-MAX, PDSO14, PLASTIC, SOIC-14 | 获取价格 | |
UC2842BDR2G | ONSEMI | High Performance Current Mode Controllers | 获取价格 | |
UC2842BN | STMICROELECTRONICS | HIGH PERFORMANCE CURRENT MODE PWM CONTROLLER | 获取价格 | |
UC2842BN | ONSEMI | High Performance Current Mode Controllers | 获取价格 | |
UC2842BN | MOTOROLA | HIGH PERFORMANCE CURRENT MODE CONTROLLERS | 获取价格 |
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