RS2051_10_技术文档

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RS2051

Green-Mode PWM Controller with Frequency Jiggling for Low EMI

Description

The RS2051 is a highly integrated low cost current mode PWM controller, which is ideal for small power current mode of offline

AC-DC fly-back converter applications. Making use of external resistors, the IC changes the operating frequency and

automatically enters the PFM/CRM (Cycle Reset Mode) under light-load/zero-load conditions. This can minimize standby power

consumption and achieve power-saving functions. With a very low start-up current, the RS2051 could use a large value start-up

resistor (2Mohms). Built-in synchronized slope compensation enhances the stability of the system and avoids sub-harmonic

oscillation. Dynamic peak current limiting circuit minimizes output power change caused by delay time of the system over a

universal AC input range. Leading edge blanking circuit on current sense input could remove the signal glitch due to snubber

circuit diode reverse recovery and thus greatly reduces the external component count and system cost in the design. Cycle-by-

Cycle current limiting ensures safe operation even during short-circuit.

Excellent EMI performance is achieved built-in soft start with 1.2ms、soft driver and low EMI Technique.

The RS2051 offers perfect protection like OVP(Over Voltage Protection)、OLP(Over Load Protection)、SCP(Short circuit

protection)、Sense Fault Protection, LM (Latch Mode) and OCP(Over current protection). The RS2051’s output driver is soft

clamped to maximum 18V to protect the power MOSFET. RS2051 is offered in SOT-23-6, SOP-8 and DIP-8 packages.

Features

ꢀ

Low Cost, PWM, PFM&CRM (Cycle Reset Mode)

Low Start-up Current (about 3μA)

Low Operating Current (about 1.2mA)

Current Mode Operation

Under Voltage Lockout (UVLO)

Built-in Synchronized Slope Compensation

Built-in fixed soft start with 1.2ms

Built-in Frequency Jiggling for better EMI Signature

Programmable PWM Frequency

Audio Noise Free Operation

ꢀ

Constant output power limiting for universal AC input

Range

SOT-26、SOP-8 and DIP-8 Pb-Free Packaging

Soft Clamped GATE output voltage 18V

VDD over voltage protect 34V

Cycle-by-cycle current limiting

Sense Fault Protect ion

Output SCP (Short circuit Protection)

Output OLP (Over Load Protection)

Latch mode After OLP&SCP

ꢀ

Leading edge Blanking on Sense input

High-Voltage CMOS Process with ESD

Applications

ꢀ

Switching AC/DC Adaptor

Battery Charger

Open Frame Switching Power Supply

Standby Power Supplies

Set-Top Box Power Supplies

Pin Configurations

Name

Description

GND

FB

RI

SEN

VDD

GND Pin

Voltage feedback pin. Output current of this pin could controls the PWM duty cycle、OLP and SCP.

This pin is to program the switching frequency. By connecting a resistor to ground to set the switching frequency

Current sense pin, connect to sense the MOSFET current

Supply voltage pin

GATE Totem output to drive the external Power MOSFET.

DS-RS2051-09 No v, 2010

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Typical Application Circuit

Block Diagram

DS-RS2051-09 No v, 2010

www.Orister.com

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Absolute Maximum Ratings

Symbol

Parameter

Rating

40

20

-0.3 to 6V

300

Unit

V

mA

V

mW

V

V_DD

I_OVP

V_FB

V_SEN

P_D

Supply voltage Pin Voltage

VDD OVP maximal enter current

Input Voltage to FB Pin

Input Voltage to SEN Pin

Power Dissipation

ESD Capability, HBM Model

ESD Capability, Machine Model

2500

250

ESD

V

20second:

SOT-23-6L

10second:

DIP-8L

10second:

SOP-8L

220

260

^oC

Lead Temperature

(Soldering)

T_L

^oC

230

T_STG

Storage Temperature Range

-55 to + 150

Recommended Operation Condition

Symbol

V_DD

RI

T_OA

Parameter

VDD Supply Voltage

RI PIN Resistor Value

Operation Ambient Temperature

Output Power

Min ~ Max

10~30

100

-20~85

60

Unit

V

K ohm

^oC

P_O

W

F_PWM

Frequency of PWM

30~150

KHz

Electrical Characteristics (Ta=25°C unless otherwise noted, V_DD= 15V.)

Symbol

Parameter

Conditions

Supply Voltage (V_DDPin)

Min.

Typ.

Max.

Unit

3.0

20.0

I_ST

Startup Current

μA

mA

V

V_FB=0V

V_FB=3V

1.2

I_SS

Operating Current

0.8

V_FB=Open

13.0

7.8

14.0

8.8

15.0

9.8

V_DDON

V_DDOFF

Turn-on Threshold Voltage

Turn-off Threshold Voltage

VDD Clamp Voltage

V

34.0

V_DDCLAMP

I_VDD=20mA

V

Anti Intermission Surge

VDD Voltage

9.4

V_DDAIS

V

Voltage Feedback (FB Pin)

V_FB=0V

0.7

4.8

I_FB

V_FB

Short Circuit Current

Open Loop Voltage

mA

V

V_FB=Open

0.59

0.50

0.55

1.80

1.40

170

3.7

I_{FB_0D}

I_PFM

Zero Duty Cycle FB current

mA

V

Enter PFM&PWM, FB current

Enter CRM, FB current

I_CRM

V_PFM

PFM Threshold V_FB

V_CRM

Enter CRM Threshold V_FB

Enter OLP&SCP FB current

Enter OLP&SCP FB voltage

OLP&SCP min. delay Time

V

I_OLP&SCP

V_OLP&SCP

T_OLP&SCP

uA

V

33

35

50

RI=100K

Current Sensing (SEN Pin)

ms

Minimum Voltage Lever

(Dmin=0%)

Maximum Voltage Lever

(Dmax=78%)

0.80

1.05

V_{TH_L}

V_{TH_H}

V

75

40

T_PD

R_CS

T_LEB

Delay to Output

Input Impedance

Leading edge blanking time

ns

KΩ

ns

300

DS-RS2051-09 No v, 2010

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Oscillator (RI Pin)

RI=100Kohm

60

65

22

78

5

70

F_OSC

F_PFM

Normal Frequency

PFM Frequency

KHz

KHZ

%

RI=100Kohm

-30~100℃

DC_{MAX_W}

DC_{MAX_F}

ΔF_TEMP

T_BLANK

F_PFM

Maximum Duty Cycle PWM

Maximum Duty Cycle PFM

Frequency Temp. Stability

Leading-Edge Blanking Time

Frequency PFM

%

300

nS

%

-4

4

RI=100Kohm

GATE Drive Output (GATE Pin)

V_DD=16V, I_O=20mA

C_L=500pF

0.8

V_OL

V_OH

T_R1

Output Low Level

Output High Level

Rising Time

V

10

V

123

71

ns

V

T_F1

Falling Time

C_L=500pF

248

116

343

153

508

209

18.0

T_R2

Rising Time

C_L=1000pF

T_F2

Falling Time

C_L=1000pF

T_R3

Rising Time

C_L=1500pF

T_F3

Falling Time

C_L=1500pF

T_R4

Rising Time

C_L=2000pF

T_F4

Falling Time

C_L=2000pF

VG_CLAMP

Output Clamp Voltage

VDD=20V

Frequency Jiggling

RI=100Kohm

F_Jiggling

Low EMI frequency

65

KHz

%

∆f_osc

RI=100Kohm

-3

3

Frequency modulation range / Base frequency

2

Notice: The drive current of GATE pin is a variable value, which is decided by I = K(V

− V

− 2.8) (Among these, K

VDD

GATE

is a invariable coefficient，V_GATEis the voltage of GATE pin, V_VDDis the voltage of VDD pin)；So the higher the VDD voltage is

and the lower the output voltage is, the bigger the drive transient current is. When the GATE voltage is 0V and the VDD voltage

is 13V, the output drive current would over 120mA. The output driver current would decrease with increasing of the GATE

voltage.

DS-RS2051-09 No v, 2010

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OPERATION DESCRIPTION

Current Mode

Compared to voltage mode control, current mode control has a current feedback loop. When the voltage of the Sense resistor

peak current of the primary winding reaches the internal setting value V_TH, the register resets and the power MOSFET cuts off.

So, to detect and modulate the peak current cycle-by-cycle could control the output of the power supply. The current feedback

has a good linear modulation rate and a fast input and output dynamic impact, and avoid the pole that the output filter

inductance brings and the two-class system descends to the one-class. So it widens the frequency range and optimizes

overload protection and short circuit protection.

Startup Current and Under Voltage Lockout

The startup current of RS2051 is set to be very low so that a large value startup resistor can be used to minimize the power loss.

For AC to DC adaptor with universal input range design, a 2 mΩ, 1/8 W startup resistor and a 10uF/25V VDD hold capacitor

could be used.

The turn-on and turn-off threshold of the RS2051 is designed to 14V/8.8V. During startup, the hold-up capacitor must be charge

to 14V through the startup resistor. The hysteresis is implemented to prevent the shutdown from the voltage dip during startup.

Internal Bias and OSC Operation

A resistor connected between RI pin and GND pin sets the internal constant current source to charge or discharge the internal

fixed capacitor. The charge time and discharge time determines the internal clock speed and the switching frequency.

Increasing the resistance will reduce the value of the input current and reduce the switching frequency. The relationship

between RI and PWM switching frequency follows the below equation within the RI allowed range.

6500

F_OSC

=

(kHz)

RI(KΩ)

For example, a 100kΩ resistor RI could generate a 20uA constant current and a 65KHz PWM switching frequency.

The suggested operating frequency range of RS2051 is within 50KHz to 150KHz.

Green Power Operation

The power dissipation of switching mode power supply is very important in zero load or light load condition. The major

dissipation results from conduction loss、switching loss and consume of the control circuit. However, all of them relates to the

switching frequency. There are many difference topologies has been implemented in different chip. The basic operation theory

of all these approaches intends to reduce the switching frequency under light-load or no-load condition.

The RS2051’s green power function adapts PWM、PFM and CRM combining modulation. When RI resistor is 100kΩ, the PWM

frequency is 65KHz in medium or heavy load operation. Through modifying the pulse width, The RS2051 could control output

voltage. The current of FB pin increases when the load is in light condition and the internal mode controller enters PFM&PWM

when the feedback current is over 1.37mA. The operation frequency of oscillator is to descend gradually. When the feedback

current is over 0.5mA, the frequency of oscillator is invariable, namely 22kHz.

To decrease the standby consumption of the power supply, Orister introduces the Cycle Reset Mode technology (CRM). If the

feedback current is over 0.59mA, mode controller of the RS2051 would reset internal register all the time and cut off the GATE

pin. While the output voltage is lower than the set value, the register would be set, the GATE pin operate again. So the

frequency of the internal OSC is invariable, the register would reset some pulses so that the practical frequency is decreased at

the GATE pin.

RS2051 Green-Power Function

DS-RS2051-09 No v, 2010

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Internal Synchronized Slope Compensation

Although there are more advantages of the current mode control than conventional voltage mode control, there are still several

drawbacks of peak-sensing current-mode converter, especially the open loop instability when it operates in higher than 50% of

the duty-cycle. To solve this problem, the RS2051 is introduced an internal slope compensation adding voltage ramp to the

current sense input voltage for PWM generation. It improves the close loop stability greatly at CCM, prevents the sub-harmonic

oscillation and thus reduces the output ripple voltage.

DUTY

V_SLOP= 0.33 ×

= 0.4389 × DUTY

DUTY_MAX

Slope Compensation

Current Sensing & Dynamic peak limiting

The current flowing by the power MOSFET comes into being a voltage V_SENSEon the Sense pin cycle-by-cycle, which compares

to the internal reference voltage, and controls the reverse of the internal register, limits the peak current IMAX of the primary of

1

2

the transformer. The transformer energy is E = × L× I_MAX. So adjusting the R_SENSEcan set the maximal output power of

2

V_IN

the power supple. The current flowing by the power MOSFET has an extra value ( ΔI =

× T_D) due to the system delay time

L_P

that is from detecting the current through the Sense pin to power MOSFET off in the RS2051 (Among these, V_INis the primary

winding voltage of the transformer and L_Pis the primary wind inductance). V_INranges from 85VAC to 264VAC. To guarantee the

output power is a constant for universal input AC voltage, there is a dynamic peak limit circuit to compensate the system delay T

that the system delay brings on.

Vsense

1.10

1.05

1.00

0.95

0.90

0.85

0.80

0.75

0.70

Duty Cycle

0.65

0% 10%20%30%40%50%60%70%80%90%

Frequency Jiggling for EMI improvement

The Frequency Jiggling Technique is introduced in the RS2051. As following figure, the internal oscillation frequency is

modulated by itself. A whole surge cycle includes 128 pulses and the Jiggling ranges from -4% to +4%. Thus, the function could

minimize the electromagnetic interferer from the power supply module.

Frequency(HZ)

70K

65K

60K

Time

Frequency Jiggling for EMI

DS-RS2051-09 No v, 2010

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OLP&SCP

To protect the circuit from being damaged under the over load or short circuit condition, a smart OLP&SCP function is

implemented in the RS2051. When short circuit or over load occurs in the output end, the feedback cycle would enhance the

voltage of FB pin, while the voltage is over 3.7V or the current from FB is below 170uA, the internal detective circuit would send

a signal to shut down the GATE and pull down the VDD voltage, then the circuit is restart. To avoid the wrong operation when

circuit starts, the delay time is set. When the RI resistance is 100Kohm, the delay time T_OLP&SCPis between 33ms and 50ms.

The relationship between RI and T_OLP&SCPfollows the below equation.

RI× 2

6 × 10³

RI× 3

6 × 10³

(mS) < T_OLP&SCP

<

(mS)

Anti Intermission Surge

When the power supplies change the heavy load to light load immediately, there could be tow phenomena caused by system

delay. They are output voltage overshot and intermission surge. To avoid it, the anti intermission surge is built in the RS2051. If

it occurs, the FB current is to increase rapidly, the GATE would be cut off for a while, VDD pin voltage descends gradually.

When VDD reaches 9.4V, the GATE pin would operate again, which the frequency is 22KHz.

Leading-edge Blanking (LEB)

Each time the power MOSFET is switched on, a turn-on spike will inevitably occur at the Sense pin, which would disturb the

internal signal from the sampling of the R_SENSE. There is a 300ns leading edge blanking time built in to avoid the effect of the

turn-on spike, and the power MOSFET cannot be switched off during the moment. So that the conventional external RC filtering

on sense input is no longer required.

Over Voltage Protection (OVP)

There is a 25.6V over-voltage protection circuit in the RS2051 to improve the credibility and extend the life of the chip. When the

VDD voltage is over 25.6V, the GATE pin is to shutdown immediately and the VDD voltage is to descend rapidly.

GATE Driver & Soft Clamped

The RS2051 output designs a totem pole to drive a periphery power MOSFET. The dead time is introduced to minimize the

transfixion current during the output operating. The novel soft clamp technology is introduced to protect the periphery power

MOSFET from breaking down and current saturation of the Zener.

DS-RS2051-09 No v, 2010

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DIP-8 Dimension

6

3

5

4

8

1

7

2

DIM

A

B

C

D

E

Min.

Max.

6.40

9.32

*1.52

*1.27

*0.99

3.35

3.55

0.53

2.79

7.74

*3.00

8.81

0.381

97^o

6.29

9.22

-

3.25

3.17

0.38

2.28

7.49

-

8.56

0.229

94^o

A

Marking:

Date Code

B

J

F

P

RS

G

H

I

J

K

L

M

α1

2 0 5 1

F

Control Code

α1

K

L

E

C

G

H

M

D

*: Typical, Unit: mm

I

8-Lead DIP-8

Plastic Package

Package Code: P

SOP-8 Dimension

A

G

DIM

A

B

C

D

E

F

G

H

I

J

K

L

M

N

O

Min.

4.85

3.85

5.80

1.22

0.37

3.74

1.45

4.80

0.05

0.30

0.19

0.37

0.23

0.08

0.00

Max.

5.10

3.95

6.20

1.32

0.47

3.88

1.65

5.10

0.20

0.70

0.25

0.52

0.28

0.13

0.15

I

8

7

6

5

4

Marking:

C

B

H

Pin1 Index

2

3

RS

2 0 5 1

S

J

Date Code

Control Code

D

E

K

Part A

L

Part A

N

M

O

*: Typical, Unit: mm

F

8-Lead SO-8 Plastic

Surface Mounted Package

Package Code: S

DS-RS2051-09 No v, 2010

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SOT-23-6 Dimension

DIM

A

A1

B

b

C

D

e

H

L

Min.

Max.

1.000

0.100

1.803

0.559

3.000

3.099

1.041

0.254

0.610

0.700

0.000

1.397

0.300

2.591

2.692

0.838

0.080

0.300

Marking:

1

6-Lead SOT-23-6L

Plastic Package

Package Code: N

Ordering Information

PART NUMBER

RS2051S

PACKAGE

SOP-8

RS2051P

DIP-8

RS2051N

SOT-23-6

DS-RS2051-09 No v, 2010

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Page No. : 10/11

Soldering Methods for Orister’s Products

1. Storage environment: Temperature=10^oC~35^oC Humidity=65%±15%

2. Reflow soldering of surface-mount devices

Figure 1: Temperature profile

t

P

Critical Zone

to T

TP

T

L

P

Ramp-up

TL

t

L

Tsmax

Tsmin

t

S

Preheat

Ramp-down

25

t 25^oC to Peak

Time

Profile Feature

Average ramp-up rate (T_Lto T_P)

Preheat

Sn-Pb Eutectic Assembly

Pb-Free Assembly

<3^oC/sec

- Temperature Min (Ts_min

)

100^oC

150^oC

200^oC

- Temperature Max (Ts_max

- Time (min to max) (ts)

Tsmax to T_L

)

60~120 sec

60~180 sec

- Ramp-up Rate

<3^oC/sec

Time maintained above:

- Temperature (T_L)

- Time (t_L)

183^oC

217^oC

60~150 sec

240^oC +0/-5^oC

60~150 sec

260^oC +0/-5^oC

Peak Temperature (T_P)

Time within 5^oC of actual Peak

10~30 sec

20~40 sec

Temperature (t_P)

Ramp-down Rate

Time 25^oC to Peak Temperature

<6^oC/sec

<6 minutes

<8 minutes

3. Flow (wave) soldering (solder dipping)

Products

Pb devices.

Peak temperature

245^oC ±5^oC

260^oC +0/-5^oC

Dipping time

5sec ±1sec

Pb-Free devices.

DS-RS2051-09 No v, 2010

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Page No. : 11/11

Important Notice:

• All rights are reserved. Reproduction in whole or in part is prohibited without the prior written approval of Orister Corporation.

• Orister Corporation reserves the right to make changes to its products without notice.

• Orister Corporation products are not warranted to be suitable for use in Life-Support Applications, or systems.

• Orister Corporation assumes no liability for any consequence of customer product design, infringement of patents, or application assistance.

DS-RS2051-09 No v, 2010

www.Orister.com


型号：	RS2051_10
厂家：	ORISTER CORPORATION
描述：	Green-Mode PWM Controller with Frequency Jiggling for Low EMI 绿色模式PWM控制器，频率摇动的低EMI 控制器
文件：	总11页 (文件大小：334K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

RS2051_10 [ORISTER]

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