RS6501 [ORISTER]
150KHz, 40V, 2A PWM Buck DC/DC Converter; 为150KHz ， 40V ， 2A PWM降压型DC / DC转换器
| 型号： | RS6501 |
| 厂家： | 
ORISTER CORPORATION |
| 描述： | 150KHz, 40V, 2A PWM Buck DC/DC Converter |
| 文件： | 总8页 (文件大小：486K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Page No. : 1/8
RS6501
150KHz, 40V, 2A PWM Buck DC/DC Converter
General Description
The RS6501 is Monolithic IC that design for a step‐down DC/DC Converter, and own the ability of driving a 2A load without
additional transistor component.
The output version included 3.3V, 5V, 12V and an adjustable type. It operates at a switching frequency of 150KHz thus
allowing smaller sized filter components than what would be needed with lower frequency switching regulators. Other
features include a guaranteed ±4% tolerance on output voltage under specified input voltage and output load conditions,
and ±15% on the oscillator frequency. Regarding protected function, thermal shutdown is to prevent over temperature
operating from damage, and current limit is against over current operating of the output switch.
Features
Applications
●
●
●
●
●
●
●
●
●
●
●
●
●
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3.3V, 5V, 12V and adjustable
Adjustable version output voltage range: 1.23‐37V
Simple High‐efficiency step‐down regulator
Positive to negative converter
On‐card switching regulators
4% max over line and load conditions
±
150KHz 15% fixed switching frequency
±
TTL shutdown capability
Operating voltage can be up to 40V
Output load current: 2A
SOP‐8 package
Low power standby mode
Thermal‐shunt down and current‐limit protection
Built‐in switching a transistor on chip, requires only 4
external components
Application Circuits
VCC_INPUT
+5.0V
U1
L1
33uH
2
1
2
3
4
8
1
VIN
Output GND
FB
SD
GND
7
6
5
GND
GND
R1
R1
C1
+
C2 3.1K(0805)
RS6501-ADS
10
C4
+
C5
R2
1K(0805)
C3
1000pF
D1
Adjustable Output Voltage Version
This integrated circuit can be damaged by ESD. Orister Corporation recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
DS‐RS6501‐06 September, 2010
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Pin Assignments
SOP‐8(EP)
PACKAGE
PIN
1
SYMBOL
VIN
DESCRIPTION
Regulator Input Pin
2
3
4
VOUT
FB
SD
Regulator Output Pin
Output Voltage Feed Back Control Pin
ON/OFF Shutdown Pin
Ground Pin
SOP‐8(EP)
5, 6, 7, 8 ,9
GND
Ordering Information
DEVICE
DEVICE CODE
XX is nominal output voltage (for example, AD=ADJ, 33 = 3.3V, 50 = 5.0V, 12 = 12V).
Y is package designator :
SE : SOP‐8(EP)
Z is Lead Free designator :
RS6501‐XX YY Z
P: Commercial Standard, Lead (Pb) Free and Phosphorous (P) Free Package
G: Green (Halogen Free with Commercial Standard)
Block Diagram
SD
VIN
+
+
Current
Source
Bias
1.235V
Reference
2.5V
Regulator
Start
Up
200mV
220mV
R
+
COMP
-
Current
Limit
-
FB
COMP
+
-
+
R2
AMP
-
3A
Switch
COMP
Driver
+
+
Output
GND
R1=2.5K
150KHz
OSC.
Thermal
Limit
COMP
-
DS‐RS6501‐06 September, 2010
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(Note1)
Absolute Maximum Ratings
Parameter
Supply Voltage
Symbol
VCC
Value
40
Unit
V
On/Off Pin Input Voltage
Feedback Pin Voltage
Output Voltage to Ground
Power Dissipation
Operating Temperature
Storage Temperature
VSD
VFB
VOUT
PD
Topr
Tstg
‐0.3~+25
‐0.3~+25
‐1
V
V
V
W
oC
oC
oC
V
Internally Limited
0~+70
‐65~+150
‐40~+125
+4.5~+40
Operating Junction Temperature Range
Operating Voltage
TJ
VOP
Electrical Characteristics (Continued)
Specifications with boldface type apply over for full operating temperature range, the other type are for TJ=25oC(Note 2)
Part No.
Parameter
Output Voltage
Efficiency
Symbol
VOUT
η
Conditions
5V≤VIN≤40V, 0.2A≤ILOAD≤2A
IN =12V, ILOAD=2A
Min.
3.135
‐
Typ.
3.3
72
Max.
3.465
‐
Unit
V
%
RS6501‐3.3V
V
Output Voltage
Efficiency
Output Voltage
Efficiency
VOUT
η
VOUT
η
7V≤VIN≤40V, 0.2A≤ILOAD≤2A
VIN=12V, ILOAD=2A
15V≤VIN≤40V, 0.2A≤ILOAD≤2A
VIN=25V, ILOAD=2A
4.750
5.0
79
12.0
90
5.250
‐
12.60
‐
V
%
V
%
RS6501‐5.0V
RS6501‐12V
‐
11.40
‐
4.5V≤VIN≤40V, 0.2A≤ILOAD≤2A
Reference Voltage
Efficiency
VFB
1.193
1.230
72
1.280
V
RS6501‐ADJ
VOUT programmed for 3V
VIN=12V, ILOAD=2A
‐
‐
%
η
All Output Voltage Versions Electrical Characteristics
Specifications with boldface type apply over for full operating temperature range, the other type are for TJ=25oC
(Unless otherwise specified, VIN=12V for the 3.3V, 5V, and adjustable version and VIN=24V for the 12V version, ILOAD=500mA)
Parameter
Symbol
Test Condition
Device Parameters
Min.
Typ.
Max.
Unit
50
Feedback Bias Current
Oscillator Frequency
Saturation Voltage
Ib
fO
Adjustable Version Only, VFB=1.3V
(Note 5)
‐
40
nA
KHz
V
100
173
173
1.4
127
110
150
1.16
VSAT
DC
ICL
IOUT=2A (Note 6,7)
‐
‐
‐
1.5
Max. Duty Cycle (ON)
Min. Duty Cycle (OFF)
(Note 7)
(Note 8)
100
0
‐
‐
%
Current Limit
Peak Current (Note 6,7)
3.6
A
Output Leakage Current
Quiescent Current
IL
IQ
Output=0V (Note 6,8)
(Note 8)
‐
‐
‐
5
50
30
uA
mA
200
300
Standby Quiescent Current
ISTBY
ON/OFF pin=5V (Note 9)
‐
85
uA
θJC
SOP‐8
Junction to Case
‐
‐
15
70
‐
‐
oC/W
oC/W
Thermal Resistance
θJA (Note 10)
SOP‐8
Junction to ambient
ON/OFF Control
VIH
Low (Regulator ON)
‐
0.6
ON/OFF Pin Logic Input Threshold Voltage
ON/OFF Pin Input Current
1.4
V
VIL
IIH
IIL
High (Regulator OFF)
VLOGIC=2.5V (Regulator OFF)
VLOGIC=0.5V (Regulator ON)
2.0
‐
‐
‐
15
5
6
0.02
uA
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NOTE:
1.
Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate
conditions for which the device is intended to be functional, but do not guarantee specific performance limits. For
guaranteed specifications and test conditions, see the Electrical Characteristics.
External components such as the catch diode, inductor, input and output capacitors, and voltage programming
resistors can affect switching regulator system performance.
2.
3.
4.
Typical numbers are at 25oC and represent the most likely norm.
All limits guaranteed at room temperature (standard type face) and at temperature extremes (bold type face). All room
temperature limits are 100% production tested. All limits at temperature extremes are guaranteed via correlation using
standard Statistical Quality Control (SQC) methods. All limits are used to calculate Average Outgoing Quality Level
(AOQL).
5.
6.
7.
8.
The switching frequency is reduced when the second stage current limit is activated.
No diode, inductor or capacitor connected to output pin.
Feedback pin removed from output and connected to 0V to force the output transistor switch ON.
Feedback pin removed from output and connected to 12V for the 3.3V, 5V, ADJ. version, and 15V for the 12V version,
to force the output transistor switch OFF.
9.
VIN=40V.
10. Junction to ambient thermal resistance. (With copper area of approximately 3in2)
DS‐RS6501‐06 September, 2010
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Page No. : 5/8
Characteristics Curve
Normalized Output Voltage
Shutdown Quiescent Current
160
140
120
100
80
1.5
1
V =12V
IN
ILOAD=200mA
0.5
0
VON/VOFF=5V
TJ=25oC
60
-0.5
-1
40
20
-1.5
0
0
25
50
75
100
125
150
175
0
10
20
30
40
Junction Temperature (oC)
Supply Voltage (V)
Switch Current Limit
Switch Saturation Voltage
6.00
5.90
5.80
5.70
5.60
5.50
5.40
5.30
5.20
1.30
1.20
1.10
1.00
0.90
0.80
V =12V
TJ=25oC
IN
V =12V
IN
VOUT=5V
0
1
2
3
4
0
25
50
75
100
125
150
Junction Temperature (oC)
Switch Current (A)
On/Off Pin Current (Sinking)
12
10
8
Vin=22V
Tj=25
℃
6
4
2
0
0
5
10
15
20
25
30
On/Off Pin Voltage (V)
DS‐RS6501‐06 September, 2010
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Page No. : 6/8
SOP‐8/EP Dimension
NOTES:
A. All linear dimensions are in millimeters (inches).
B. This drawing is subject to change without notice.
C. Body length does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.006 (0.15) per end.
D. Body width dimension does not include inter‐lead flash or protrusions. Inter‐lead flash and protrusions shall not exceed
0.010 (0.25) per side.
E. The chamfer on the body is optional. If it is not present, a visual index feature must be located within the cross‐hatched
area.
F. Lead dimension is the length of terminal for soldering to a substrate.
G. The lead width, as measured 0.014 (0.36) or greater above the seating plane, shall not exceed a maximum value of 0.024
(0.61).
H. Lead to lead coplanarity shall be less than 0.004 (0.10) form Seating Plane.
I. Falls within JEDEC MS‐012 variation AA.
DS‐RS6501‐06 September, 2010
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Page No. : 7/8
Soldering Methods for Orister’s Products
1. Storage environment: Temperature=10oC~35oC Humidity=65%±15%
2. Reflow soldering of surface‐mount devices
Figure 1: Temperature profile
t
P
Critical Zone
to T
TP
T
L
P
Ramp-up
TL
t
L
Tsmax
Tsmin
t
S
Preheat
Ramp-down
25
t 25oC to Peak
Time
Profile Feature
Average ramp‐up rate (TL to TP)
Preheat
Sn‐Pb Eutectic Assembly
Pb‐Free Assembly
<3oC/sec
<3oC/sec
‐ Temperature Min (Tsmin
)
100oC
150oC
150oC
200oC
‐ Temperature Max (Tsmax
‐ Time (min to max) (ts)
Tsmax to TL
)
60~120 sec
60~180 sec
‐ Ramp‐up Rate
<3oC/sec
<3oC/sec
Time maintained above:
‐ Temperature (TL)
‐ Time (tL)
183oC
217oC
60~150 sec
240oC +0/‐5oC
60~150 sec
260oC +0/‐5oC
Peak Temperature (TP)
Time within 5oC of actual Peak
10~30 sec
20~40 sec
Temperature (tP)
Ramp‐down Rate
Time 25oC to Peak Temperature
<6oC/sec
<6oC/sec
<6 minutes
<8 minutes
3. Flow (wave) soldering (solder dipping)
Products
Pb devices.
Peak temperature
245oC ±5oC
260oC +0/‐5oC
Dipping time
5sec ±1sec
5sec ±1sec
Pb‐Free devices.
DS‐RS6501‐06 September, 2010
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Important Notice:
© Orister Corporation
Orister cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in an Orister product.
No circuit patent licenses, copyrights, mask work rights, or other intellectual property rights are implied.
Orister reserves the right to make changes to their products or specifications or to discontinue any product or service
without notice. Except as provided in Orister’s terms and conditions of sale, Orister assumes no liability whatsoever, and
Orister disclaims any express or implied warranty relating to the sale and/or use of Orister products including liability or
warranties relating to fitness for a particular purpose, merchantability, or infringement of any patent, copyright or other
intellectual property right. In order to minimize risks associated with the customer’s applications, adequate design and
operating safeguards must be provided by the customer to minimize inherent or procedural hazards. Testing and other
quality control techniques are utilized to the extent Orister deems necessary to support this warranty. Specific testing of
all parameters of each device is not necessarily performed.
Orister and the Orister logo are trademarks of Orister Corporation. All other brand and product names appearing in this
document are registered trademarks or trademarks of their respective holders.
DS‐RS6501‐06 September, 2010
www.Orister.com
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