Q68000A8560_技术文档

0.200" 8-Character 5x7 Dot Matrix Parallel Input

Alphanumeric Intelligent Display® Devices

Lead (Pb) Free Product - RoHS Compliant

Red

HSDP2110S

HSDP2111S

HSDP2112S

HSDP2113S

HSDP2114S

HSDP2115S

Yellow

High Efficiency Red

Green

High Efficiency Green

Soft Orange

DESCRIPTION

FEATURES

•

Eight 0.200" Dot Matrix Characters in Red, Yellow,

High Efficiency Red, Green, High Efficiency Green, or

Soft Orange

The HDSP2110S (Red), HDSP2111S (Yellow),

HDSP2112S (High Efficiency Red), HDSP2113S

(Green), HDSP2114S (High Efficiency Green), and

HDSP2115S (Soft Orange) are eight digit, 5 x 7 dot

matrix, alphanumeric Intelligent Display devices. The

0.20 inch high digits are packaged in a rugged, high qual-

ity, optically transparent, 0.6 inch lead spacing, 28 pin

plastic DIP.

•

Built-in 128 Character ROM,

Mask Programmable for Custom Fonts

Readable from 8 Feet (2.5 meters)

Built-in Decoders, Multiplexers and Drivers

Wide Viewing Angle, X Axis ± 55°, Y Axis ± 65°

Programmable Features:

•

The on-board CMOS has a built-in 128 character ROM.

The HDSP211XS also has a user definable character

(UDC) feature, which uses a RAM that permits storage of

16 arbitrary characters, symbols or icons that are soft-

ware-definable by the user. The character ROM itself is

mask programmable and easily modified by the manufac-

turer to provide specified custom characters.

–

Individual Flashing Character

Full Display Blinking

Multi-Level Dimming and Blanking

Clear Function

Self Test

•

Internal or External Clock

End Stackable Dual-In-Line Plastic Package

Read/Write Capability

The

HDSP211XS

is

designed

for

standard

microprocessor interface techniques, and is fully TTL

compatible. The Clock I/O and Clock Select pins allow the

user to cascade multiple display modules.

16 User Definable Characters

Standard precautions for CMOS

handling should be observed.

ESD Warning:

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HSDP2110S, HSDP2111S, HSDP2112S, HSDP2113S, HSDP2114S, HSDP2115S

Ordering Information

Type

Color of Emission

Character Height

[inch] ([mm])

Ordering Code

HSDP2110S

HSDP2111S

HSDP2112S

HSDP2113S

HSDP2114S

HSDP2115S

red

Q68000A8560

Q68000A8561

Q68000A8562

Q68000A8563

Q68000A8564

Q68000A8907

yellow

high efficiency red

green

0.200 (5.10)

high efficiency green

soft orange

Package Outlines

Dimensions in inch (mm)

EIA Date

Code

Intensity

Code

Part Number

Color Bin

HDSP211X

OSRAM

Z

YYWW

V

Y

0.3 (0.012) typ.

15.24 (0.600)

2.19 (0.086)

4.79 (0.189)

2.54 (0.100) typ.

0.46 (0.018) typ.

42.67 (1.680) max.

5.34 (0.210)

2.67 (0.105)

Pin 1

Indicator

IDOD5019

Enlarged Character Font

Dimensions in inch (mm)

2.85 (0.112)

C1 C2 C3 C4 C5

R1

R2

R3

R4

R5

R6

R7

0.65 (0.026) typ.

IDOD5201

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HSDP2110S, HSDP2111S, HSDP2112S, HSDP2113S, HSDP2114S, HSDP2115S

Maximum Ratings at 25°C

Parameter

Symbol

T_op

Value

Unit

°C

V

Operating temperature range

Storage temperature range

– 40 … + 85

– 40 … + 100

-0.3 to + 7.0

T_stg

DC Supply Voltage, V_CCto GND

V_CC

(max. voltage with no LEDs on)

Input Voltage Levels

All inputs

-0.3 to V_CC+0.3

V

Operating Voltage, V_CCto GND

(max. voltage with 20 dots/digits on)

+ 5.5

260

V

Solder temperature 063“ (1.59 mm)

below seating plane, t < 5.0 s

T_S

°C

Relative Humidity at 85°C (non-condensing)

85

%

ESD (100 pF, 1.5 kΩ), each pin

V_Z

4.0

kV

Optical Characteristics at 25°C

(V_LL=V_CC=5.0 V at 100% brightness level, viewing angle: X axis ± 55°, Y axis ± 65°)

Description

Symbol

Values

Unit

Peak Luminous Intensity (min.) I_Vpeak

(typ.)

70

90

130

210

150

330

150

200

510

150

270

µcd/dot

260

565

570

Peak Wavelength

(typ.) λ_peak

(typ.) λ_dom

660

639

583

585

630

620

568

574

610

604

nm

Dominant Wavelength

Note:

1)

Peak luminous intensity is measured at T_A=T_J=25°C. No time is allowed for the device to warm up prior to measurement.

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HSDP2110S, HSDP2111S, HSDP2112S, HSDP2113S, HSDP2114S, HSDP2115S

Write Cycle Timing Diagram (Input pulse levels –0.6 V to 2.4 V)

T

acc

A0-A3

FL

T

acs

T

ach

T

acs

T

ce

T

cer

CE

T

ceh

T

ces

T

w

WR

T

wd

T

dh

D0-D7

Input pulse levels —0.6 V to 2.4 v

Read Cycle Timing Diagram

T

acc

A0-A3

FL

T

acs

T

ach

T

acs

T

ce

T

cer

CE

RD

T

ceh

T

ces

T

r

T

rd

T

df

D0-D7

Switching Specifications

(over operating temperature range and V_CC=4.5 V)

Symbol Description

Min.

210

230

10

Units Symbol Description

Min.

Units

ns

T_acc

T_acs

T_ce

Display Access Time—Write

Display Access Time—Read

Address Setup Time to CE

Chip Enable Active Time—Write

Chip Enable Active Time—Read

Address Hold Time to CE

ns

T_dh

T_r

Data Write Time

20

Chip Enable Active Prior to Valid Data 160

ns

T_rd

T_df

T_rc

T_w

T_wd

Read Active Prior to Valid Data

Read Data Float Delay

Reset Active Time

95

µs

140

160

20

10

ns

T_ce

300

100

50

ns

T_ach

T_ces

Write Active Time

ns

Chip Enable Active Prior to

Rising Edge—Write

140

Data Valid Prior to

ns

Rising Edge of Write Signal

T_ces

T_cer

Chip Enable Active Prior to

Rising Edge—Read

160

60

ns

T_ceh

Chip Enable Hold to Rising Edge of

Read/Write Signal

0

ns

Chip Enable Recovery Time

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HSDP2110S, HSDP2111S, HSDP2112S, HSDP2113S, HSDP2114S, HSDP2115S

Cascading Displays

The HDSP211XS oscillator is designed to drive up to 16 other HDSP211XSs with input loading of 15 pF each.

The following are the general requirements for cascading 16 displays together:

• Determine the correct address for each display.

• Use CE from an address decoder to select the correct display.

• Select one of the Displays to provide the clock for the other displays. Connect CLKSEL to V_CCfor this display.

• Tie CLKSEL to ground on other displays.

• Use RTS to synchronize the blinking between the displays.

Cascading Diagram

RD

WR

FL

RST

V_CC

RD WR FL RST CLK CLK

I/O SEL

RD WR FL RST CLK CLK

I/O SEL

Up to 14 more

displays in between

Display

D0-D7 A0-A4

CE

D0-D7 A0-A4

CE

Data I/O

Address

0

A6

A7

A8

A9

Address Decode Chip 1 to 14

Address

Decoder

15

IDCD5031

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HSDP2110S, HSDP2111S, HSDP2112S, HSDP2113S, HSDP2114S, HSDP2115S

Electrical Characteristics at 25°C

Parameters

Limits

Min.

4.5

Conditions

Typ.

5.0

Max.

5.5

Units

V

V_CC

—

I_CCBlank

—

0.65

185

284

–11

1.0

mA

µA

V_CC=5.0 V, V_IN=5.0 V

V_CC=5.0 V, “V” in all 8 digits

V_CC=5.0 V, “#” in all 8 digits

I_CC12 dots/digit on ^{(1) (2)}

I_CC20 dots/digit on ^{(1) (2)}

—

255

370

–5.0

—

I_ILP(with pull-up)

–18

V_CC=5.0 V, V_IN=0 V to V_CC,

Input Leakage

(WR, CE, FL, RST, RD, CLKSEL)

I_IL(no pull-up)

Input Leakage

–1.0

2.0

—

+1.0

µA

V

V_CC=5.0 V, V_IN=0–5 V,

(CLK, A0–A3, D0–D7)

V_IH

V_CC

+0.3

V_CC=4.5 V to 5.5 V

Input Voltage High

V_IL

GND

–0.3

—

V

Input Voltage Low

V_OL(D0–D7), Output Voltage Low

V_OL(CLK), Output Voltage Low

V_OHOutput Voltage High

—

2.4

—

25

0.4

—

V

V_CC=4.5 V, I_OL=1.6 mA

V_CC=4.5 V, I_OL= 40 µA

V_CC=4.5 V, I_OH= –40 µA

—

V

θ

_JCThermal Resistance,

—

°C/W

Junction to Case

Clock I/O Frequency

FM, Digit Multiplex Frequency

Blinking Rate

28

57.34

256

2.0

—

81.14

362.5

2.83

2.40

500

kHz

Hz

V_CC=4.5 to 5.5 V

—

125

0.98

—

Hz

Clock I/O Buss Loading

Clock Out Rise Time

Clock Out Fall Time

Notes:

pF

—

nsec

V_CC=4.5 V, V_OH=2.4 V

V_CC=4.5 V, V_OH=0.4 V

—

500

1)

I_CCis an average value.

I_CCis measured with the display at full brightness. Peak I_CC

2)

28

= /₁₅I_CCaverage (#displayed).

Recommended Operating Conditions (T_A=–40°C to +85°C)

Parameter

Symbol

V_CC

Min.

4.5

—

Max.

5.5

0.8

—

Units

Supply Voltage

V

Input Voltage Low

Input Voltage High

Output Voltage Low

Output Voltage High

V_IL

V_IH

2.0

—

V_OL

0.4

—

V_OH

2.4

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HSDP2110S, HSDP2111S, HSDP2112S, HSDP2113S, HSDP2114S, HSDP2115S

Top View

28

Pins

15

0

1

2

3

4

5

6

7

Digit

Pins

1

14

IDPA5114

Pin Assignment

Function

Definition

Function

Definition

1

RST

Used to initialize a display and sychronize 15

blinking for multiple displays

GND supply

Analog Ground for LED drivers

2

3

4

FL

A0

A1

Low input accesses the Flash RAM

Address input LSB

16

17

18

GND logic

CE

Digital Ground for internal drivers

Enables access to the display

Address input

RD

A low will read data from the display if CE

is low. If read from display is not required,

5

A2

Address input MSB

Mode selector

19

20

21

22

23

24

25

26

D0

Data input LSB

Data input

—

6

A3

D1

7

V_CC

No pin

D2

Optional connection to positive

power supply input.

8

V_CC

—

9

V_CC

Data input

10

11

12

A4

Mode Selector

D3

CLKSEL

CLK I/O

Selects internal/high clock source

D4

Outputs master clock or inputs

external clock

D5

13

14

WR

A low will write data into the display if CE 27

is low

D6

D7

Data input

V_CC

Positive power supply input

28

Data input MSB, selects ROM,

page 1 or 2

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HSDP2110S, HSDP2111S, HSDP2112S, HSDP2113S, HSDP2114S, HSDP2115S

Character Set

D0

D1

D2

D3

L

0

H

L

1

L

H

L

2

H

L

3

L

H

L

4

H

L

H

L

H

L

H

L

H

8

H

L

H

9

L

H

L

H

A

H

L

H

B

L

H

C

H

L

H

D

L

H

F

H

E

ASCII

CODE

D7 D6 D5 D4 HEX

5

6

7

L

H

L

0

1

2

3

4

5

6

L

H

L

H

L

H

L

H

L

H

L

H

X

H

X

H

X

7

8

UDC UDC UDC UDC UDC UDC UDC UDC UDC UDC UDC UDC UDC UDC UDC UDC

H

0

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

IDCS5086

Notes:

1. Upon power up, the device will initialize in a random state.

2. X=don’t care.

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HSDP2110S, HSDP2111S, HSDP2112S, HSDP2113S, HSDP2114S, HSDP2115S

Block Diagram

OSC

32

Counter

7

Counter

3

Counter

Row

Drivers

Column

Drivers

Character

RAM

Decode

8 Digit Display

128

Counter

Character

RAM

Column

Latch

Cursor

Controls

and

Display

MUX

D Latch

Holding

Register

ROM

Word

Decode

ROM

64

5

25

5

Character

Decode

for Display

16

UDC

RAM

Control

Word

Register

Self

Test

Flash

RAM

UDC

Address

Register

Character

Decode

4

Data

Bus

(Read/Write)

IDBD5064

Functional Description

The display's user interface is organized into five memory

areas. They are accessed using the Flash Input, FL, and

address lines, A3 and A4. All the listed RAMs and Regis-

ters may be read or written through the data bus. See

Table „Memory Selection“. Each input pin is described in

Pin Definitions.

RST can be used to initialize display operation upon

power up or during normal operation. When activated,

RST will clear the Flash RAM and Control Word Register

(00H) and reset the internal counter. All eight display

memory locations will be set to 20H to show blanks in all

digits.

FL pin enables access to the Flash RAM. The Flash

RAM will set (D0=1) or reset (D0=0) flashing of the char-

acter addressed by A0–A2.

Five Basic Memory Areas

Character RAM

Stores either ASCII (Katakana)

character data or an UDC RAM

address

The 1 x 8 bit Control Word Register is loaded with

attribute data if A3=0.

Flash RAM

1 x 8 RAM which stores Flash data

The Control Word Logic decodes attribute data for

proper implementation.

User-Defined

Character RAM

(UDC RAM)

Stores dot pattern for custom

characters

Character ROM is designed for 128 ASCII characters.

The ROM is Mask Programmable for custom fonts.

User-Defined Address

Register (UDC Address

Register)

Provides address to UDC RAM

when user is writing or reading

custom character

The Clock Source could either be the internal oscillator

(CLKSEL=1) of the device or an external clock

(CLKSEL=0) could be an input from another HDSP211X

display for the synchronization of blinking for multiple dis-

plays.

Control Word

Register

Enables adjustment of display

brightness, flash individual

characters, blink, self test or clearing

the display

The Display Multiplexer controls the Row Drivers so no

additional logic is required for a display system.

The Display has eight digits. Each digit has 35 LEDs

clustered into a 5 x 7 dot matrix.

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HSDP2110S, HSDP2111S, HSDP2112S, HSDP2113S, HSDP2114S, HSDP2115S

Memory Selection

FL A4 A3

Section of Memory

Flash RAM

A2–A0

Data Bits Used

D0

0

1

X

0

1

X

0

1

0

Character Address

Don’t Care

UDC Address Register

UDC RAM

D3–D0

Row Address

Character Address

Don’t Care

D4–D0

Character RAM

Control Word Register

D7–D0

Theory of operation

The display Blink works the same way as the Flash Enable but

causes all twenty column drivers to cycle at 2.0 Hz thereby making

all eight digits to blink at 2.0 Hz.

The HDSP211XS Programmable Display is designed to work with

all major microprocessors. Data entry is via an eight bit parallel

bus. Three bits of address route the data to the proper digit loca-

tion in the RAM. Standard control signals like WR and CE allow

the data to be written into the display.

The Self Test function of the IC consists of two internal routines

which exercise major portions of the IC and illuminates all the

LEDs.

D0–D7 data bits are used for both Character RAM and control

word data input. A3 acts as the mode selector.

Clear bit clears the character RAM and writes a blank into the dis-

play memory. It however does not clear the control word.

If A3=1, character RAM is selected. Then input data bit D7 will

determine whether input data bits D0–D6 is ASCII coded data

(D7=0) or UDC data (D7=1). See section on UDC Address Regis-

ter and RAM.

ASCII Data or Control Word Data can be written into the display at

this point. For multiple display operation, CLK I/O must be properly

selected. CLK I/O will output the internal clock if CLKSEL=1, or will

allow input from an external clock if CLKSEL=0.

For normal operation FL pin should be held high. When FL is held

low, Flash RAM is accessed to set character blinking.

Character RAM

The Character RAM is selected when FL, A4 and A3 are set to

1,1,1 during a read or write cycle. The Character RAM is a 8 by 8

bit RAM with each of the eight locations corresponding to a digit on

the display. Digit 0 is on the left side of the display and digit 7 is on

the right side of the display. Address lines, A2–A0 select the digit

address with A2 being the most significant bit and A0 being the

least significant bit. The two types of data stored in the Character

RAM are the ASCII coded data and the UDC Address Data. The

type of data stored in the Character RAM is determined by data bit,

D7. If D7 is low, then ASCII coded data is stored in data bits D6–

D0. If D7 is high, then UDC Address Data is stored in data bit D3–

D0.

The seven bit ASCII code is decoded by the Character ROM to

generate Column data. Twenty columns worth of data is sent out

each display cycle, and it takes fourteen display cycles to write into

eight digits.

The rows are multiplexed in two sets of seven rows each. The

internal timing and control logic synchronizes the turning on of

rows and presentation of column data to assure proper display

operation.

Power Up Sequence

Upon power up display will come on at random. Thus the display

should be reset on power-up. The reset will clear the Flash RAM,

Control Word Register and reset the internal counter. All the dig-

its will show blanks and display brightness level will be 100%.

The ASCII coded data is a 7 bit code used to select one of 128

ASCII characters permanently stored in the ASCII ROM.

The UDC Address data is a 4 bit code used to select one of the

UDC characters in the UDC RAM. There are up to 16 characters

available. See Table „Character RAM Access Logic“ (page 11).

The display must not be accessed until three clock pulses

(110 µseconds minimum using the internal clock) after the rising

edge of the reset line.

UDC Address Register and UDC RAM

Microprocessor interface

The UDC Address Register and UDC RAM allows the user to gen-

erate and store up to 16 custom characters. Each custom charac-

ter is defined in 5 x 7 dot matrix pattern. It takes 8 write cycles to

define a custom character, one cycle to load the UDC Address

Register and 7 cycles to define the character. The contents of the

UDC Address Register will store the 4 bit address for one of the 16

UDC RAM locations. The UDC RAM is used to store the custom

character.

The interface to a microprocessor is through the 8-bit data bus

(D0–D7), the 4-bit address bus (A0–A3) and control lines FL, CE

and WR.

To write data (ASCII/Control Word) into the display CE should be

held low, address and data signals stable and WR should be

brought low. The data is written on the low to high transition of

WR.

The Control Word is decoded by the Control Word Decode Logic.

Each code has a different function. The code for display brightness

changes the duty cycle for the column drivers. The peak LED cur-

rent stays the same but the average LED current diminishes

depending on the intensity level.

The character Flash Enable causes 2.0 Hz coming out of the

counter to be ANDED with column drive signal and makes the col-

umn driver to cycle at 2.0 Hz. Thus the character flashes at 2.0 Hz.

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HSDP2110S, HSDP2111S, HSDP2112S, HSDP2113S, HSDP2114S, HSDP2115S

UDC Address Register

Control Word

The UDC Address Register is selected by setting FL=1, A4=0,

A3=0. It is a 4 bit register and uses data bits, D3–D0 to store the

4 bit address code (D7–D4 are ignored). The address code selects

one of 16 UDC RAM locations for custom character generation.

The Control Word is used to set up the attributes required by the

user. It is addressed by setting FL=1, A4=1, A3=0. The Control

Word is an 8 bit register and is accessed using data bits, D7–D0.

See Table „Control Word Access Logic“ (page 12) and Figure

„Control Word Data Definition“ (page 13) for the logic and attrib-

uted control. The Control Word has 5 functions. They are bright-

ness control, flashing character enable, blinking character enable,

self test, and clear (Flash and Character RAMS only).

UDC RAM

The UDC RAM is selected by setting FL=1, A4=0, A3=1. The RAM

is comprised of a 7 x 5 bit RAM. As shown in Table „Flash RAM

Access Logic“ (page 12), address lines, A2–A0 select one of the

7 rows of the custom character. Data bits, D4–D0 determine the

5 bits of column data in each row. Each data bit corresponds to a

LED. If the data bit is high, then the LED is on. If the data bit is low,

the LED is off. To create a character, each of the 7 rows of column

data need to be defined. See Tables „UDCAddress Register and

UDC Character RAM“ (page 11) and „UDC Character Map“

(page 12) for logic.

Brightness Control

Control Word bits, D2–D0, control the brightness of the display

with a binary code of 000 being 100% brightness and 111 being

display blank. See Figure „Control Word Data Definition“ (page 13)

for brightness level versus binary code. The average I_CCcan be

calculated by multiplying the 100% brightness level I_CCvalue by

the display’s brightness level. For example, a display set to 80%

brightness with a 100% average I_CCvalue of 200 mA will have an

average I_CCvalue of 200 mA x 80%=160 mA.

Flash RAM

The Flash RAM allows the display to flash one or more of the char-

acters being displayed. The Flash Ram is accessed by setting FL

low. A4 and A3 are ignored. The Flash RAM is a 8 x 1 bit RAM with

each bit corresponding to a digit address. Digit 0 is on the left side

of the display and digit 7 is on the right side of the display. Address

lines, A2–A0 select the digit address with A2 being the most signif-

icant digit and A0 being the least significant digit. Data bit, D0, sets

and resets the flash bit for each digit. When D0 is high, the flash bit

is set and when D0 is low, It is reset. See Table „Flash RAM

Access Logic“ (page 12).

Flash Function

Control Word bit, D3, enables or disables the Flash Function.

When D3 is 1, the Flash Function is enabled and any digit with its

corresponding bit set in the Flash RAM will flash at approximately

2.0 Hz. When using an external clock, the flash rate can be deter-

mined by dividing the clock rate by 28,672. When D3 is 0, the

Flash Function is disabled and the contents of the Flash RAM is

ignored. For synchronized flashing on multiple displays, see the

Reset Section (page 12)..

Character RAM Access Logic

RST

CE

0

WR

0

RD

1

FL

1

A4

1

A3

1

A2

A1

A0

D7 D6 D5 D4 D3 D2 D1 D0

1

Character Address for Digits 0–7

0

1

7 bit ASCII code for a Write Cycle

0

1

0

1

7 bit ASCII code read during a Read Cycle

D3–D0=UDC address for a Write Cycle

D3–D0=UDC address for Read Data

0

1

0

1

0

1

0

UDC Address Register and UDC Character RAM

RST

CE

WR

RD

FL

A4

A3

A2

A1

A0

D7 D6 D5 D4 D3 D2 D1 D0

1

0

1

0

Not used for UDC

Address Register

D3–D0=UDC RAM Address Code for Write

Cycle

UDC

Address

Register

1

0

1

0

1

0

1

0

1

0

1

Not used for UDC

Address Register

D3–D0=UDC RAM Address Code for Read

Cycle

A2–A0=Character

Row Address

D4–D0=Character Column Data for

Write Cycle

UDC

RAM

A2–A0=Character

Row Address

D4–D0=Character Column Data read

during a Read Cycle

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HSDP2110S, HSDP2111S, HSDP2112S, HSDP2113S, HSDP2114S, HSDP2115S

Blink Function

The second routine provides a visual test of the LEDs using the

drive circuitry. This is accomplished by writing checkered and

inverse checkered patterns to the display. Each pattern is dis-

played for approximately 2.0 seconds. During the self test function

the display must not be accessed. The time needed to execute the

self test function is calculated by multiplying the clock time by

262,144 (typical time=4.6 sec.). At the end of the self test func-

tion, the Character RAM is loaded with blanks; the Control Word

Register is set to zeroes except D5, and the Flash RAM is cleared

and the UDC Address Register is set to all 1.0 s.

Control Word bit, D4, enables or disables the Blink Function. When

D4 is 1, the Blink Function is enabled and all characters on the dis-

play will blink at approximately 2.0 Hz. The Blink Function will over-

ride the Flash Function if both functions are enabled. When D4 is 0,

the Blink Function is disabled. When using an external clock, the

blink rate can be determined by dividing the clock rate by 28,672.

For synchronized blinking on multiple displays, see the Reset Sec-

tion.

Self Test

Clear Function (see Table „Clear Function“ (page 13) and Figure

„Control Word Data Definition“ (page 13))

Before starting Self Test, Reset must first be activated. Control

Word bits, D6 and D5, are used for the Self Test Function. When

D6 is 1, the Self Test is initiated. Results of the Self Test are stored

in bits D5. Control Word bit, D5, is a read only bit. When D5 is 1,

Self Test passed is indicated. When D5 is 0, Self Test failed is indi-

cated. The Self Test function of the IC consists of two internal rou-

tines which exercise major portions of the IC and illuminates all of

the LEDs. The first routine cycles the ASCII decoder ROM through

all states and performs a check sum on the output. If the check

sum agrees with the correct value, D5 is set to a 1.

Control Word bit, D7 clears the character RAM to 20 hex and the

flash RAM to all zeroes. The RAMs are cleared within three clock

cycles (110 µs minimum, using the internal clock) when D7 is set

to 1. During the clear time the display must not be accessed.

When the clear function is finished, bit 7 of the

Control Word RAM will be reset to a “0”.

Reset Function

The display should be reset on power up of the display

(RST=LOW). When the display is reset, the Character RAM, Flash

RAM, and Control Word Register are cleared.

UDC Character Map

Row Data

Column Data

The display's internal counters are reset. Reset cycle takes three

clock cycles (110 µseconds minimum using the internal clock).The

display must not be accessed during this time.

C1

D4

C2

D3

C3

D2

C4

D1

C5

D0

A2

A1

A0

Row #

To synchronize the flashing and blinking of multiple displays, it is

necessary for the display to use a common clock source and reset

all the displays at the same time to start the internal counters at

the same place.

While RST is low, the display must not be accessed by RD nor

WR.

0

1

0

1

0

1

0

1

0

1

0

1

0

1

2

3

4

5

6

7

5 x 7

Dot Matrix

Pattern

Flash RAM Access Logic

RST

CE

WR

RD

FL

A4

A3

A2

A1

A0

D7 D6 D5 D4 D3 D2 D1 D0

1

0

1

0

X

Flash RAM Address

for Digits 0–7

D0=Flash Data, 0-Flash Off and 1=Flash On (Write Cycle)

1

0

1

0

X

Flash RAM Address

for Digits 0–7

D0=Flash Data, 0-Flash Off and 1=Flash On (Read Cycle)

Control Word Access Logic

RST

CE

WR

RD

FL

A4

A3

A2

A1

A0

D7 D6 D5 D4 D3 D2 D1 D0

1

0

1

0

Not used for Control Word Control Word data for a Write Cycle,

see Figure „Control Word Data Definition“ (page 13)

1

0

1

0

1

0

Not used for Control Word Control Word data for a Read during a Read Cycle

2006-01-23

12

HSDP2110S, HSDP2111S, HSDP2112S, HSDP2113S, HSDP2114S, HSDP2115S

Control Word Data Definition

Key

C

D7

D6

D5

D4

D3

D2

D1

D0

Clear

Function

Blink

Function

Flash

Function

Clear Function

Self test

Self Test

Brightness Control

ST

BL

FL

Br

Blink function

Flash function

Brightness control

D2 D1 D0 Brightness Control

0

1

0

1

0

1

0

1

0

1

0

1

100% Brightness

80% Brightness

53% Brightness

40% Brightness

27% Brightness

20% Brightness

13% Brightness

Blank Display

D3 Flash Function

0

1

Disabled

Enabled

D4 Blink Function

0

1

Disabled

Enabled (overrides Flash Function)

D6 D5 Self Test

0

1

X

R

Normal Operation (X = bit ignored)

Run Self Test, R = Test Result (1 = pass, 0 = fail)

D7 Clear Function

0

1

Normal Operation

Clear Flash RAM & Character RAM (Character RAM = 20 Hex)

IDCW5161

Clear Function

CE

WR FL

AL A3

A2

A1

A0

D7

D6

D5

D4

D3

D2

D1

D0

Operation

0

1

0

X

0

1

X

Clear disabled

Clear user RAM, page RAM,

flash RAM and display

X=don’t care

Display Cycle Using Built-in ROM Example

Display message “Showtime.” Digit 0 is leftmost—closest to pin 1.

Logic levels: 0=Low, 1=High, X=Don’t care

RST CE WR RD FL A4 A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0 Operation

Display

0

X

1

X

Reset. No Read/Write All Blank

Within 3 Clock Cycles

1

0

1

0

X

0

X

0

1

53% Brightness

Selected

All Blank

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

Write “S” to Digit 0

Write “H” to Digit 1

Write “O” to Digit 2

Write “W” to Digit 3

Write “T” to Digit 4

Write “I” to Digit 5

Write “M” to Digit 6

Write “E” to Digit 7

S

SH

SHO

SHOW

SHOWT

SHOWTI

SHOWTIM

SHOWTIME

2006-01-23

13

HSDP2110S, HSDP2111S, HSDP2112S, HSDP2113S, HSDP2114S, HSDP2115S

Displaying User Defined Character Example

Load character “A” into UDC-5 and then display it in digit 2

Logic levels: 0=Low, 1=High, X=Don‘t care

RST

CE WR RD FL A4 A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0 Operation

Display

0

X

1

X

Reset. No Read/Write

Within 3 Clock Cycles

All Blank

1

0

1

0

1

0

1

X

0

1

0

X

0

1

0

1

X

0

1

0

1

0

1

0

X

1

X

0

1

X

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

Select UDC-5

All Blank

(Digit 2) A

Write into Row 1 of UDC-5

Write into Row 2 of UDC-5

Write into Row 3 of UDC-5

Write into Row 4 of UDC-5

Write into Row 5 of UDC-5

Write into Row 6 of UDC-5

Write into Row 7 of UDC-5

Write UDC-5 into Digit 2

Electrical and Mechanical Considerations

Voltage Transient Suppression

Post Solder Cleaning Procedures

The least offensive cleaning solution is hot D.I. water (60°C) for

less than 15 minutes. Addition of mild saponifiers is acceptable. Do

not use commercial dishwasher detergents.

For best results power the display and the components that inter-

face with the display to avoid logic inputs higher than V_CC. Addi-

tionally, the LEDs may cause transients in the power supply line

while they change display states. The common practice is to place

a parallel combination of a 0.01 µF and a 22 µF capacitor between

For faster cleaning, solvents may be used. Exercise care in choos-

ing solvents as some may chemically attack the nylon package.

Maximum exposure should not exceed two minutes at elevated

temperatures. Acceptable solvents are TF (trichorotrifluorethane),

TA, 111 Trichloroethane, and unheated acetone.⁽¹⁾

V

_CCand GND for all display packages.

ESD Protection

Note:

The input protection structure of the HDSP211XS provides signifi-

cant protection against ESD damage. It is capable of withstanding

discharges greater than 2.0 kV. Take all the standard precautions,

normal for CMOS components. These include properly grounding

personnel, tools, tables, and transport carriers that come in con-

tact with unshielded parts. If these conditions are not, or cannot be

met, keep the leads of the device shorted together or the parts in

antistatic packaging.

1)

Acceptable commercial solvents are: Basic TF, Arklone, P.

Genesolv, D. Genesolv DA, Blaco-Tron TF and Blaco-Tron TA.

Unacceptable solvents contain alcohol, methanol, methylene

chloride, ethanol, TP35, TCM, TMC, TMS+, TE, or TES. Since

many commercial mixtures exist, contact a solvent vendor for

chemical composition information. Some major solvent manu-

facturers are: Allied Chemical Corporation, Specialty Chemical

Division, Morristown, NJ; Baron-Blakeslee, Chicago, IL; Dow

Chemical, Midland, MI; E.I. DuPont de Nemours & Co., Wilm-

ington, DE.

Soldering Considerations

The HDSP211XS can be hand soldered with SN63 solder using a

grounded iron set to 260°C.

For further information refer to Appnotes 18 and 19 at

www.osram-os.com

Wave soldering is also possible following these conditions:

Preheat that does not exceed 93°C on the solder side of the PC

board or a package surface temperature of 85°C. Water soluble

organic acid flux (except carboxylic acid) or rosin-based RMA flux

without alcohol can be used.

An alternative to soldering and cleaning the display modules is to

use sockets. Naturally, 28 pin DIP sockets .600" wide with .100"

centers work well for single displays. Multiple display assemblies

are best handled by longer SIP sockets or DIP sockets when avail-

able for uniform package alignment. Socket manufacturers are

Aries Electronics, Inc., Frenchtown, NJ; Garry Manufacturing, New

Brunswick, NJ; Robinson-Nugent, New Albany, IN; and Samtec

Electronic Hardward, New Albany, IN.

Direct contact with alcohol or alcohol vapor will cause degradation

of the package.

Wave temperature of 245°C ±5°C with a dwell between 1.5 sec.

to 3.0 sec. Exposure to the wave should not exceed tempera-

tures above 260°C for five seconds at 0.063" below the seating

plane. The packages should not be immersed in the wave.

For further information refer to Appnote 22 at www.osram-os.com

2006-01-23

14

HSDP2110S, HSDP2111S, HSDP2112S, HSDP2113S, HSDP2114S, HSDP2115S

Optical Considerations

The .200" high character of the HDSP211XS gives readability up to eight feet. Proper filter selection enhances readability over this dis-

tance.

Using filters emphasizes the contrast ratio between a lit LED and the character background. This will increase the discrimination of differ-

ent characters. The only limitation is cost. Take into consideration the ambient lighting environment for the best cost/benefit ratio for filters.

Incandescent (with almost no green) or fluorescent (with almost no red) lights do not have the flat spectral response of sunlight. Plastic

band-pass filters are an inexpensive and effective way to strengthen contrast ratios. The HDSP2110/2112S are red/high efficiency red dis-

plays and should be matched with long wavelength pass filter in the 570 nm to 590 nm range. The HDSP2113S should be matched with a

yellow-green band-pass filter that peaks at 565 nm. For displays of multiple colors, neutral density grey filters offer the best compromise.

Additional contrast enhancement is gained by shading the displays. Plastic band-pass filters with built-in louvers offer the next step up in

contrast improvement. Plastic filters can be improved further with anti-reflective coatings to reduce glare. The trade-off is fuzzy characters.

Mounting the filters close to the display reduces this effect. Take care not to overheat the plastic filter by allowing for proper air flow.

Optimal filter enhancements are gained by using circular polarized, anti-reflective, band-pass filters. The circular polarizing further

enhances contrast by reducing the light that travels through the filter and reflects back off the display to less than 1%.

Several filter manufacturers supply quality filter materials. Some of them are: Panelgraphic Corporation, W. Caldwell, NJ; SGL Homalite,

Wilmington, DE; 3M Company, Visual Products Division, St. Paul, MN; Polaroid Corporation, Polarizer Division, Cambridge, MA; Marks

Polarized Corporation, Deer Park, NY, Hoya Optics, Inc., Fremont, CA.

One last note on mounting filters: recessing displays and bezel assemblies is an inexpensive way to provide a shading effect in overhead

lighting situations. Several bezel manufacturers are: R.M.F. Products, Baklava, IL; Nobody Components, Griffith Plastic Corp., Burningly,

CA; Photo Chemical Products of California, Santa Monica, CA; I.E.E.-Atlas, Van Nuys, CA.

2006-01-23

15

HSDP2110S, HSDP2111S, HSDP2112S, HSDP2113S, HSDP2114S, HSDP2115S

Revision History: 2006-01-23

Previous Version: 2004-11-11

Page

Subjects (major changes since last revision)

Date of change

all

Lead free device

2006-01-23

Published by

OSRAM Opto Semiconductors GmbH

Wernerwerkstrasse 2, D-93049 Regensburg

www.osram-os.com

Attention please!

The information describes the type of component and shall not be considered as assured characteristics.

Terms of delivery and rights to change design reserved. Due to technical requirements components may contain

dangerous substances. For information on the types in question please contact our Sales Organization.

If printed or downloaded, please find the latest version in the Internet.

Packing

Please use the recycling operators known to you. We can also help you – get in touch with your nearest sales office.

By agreement we will take packing material back, if it is sorted. You must bear the costs of transport. For packing

material that is returned to us unsorted or which we are not obliged to accept, we shall have to invoice you for any costs

incurred.

Components used in life-support devices or systems must be expressly authorized for such purpose! Critical

components¹⁾may only be used in life-support devices or systems²⁾with the express written approval of OSRAM OS.

1)

A critical component is a component used in a life-support device or system whose failure can reasonably be expected to cause the

failure of that life-support device or system, or to affect its safety or the effectiveness of that device or system.

Life support devices or systems are intended (a) to be implanted in the human body, or (b) to support and/or maintain and sustain

2)

human life. If they fail, it is reasonable to assume that the health and the life of the user may be endangered.

2006-01-23

16


型号：	Q68000A8560
厂家：	OSRAM GMBH
描述：	Alphanumeric Intelligent Display Devices
文件：	总16页 (文件大小：977K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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