UHP112 [OXFORD]
Two-Port PCI-to-USB OpenHCI Host Controller - Product Brief; 双端口PCI到USB OpenHCI主机控制器 - 产品简介
| 型号： | UHP112 |
| 厂家： | 
OXFORD SEMICONDUCTOR |
| 描述： | Two-Port PCI-to-USB OpenHCI Host Controller - Product Brief |
| 文件： | 总8页 (文件大小：141K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
UHP112
Two-Port PCI-to-USB OpenHCI Host Controller - Product Brief
The UHP112 is a 3.3 V device fabricated in 0.35 µm
Features
technology. Integrated dual-speed USB transceivers
enable a single-chip PCI-to-USB solution.
Q 32-bit, 33 MHz PCI interface compliant with PCI
Local Bus Specification Revision 2.1s
The UHP112 supports the legacy peripherals feature,
as defined in the OpenHCI Specification Release
1.0a.
Q Two downstream USB ports
Q Full compliance with Universal Serial Bus Specifi-
An advanced power management capabilities inter-
face compliant with PCI Bus Power Management
Interface Specification Revision 1.1 is present to offer
a variety of power-savings modes to the host system.
cation Revision 1.1
Q OpenHCI Open Host Controller Interface Specifi-
cation for USB Release 1.0a compatible
Q Provides advanced power management capabili-
ties compliant with PCI Bus Power Management
Interface Specification Revision 1.1
The UHP112 provides two downstream USB ports for
connectivity with any USB compliant device or hub.
Full-speed or low-speed peripherals are supported
along with all of the USB transfer types: control, inter-
rupt, bulk, or isochronous. The UHP112’s OpenHCI
compliance offers significant USB performance
benefits and reduced CPU overhead compared to
other host controllers.
Q Fully compatible with Microsoft Windows*Standard
OpenHCD Drivers
Q Supports legacy keyboard and mouse devices
Q Integrated dual-speed USB transceivers
Q 3 V or 5 V switchable PCI signaling
Q 100-pin TQFP
The UHP112 is fully compatible with the Microsoft
Windows Standard OpenHCD Drivers.
The UHP112 is supported natively as an OHCI
compliant host controller under Windows 98, ME, XP
and CE, as well as under MacOS and Linux. For
customers using other operating systems, Soft-
Connex Technologies’ USBLink Host solution
supports a wide range of products, such as AMX,
ITRON, Linux, LynxOS, MS-DOS, Nucleus, OS-40,
PowerTV, QNX, ThreadX, VRTX and VxWorks.
Q Evaluation kit available
Applications
Q Seamless integration with 3 V or 5 V PCI-based
computer products
Q Supports all USB compliant devices and hubs
USBLink Host is also distinguished by the variety of
USB devices that it can support, including: printers;
audio, communication, human interface and mass
storage devices; digital still and video cameras;
Hubs; MP3 players; Host to Host cables and Blue-
tooth connectivity products. In addition, USBLink
Host runs on both little endian (x86, ARM, SA, SH,
ST) and big endian (PPC, MIPS) processors. For
more information, please visit www.softconnex.com.
Description
The Transdimension’s UHP112 provides a single-
chip PCI-to-Universal Serial Bus (USB) solution. The
UHP112 interfaces directly to any 32-bit 33 MHz PCI
bus and is ideal for either onboard applications or
add-in card applications. It can easily be configured
to communicate in either a 3 V PCI environment or
5 V PCI environment simply by selecting the appro-
priate communications voltage level on the VIO input
pin.
*SoftConnex Technologies is a wholly owned subsidiary of Trans-
dimension Inc.
* Microsoft and Windows are registered trademarks of Microsoft
Corporation.
UHP112
Two-Port PCI-to-USB OpenHCI Host Controller
Description (continued)
UHP112 PCI-TO-USB OpenHCI HOST CONTROLLER
ROM
BIOS
MASTER
FIFOs
ADDRESS
OHCI
ROOT
HUB
W DATA
DATA
ADDRESS
ADDRESS/
DATA
DATA
R DATA
ADDRESS
R DATA
HCI
CONTROL
CONTROL
USB
ADDRESS/
DATA
DATA
DATA
ROOT
HUB
AND
HOST
SIE
SLAVE
BLOCK
STATE
PORT
1
PARITY
USB
USB
CONTROL
MUX
TX
RX
CONTROL
ADDRESS
CONTROL
OHCI
REG
LIST
PORT
2
W DATA
CLOCK
MUX
CONTROL
CONTROL
PROCESSOR
BLOCK
CONTROL
SLAVE
FIFOs
12/1.5
DATA
ED AND TD
REGS
DATA
IDSEL
CONFIG.
BLOCK
STATUS
HCI
ADDRESS/
DATA
HSIE
S/M
MASTER
BLOCK
STATUS
DATA
DATA
DATA
DATA
CONTROL
PCI
64 x 8
FIFO
DPLL
SLAVE
CONTROL
CONTROL
PCI
FIFO STATUS
F-BUS CONTROL
F-BUS IRQ
MASTER
CONTROL
PCI
CONTROL
FIFO
INTA
INTR.
64 x 8
BLOCK
5-5596.b
Figure 1. UHP112 Interconnection Diagram
Applicable Documents and Specifications
Q PCI Local Bus Specification Revision 2.1s., June 1, 1995. PCI Special Interest Group.
Q Universal Serial Bus Specification Revision 1.1., September 23, 1998. Compaq/Digital Equipment Corporation/
IBM PC Company/Intel/Microsoft/NEC/Northern Telecom.
Q OpenHCI Open Host Controller Interface Specification for USB Release 1.0a., July 31, 1997. Compaq/Microsoft/
National Semiconductor.
Q PCI Bus Power Management Interface Specification Revision 1.1., December 18, 1998. PCI Special Interest
Group.
2
Transdimension Inc.
UHP112
Two-Port PCI-to-USB OpenHCI Host Controller
Pin Information (continued)
A20MN
AD2
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
SERRN
VDD
1
2
3
4
5
6
7
8
AD1
MIRQ12I
VSS
AD0
VSS
PERRN
STOPN
DEVSELN
TRDYN
IRDYN
VSS
CLK48
VDD
PMEN
PRTPWR1
PWRFLT1N
PWROK1
VDDT
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
VDD
FRAMEN
C/BEN2
AD16
AD17
VDD
DPLS1
DMNS1
PMIENABLE
VSST
TDUHP112
VSS
VDDT
AD18
AD19
AD20
AD21
VSS
DPLS2
DMNS2
VSS
TEST0
PWROK2
PWRFLT2N
PRTPWR2
TEST1
A20I
AD22
AD23
5-7220a
Figure 2. Pin Diagram (100-Pin TQFP)
Transdimension Inc.
3
UHP112
Two-Port PCI-to-USB OpenHCI Host Controller
Pin Information (continued)
Table 1. Numeric Pin Cross Reference
Pin
Symbol*
Pin
Symbol*
Pin
Symbol*
Pin
Symbol*
1
A20MN
AD2
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
VDD5
IRQ1
IRQ12
SMIN
INTAN
RSTN
CLK
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
AD23
AD22
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
PAR
C/BEN1
AD15
AD14
VSS
2
3
AD1
A20I
4
AD0
VSS
CLK48
VDD
PMEN
VSS
5
AD21
6
AD20
VDD
7
AD19
AD13
AD12
AD11
VSS
AD10
AD9
AD8
8
VSS
AD18
9
PRTPWR1
PWRFLT1N
PWROK1
VDDT
VDD
VSS
VDD
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
GNTN
REQN
AD31
AD30
AD29
VSS
AD17
AD16
DPLS1
DMNS1
PMIENABLE
VSST
C/BEN2
FRAMEN
VDD
C/BEN0
VSS
VDD
VSS
VIO
VDDT
AD28
AD27
AD26
AD25
VDD
IRDYN
TRDYN
DEVSELN
STOPN
PERRN
VSS
VDD
DPLS2
DMNS2
VSS
AD7
AD6
AD5
TEST0
PWROK2
PWRFLT2N
PRTPWR2
TEST1
VSS
VSS
KIRQ1I
VDD
AD24
C/BEN3
IDSEL
MIRQ12I
VDD
SERRN
AD4
AD3
* Active-low signals within this document are indicated by an N following the symbol names.
4
Transdimension Inc.
UHP112
Two-Port PCI-to-USB OpenHCI Host Controller
Pin Information (continued)
Table 2. Pin Descriptions
Pin
Symbol*
Type
Description
1
2
3
4
5
6
7
8
9
A20MN
AD2
Output/Open Drain Legacy Gate A20 Output (Active-Low).
Bidir
Bidir
PCI Address/Data Bit.
PCI Address/Data Bit.
PCI Address/Data Bit.
Device Ground.
USB Clock (48 MHz).
Device Power (3.3 V).
AD1
AD0
VSS
CLK48
VDD
PMEN
PRTPWR1
Bidir
Power
Input
Power
Output/Open Drain Power Management Event (Active-Low).
Bidir
Input
Input
Port 1 Power. Logic output expected to turn on port 1 power. Boot-
strap low for high active. Bootstrap high for low active.
10
11
PWRFLT1N
PWROK1
Port 1 Power Fault (Active-Low). Logic input indicates an overcur-
rent fault on port 1.
Port 1 Power OK. Analog or digital input to inform the UHP112 that
USB port 1 power is stable (when >4 V).
12
13
14
15
16
17
18
19
20
21
VDDT
DPLS1
DMNS1
PMIENABLE
VSST
Power
Bidir
Bidir
Transceiver Power (3.3 V).
DIfferential USB Port 1 Signals.
Input
Power
Power
Bidir
Power Management Interface Enable Input (Active-High).
Transceiver Ground.
VDDT
Transceiver Power (3.3 V).
DPLS2
DMNS2
VSS
Differential USB Port 2 Signals.
Bidir
Power
Input
Device Ground.
TEST0
Test 0. For device testing. Connect this to ground during normal use.
Connect to logic high for NAND tree mode. See NAND Tree Mode
on page 2-32.
22
23
24
25
PWROK2
PWRFLT2N
PRTPWR2
TEST1
Input
Input
Bidir
Input
Port 2 Power OK. Analog or digital input to inform the UHP112 that
USB port 2 power is stable (when >4 V).
Port 2 Power Fault (Active-Low). Logic input indicates an overcur-
rent fault on port 2.
Port 2 Power. Logic output expected to turn on port 2 power. Boot-
strap low for high active. Bootstrap high for low active.
Test 1. For device testing. Tie this to ground during normal use.
Connect to logic high for NAND tree mode. See the NAND Tree
Mode section on page 2-32.
26
VDD5
Power
5 V Power for 5 V PCI Operation. 5 V must be present on this pin
while selecting either 3 V PCI or 5 V PCI operation with the VIO pin.
See PCI Connection Instructions section on page 2-26.
27
28
29
30
31
32
IRQ1
IRQ12
SMIN
INTAN
RSTN
CLK
Output/Open Drain System Keyboard Interrupt (Active-High).
Output/Open Drain System Mouse Interrupt (Active-High).
Output/Open Drain System Management Interrupt (Active-Low).
Output/Open Drain PCI Interrupt (Active-Low).
Input
Input
PCI Reset (Active-Low). Also the chip reset.
PCI Clock. 33 MHz input clock.
* Active-low signals within this document are indicated by an N following the symbol names.
Transdimension Inc.
5
UHP112
Two-Port PCI-to-USB OpenHCI Host Controller
Pin Information (continued)
Table 2. Pin Descriptions (continued)
Pin
Symbol*
Type
Description
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
VSS
VDD
Power
Power
Input
Output/3-State
Bidir
Device Ground.
Device Power (3.3 V).
GNTN
REQN
AD31
AD30
AD29
VSS
PCI Grant Signal (Active-Low).
PCI Request Signal (Active-Low).
PCI Address/Data Bit.
PCI Address/Data Bit.
PCI Address/Data Bit.
Device Ground.
Device Power (3.3 V).
PCI Address/Data Bit.
PCI Address/Data Bit.
PCI Address/Data Bit.
PCI Address/Data Bit.
Device Power (3.3 V).
Device Ground.
PCI Address/Data Bit.
PCI Command/Byte Enable.
PCI ID Select.
PCI Address/Data Bit.
PCI Address/Data Bit.
Legacy Gate A20 Input.
Device Ground.
PCI Address/Data Bit.
PCI Address/Data Bit.
PCI Address/Data Bit.
PCI Address/Data Bit.
Device Ground.
Device Power (3.3 V).
PCI Address/Data Bit.
PCI Address/Data Bit.
PCI Command/Byte Enable.
PCI Frame (Active-Low).
Device Power (3.3 V).
Device Ground.
PCI Initiator Ready (Active-Low).
PCI Target Ready (Active-Low).
PCI Device Select (Active-Low).
PCI Stop (Active-Low).
PCI Parity Error (Active-Low).
Device Ground.
Bidir
Bidir
Power
Power
Bidir
VDD
AD28
AD27
AD26
AD25
VDD
Bidir
Bidir
Bidir
Power
Power
Bidir
VSS
AD24
C/BEN3
IDSEL
AD23
AD22
A20I
Bidir
Bidir
Bidir
Bidir
Input
Power
Bidir
VSS
AD21
AD20
AD19
AD18
VSS
Bidir
Bidir
Bidir
Power
Power
Bidir
VDD
AD17
AD16
C/BEN2
FRAMEN
VDD
Bidir
Bidir
Bidir
Power
Power
Bidir
VSS
IRDYN
TRDYN
DEVSELN
STOPN
PERRN
VSS
Bidir
Bidir
Bidir
Bidir
Power
Input
Power
MIRQ12I
Legacy Mouse Controller Interrupt Input.
Device Power (3.3 V).
VDD
* Active-low signals within this document are indicated by an N following the symbol names.
6
Transdimension Inc.
UHP112
Two-Port PCI-to-USB OpenHCI Host Controller
Pin Information (continued)
Table 2. Pin Descriptions (continued)
Pin
Symbol*
Type
Description
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
SERRN
PAR
Output/Open Drain PCI System Error (Active-Low).
Bidir
Bidir
PCI Parity.
C/BEN1
AD15
AD14
VSS
PCI Command/Byte Enable.
PCI Address/Data Bit.
PCI Address/Data Bit.
Device Ground.
Device Power (3.3 V).
PCI Address/Data Bit.
PCI Address/Data Bit.
PCI Address/Data Bit.
Device Ground.
PCI Address/Data Bit.
PCI Address/Data Bit.
PCI Address/Data Bit.
PCI Command/Byte Enable.
Device Ground.
Bidir
Bidir
Power
Power
Bidir
Bidir
Bidir
VDD
AD13
AD12
AD11
VSS
Power
Bidir
AD10
AD9
AD8
C/BEN0
VSS
VIO
Bidir
Bidir
Bidir
Power
Power
Voltage I/O. This signal is used to indicate to the UHP112 the PCI
signaling interface to use (3 V or 5 V PCI signaling). A 3 V on VIO
will indicate 3 V PCI signaling while 5 V on VIO will indicate 5 V PCI
signaling. This pin may be connected directly to the PCI VIO signal.
92
93
94
95
96
97
98
99
100
VDD
AD7
AD6
AD5
VSS
KIRQ1I
VDD
Power
Bidir
Device Power (3.3 V).
PCI Address/Data Bit.
PCI Address/Data Bit.
PCI Address/Data Bit.
Device Ground.
Legacy Keyboard Controller Interrupt Input.
Device Power (3.3 V).
PCI Address/Data Bit.
PCI Address/Data Bit.
Bidir
Bidir
Power
Input
Power
Bidir
AD4
AD3
Bidir
* Active-low signals within this document are indicated by an N following the symbol names.
Transdimension Inc.
7
For additional information, contact your Transdimension Regional Sales Representitive:
INTERNET:
E-MAIL:
http://www.transdimension.com
sales@transdimension.com, techsupport@transdimension.com
Headquarters TransdimensionInc., 2 Venture, Irvine, CA 92618. Tel 949-727-2020, FAX 949-727-3232
/N. America
Pete Todd, V.P. of Worldwide Sales: email: ptodd@transdimension.com
JAPAN:
TransdimensionInc., OYA Bldg. 5, 3 Chome-9-6, Nishi-shinjuku, Shinjuku-ku, Tokyo, Japan
Tel. +81 (3) 5308 7525, FAX +81 (3) 5308 752, Masanori Sugane, e-mail: sugane@transdimension.com
EUROPE:
Transdimension Inc., 7 The Orchard, Hilton, Derbyshire, UK, DE65 5JF.
Tel. +44 1283 730045, FAX +44 1283 730651, Neil Huntingdon, e-mail: nhungtingdon@transdimension.com
WorldWide Reps: See detailed listing for your area Transdimension representitive by viewing http://www.transdimension.com
THE DEVICE AND ITS DOCUMENTATION ARE PROVIDED “AS IS”. TRANSDIMENSION HEREBY DISCLAIMS ALL WARRANTIES, EXPRESS, STATUTORY AND IMPLIED, APPLICABLE TO THE SOFTWARE AND ITS DOCUMENTATION AND ANY RELATED
PRODUCTS, INCLUDING, BUT NOT LIMITED TO, ANY WARRANTY OF MERCHANTABILITY, NON-INFRINGEMENT OR FITNESS FOR A PARTICULAR PURPOSE. TRANSDIMENSION ASSUMES NO LIABILITY FOR ANY ACT OR OMISSION OF LICENSEE.
IN NO EVENT SHALL TRANSDIMENSION BE LIABLE FOR DIRECT, SPECIAL, INDIRECT, INCIDENTAL, PUNITIVE, EXEMPLARY OR CONSEQUENTIAL DAMAGES, INCLUDING, WITHOUT LIMITATION, LOSS OF PROFITS OR REVENUE, LOSS OF PRODUCTS,
DATA OR ANY ASSOCIATED EQUIPMENT, COST OF CAPITAL, COST OF SUBSTITUTED EQUIPMENT OR PARTS, FACILITIES OR SERVICES, DOWN-TIME OR LABOR COSTS, EVEN IF TRANSDIMENSION HAS BEEN ADVISED OF THE POSSIBILITY THERE-
OF. The device and any related products are not designed, authorized, or warranted to be suitable for use in life-support devices or systems or other critical applications. Any such use and subsequent liabilities that may arise from such use are totally the responsibilities
of the Licensee. Copyright © 2002, TransDimension Inc., All rights reserved. All product names are trademarks or registered trademarks of their respective owners. This document is subject to changes without notice.
All Rights Reserved
Printed in U.S.A.
MFeUbru3ar0y02200,2Rev. 1.0
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