PSL12-N [PACELEADER]
SILICON EPITAXIAL PLANER TYPE; 硅外延平面型![PSL12-N](http://pdffile.icpdf.com/pdf1/p00131/img/icpdf/PSL12_725671_icpdf.jpg)
型号: | PSL12-N |
厂家: | ![]() |
描述: | SILICON EPITAXIAL PLANER TYPE |
文件: | 总2页 (文件大小:254K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
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PSL12-N thru PSL14-N
SILICON EPITAXIAL PLANER TYPE
Low VF Chip Schottky Diodes
SOD-323
0.106 (2.7)
0.091 (2.3)
0.012(0.3) Typ.
0.057 (1.45)
0.041 (1.05)
0.047 (1.2)
0.031 (0.8)
0.016(0.4) Typ.
0.016(0.4) Typ.
Dimensions in inches and (millimeters)
FEATURES
MECHANICAL DATA
Plastic package has Underwriters Laboratory
Flammability Classification 94V-0 Ufizing Flame
Retardant Epoxy Molding Compound.
For surface mounted applications.
Case JEDEC SOD-323 molded plastic
Terminals Solder plated, solderable per
MIL-STD-750, Method 2026
Polarity Indicated by cathode band
Mounting Position Any
Exceeds environmental standards of ML-S-19500/228
Low leakage current
o
MAXIMUM RATINGS (at TA=25 C unless otherwise noted)
Typ.
PARAMETER
CONDITIONS
SYMBOL
Min.
Max.
1.0
UNITS
A
See Fig.2
Forward rectified current
IO
8.3ms Single Half Sine-Wave Superimposed
on Rated Load (JEDEC Method)
Forward surge current
A
IFSM
30
0
mA
mA
1.0
10
VR=VRRM TA=25 C
Reverse current
IR
0
VR=VRRM TA=100 C
0
RJA
CJ
80
C / W
Thermal resistance
Junction to ambient
pF
Diode junction capacitance
Storage temperature
F=1MHz and applied 4vDC reverse voltage
130
0
TSTG
-55
+150
C
*1
*2
*3
*4
Operating Temperature
VRRM
VRMS
VR
VF
SYMBOLS
MARKING CODE
0
( C)
(V)
(V)
(V)
(V)
PSL12-N
PSL13-N
PSL14-N
L2
L3
L4
20
30
40
14
21
28
20
30
40
0.38
0.40
0.40
-55 to + 125
*1 Repetitive peak reverse peak reverse
*2 RMS voltage
*3 Continuous reverse voltage
*4 Maximum forward voltage
www.paceleader.tw
1
PSL12-N thru PSL14-N
SILICON EPITAXIAL PLANER TYPE
Crownpo Technology
www.paceleader.tw
2
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