PFS123-S20 [PADAUK]
8bit MTP Type MCU with 12-bit R-Type ADC;型号: | PFS123-S20 |
厂家: | PADAUK Technology |
描述: | 8bit MTP Type MCU with 12-bit R-Type ADC |
文件: | 总104页 (文件大小:2388K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
PFS123
8bit MTP Type MCU with 12-bit R-Type ADC
Data Sheet
Version 0.00
Aug. 26, 2020
Copyright 2020 by PADAUK Technology Co., Ltd., all rights reserved.
6F-6, No.1, Sec. 3, Gongdao 5th Rd., Hsinchu City 30069, Taiwan, R.O.C.
TEL: 886-3-572-8688 www.padauk.com.tw
PFS123
8bit MTP MCU with 12-bit R-Type ADC
IMPORTANT NOTICE
PADAUK Technology reserves the right to make changes to its products or to terminate
production of its products at any time without notice. Customers are strongly
recommended to contact PADAUK Technology for the latest information and verify
whether the information is correct and complete before placing orders.
PADAUK Technology products are not warranted to be suitable for use in life-support
applications or other critical applications. PADAUK Technology assumes no liability for
such applications. Critical applications include, but are not limited to, those which may
involve potential risks of death, personal injury, fire or severe property damage.
PADAUK Technology assumes no responsibility for any issue caused by a customer’s
product design. Customers should design and verify their products within the ranges
guaranteed by PADAUK Technology. In order to minimize the risks in customers’ products,
customers should design a product with adequate operating safeguards.
©Copyright 2020, PADAUK Technology Co. Ltd
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8bit MTP MCU with 12-bit R-Type ADC
Table of content
1. Features.................................................................................................................................8
1.1.
1.2.
1.3.
1.4.
Special Features.....................................................................................................................8
System Features.....................................................................................................................8
CPU Features.........................................................................................................................8
Package Information ...............................................................................................................8
2. General Description and Block Diagram............................................................................9
3. Pin Assignment and Description ......................................................................................10
4. Device Characteristics.......................................................................................................18
4.1.
4.2.
4.3.
4.4.
4.5.
4.6.
4.7.
4.8.
4.9.
AC/DC Device Characteristics ..............................................................................................18
Absolute Maximum Ratings...................................................................................................20
Typical ILRC frequency vs. VDD...........................................................................................20
Typical IHRC frequency deviation vs. VDD (calibrated to 16MHz).........................................21
Typical ILRC Frequency vs. Temperature.............................................................................21
Typical IHRC Frequency vs. Temperature (calibrated to 16MHz)..........................................22
Typical operating current vs. VDD @ system clock = ILRC/n................................................22
Typical operating current vs. VDD @ system clock = IHRC/n ...............................................23
Typical operating current vs. VDD @ system clock = 4MHz EOSC / n..................................23
4.10. Typical operating current vs. VDD @ system clock = 32KHz EOSC / n.................................24
4.11. Typical operating current vs. VDD @ system clock = 1MHz EOSC / n..................................24
4.12. Typical IO driving current (IOH) and sink current (IOL) .............................................................25
4.13. Typical IO input high/low threshold voltage (VIH/VIL) ..............................................................27
4.14. Typical resistance of IO pull high/low device .........................................................................27
4.15. Typical power down current (IPD) and power save current (IPS)..............................................29
5. Functional Description.......................................................................................................30
5.1.
5.2.
Program Memory - MTP........................................................................................................30
Boot Procedure.....................................................................................................................30
1.2.1. Timing charts for reset conditions..............................................................................31
Data Memory - SRAM...........................................................................................................32
Oscillator and clock...............................................................................................................32
5.4.1. Internal High RC oscillator and Internal Low RC oscillator.........................................32
5.4.2. Chip calibration..........................................................................................................32
5.4.3. IHRC Frequency Calibration and System Clock ........................................................33
5.4.4. External Crystal Oscillator .........................................................................................34
5.4.5. System Clock and LVR level .....................................................................................36
5.3.
5.4.
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8bit MTP MCU with 12-bit R-Type ADC
5.4.6. System Clock Switching ............................................................................................37
Comparator...........................................................................................................................38
5.5.1 Internal reference voltage (Vinternal R)...........................................................................39
5.5.2 Using the comparator ................................................................................................41
5.5.3 Using the comparator and band-gap 1.20V ...............................................................42
VDD/2 LCD Bias Voltage Generator .....................................................................................43
16-bit Timer (Timer16) ..........................................................................................................44
8-bit Timer (Timer2/Timer3) with PWM generation................................................................46
5.8.1 Using the Timer2 to generate periodical waveform....................................................47
5.8.2 Using the Timer2 to generate 8-bit PWM waveform...................................................49
5.8.3 Using the Timer2 to generate 6-bit PWM waveform...................................................50
11-bit PWM Generator ..........................................................................................................51
5.9.1 PWM Waveform ........................................................................................................51
5.9.2 Hardware Diagram ....................................................................................................52
5.9.3 Equations for 11-bit PWM Generator.........................................................................53
5.9.4 PWM Waveforms with Complementary Dead Zones .................................................54
5.5.
5.6
5.7
5.8
5.9
5.10 WatchDog Timer...................................................................................................................56
5.11 Interrupt ................................................................................................................................56
5.12 Power-Save and Power-Down ..............................................................................................59
5.12.1 Power-Save mode (“stopexe”)...................................................................................59
5.12.2 Power-Down mode (“stopsys”) ..................................................................................60
5.12.3 Wake-up....................................................................................................................61
5.13 IO Pins..................................................................................................................................61
5.14 Reset and LVR......................................................................................................................62
5.14.1 Reset.........................................................................................................................62
5.14.2 LVR reset ..................................................................................................................62
5.15 Analog-to-Digital Conversion (ADC) module .........................................................................63
5.15.1 The input requirement for AD conversion ..................................................................64
5.15.2 Select the reference high voltage ..............................................................................64
5.15.3 ADC clock selection...................................................................................................64
5.15.4 Configure the analog pins..........................................................................................65
5.15.5 Using the ADC...........................................................................................................65
5.15.6 How to calculate ADC input voltage VIN .....................................................................66
6. IO Registers ........................................................................................................................67
6.1.
6.2.
6.3.
ACC Status Flag Register (flag), IO address = 0x00 .............................................................67
Stack Pointer Register (sp), IO address = 0x02 ....................................................................67
Clock Mode Register (clkmd), IO address = 0x03 .................................................................67
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8bit MTP MCU with 12-bit R-Type ADC
6.4.
6.5.
6.6.
6.7.
6.8.
6.9.
Interrupt Enable Register (inten), IO address = 0x04 ............................................................68
Interrupt Request Register (intrq), IO address = 0x05...........................................................68
Timer16 mode Register (t16m), IO address = 0x06...............................................................69
External Oscillator setting Register (eoscr), IO address = 0x0a.............................................69
Interrupt Edge Select Register (integs), IO address = 0x0c...................................................70
Port A Digital Input Enable Register (padier), IO address = 0x0d..........................................70
6.10. Port B Digital Input Enable Register (pbdier), IO address = 0x0e..........................................71
6.11. Port C Digital Input Enable Register (pcdier), IO address = 0x0f...........................................71
6.12. Port A Data Register (pa), IO address = 0x10.......................................................................71
6.13. Port A Control Register (pac), IO address = 0x11 .................................................................71
6.14. Port A Pull-High Register (paph), IO address = 0x12 ............................................................72
6.15. Port B Data Register (pb), IO address = 0x13.......................................................................72
6.16. Port B Control Register (pbc), IO address = 0x14 .................................................................72
6.17. Port B Pull-High Register (pbph), IO address = 0x15 ............................................................72
6.18. Port C Data Register (pc), IO address = 0x16.......................................................................72
6.19. Port C Control Register (pcc), IO address = 0x17 .................................................................72
6.20. Port C Pull-High Register (pcph), IO address = 0x18 ............................................................72
6.21. Port B Pull-Low Register (pbpl), IO address = 0x19 ..............................................................73
6.22. Port C Pull-Low Register (pcpl), IO address = 0x1a ..............................................................73
6.23. ADC Control Register (adcc), IO address = 0x20..................................................................73
6.24. ADC Mode Register (adcm), IO address = 0x21 ...................................................................74
6.25. ADC Result High Register (adcrh), IO address = 0x22..........................................................74
6.26. ADC Result Low Register (adcrl), IO address = 0x23............................................................74
6.27. ADC Regulator Control Register (adcrgc), IO address = 0x24...............................................74
6.28. MISC Register (misc), IO address = 0x26.............................................................................75
6.29. Comparator Control Register (gpcc), IO address = 0x2b.......................................................75
6.30. Comparator Selection Register (gpcs), IO address = 0x2c....................................................76
6.31. Timer2 Control Register (tm2c), IO address = 0x30 ..............................................................76
6.32. Timer2 Counter Register (tm2ct), IO address = 0x31 ............................................................76
6.33. Timer2 Scalar Register (tm2s), IO address = 0x32................................................................77
6.34. Timer2 Bound Register (tm2b), IO address = 0x33 ...............................................................77
6.35. Timer3 Control Register (tm3c), IO address = 0x34 ..............................................................77
6.36. Timer3 Counter Register (tm3ct), IO address = 0x35 ............................................................78
6.37. Timer3 Scalar Register (tm3s), IO address = 0x36................................................................78
6.38. Timer3 Bound Register (tm3b), IO address = 0x37 ...............................................................78
6.39. PWMG0 control Register (pwmg0c), IO address = 0x40 .......................................................78
6.40. PWMG Clock Register (pwmgclk), IO address = 0x41 ..........................................................79
6.41. PWMG0 Duty Value High Register (pwmg0dth), IO address = 0x42 .....................................79
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8bit MTP MCU with 12-bit R-Type ADC
6.42. PWMG0 Duty Value Low Register (pwmg0dtl), IO address = 0x43 .......................................79
6.43. PWMG Counter Upper Bound High Register (pwmgcubh ), IO address = 0x44 ....................79
6.44. PWMG Counter Upper Bound Low Register (pwmgcubl ), IO address = 0x45 ......................79
6.45. PWMG1 control Register (pwmg1c), IO address = 0x46 .......................................................80
6.46. PWMG1 Duty Value High Register (pwmg1dth), IO address = 0x48 .....................................80
6.47. PWMG1 Duty Value Low Register (pwmg1dtl), IO address = 0x49 .......................................80
6.48. PWMG2 control Register (pwmg2c), IO address = 0x4C.......................................................81
6.49. PWMG2 Duty Value High Register (pwmg2dth), IO address = 0x4E.....................................81
6.50. PWMG2 Duty Value Low Register (pwmg2dtl), IO address = 0x4F .......................................81
7. Instructions.........................................................................................................................82
7.1.
7.2.
7.3.
7.4.
7.5.
7.6.
7.7.
7.8.
7.9.
Data Transfer Instructions.....................................................................................................83
Arithmetic Operation Instructions ..........................................................................................87
Shift Operation Instructions...................................................................................................89
Logic Operation Instructions..................................................................................................90
Bit Operation Instructions......................................................................................................93
Conditional Operation Instructions ........................................................................................94
System control Instructions ...................................................................................................95
Summary of Instructions Execution Cycle .............................................................................96
Summary of affected flags by Instructions.............................................................................97
7.10. BIT definition.........................................................................................................................97
8. Code Options......................................................................................................................98
9. Special Notes......................................................................................................................99
9.1.
9.2.
Warning ................................................................................................................................99
Using IC................................................................................................................................99
9.2.1. IO pin usage and setting............................................................................................99
9.2.2. Interrupt...................................................................................................................100
9.2.3. System clock switching............................................................................................101
9.2.4. Watchdog................................................................................................................101
9.2.5. TIMER time out .......................................................................................................101
9.2.6. IHRC .......................................................................................................................101
9.2.7. LVR.........................................................................................................................101
9.2.8. Programming Writing...............................................................................................102
Using ICE............................................................................................................................104
9.3.
©Copyright 2020, PADAUK Technology Co. Ltd
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PFS123
8bit MTP MCU with 12-bit R-Type ADC
Revision History:
Revision
Date
Description
0.00
2020/08/26 Preliminary version
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PFS123
8bit MTP MCU with 12-bit R-Type ADC
1. Features
1.1. Special Features
General purpose series
Not supposed to use in AC RC step-down powered or high EFT requirement applications.
PADAUK assumes no liability if such kind of applications can not pass the safety regulation tests.
Operating temperature range: -20°C ~ 70°C
1.2. System Features
3KW MTP program memory (programming cycle at least 1,000 times)
256 Bytes data SRAM
One hardware 16-bit timer
Two hardware 8-bit timers with PWM generation
One set triple 11bit SuLED (Super LED) PWM generators and timers
One hardware comparator
Band-gap circuit to provide 1.20V reference voltage
Up to 14-channel 12-bit resolution R-type* ADC with one channel comes from internal band-gap voltage
*Note: R-Type ADC means Resistive type ADC. Its linearity (INL&DNL), heat stability and power noise
rejection would not be as good as the C-Type ADC which is built in the PMS13x series.
ADC reference high voltage: external input, internal VDD
Max. 18 IO pins with optional pull-high resistor, four of them with additional pull-low resistor
Every IO pin can be configured to enable wake-up function
Built-in VDD/2 LCD bias voltage generator to provide maximum 5x12 dots LCD display
Clock sources: IHRC, ILRC and EOSC (XTAL)
For every wake-up enabled IO, two optional wake-up speed are supported: normal and fast
16 selectable levels of LVR reset from 1.8V to 4.5V
Two selectable external interrupt pins by code option
1.3. CPU Features
8-bit high performance RISC CPU
88 powerful instructions
Most instructions are 1T execution cycle
Programmable stack pointer to provide adjustable stack level
Direct and indirect addressing modes for data access. Data memories are available for use as an index
pointer of Indirect addressing mode
IO space and memory space are independent
1.4. Package Information
PFS123-U06: SOT23-6 (60mil)
PFS123-S08: SOP8 (150mil)
PFS123-M10: MSOP10 (118mil)
PFS123-S14: SOP14 (150mil)
PFS123-S16: SOP16 (150mil)
PFS123-D16: DIP16 (300mil)
PFS123-S20: SOP20 (300mil)
PFS123-H20: HTSOP20 (150mil)
PFS123-1J16A: QFN3*3-16P (0.5pitch)
©Copyright 2020, PADAUK Technology Co. Ltd
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PFS123
8bit MTP MCU with 12-bit R-Type ADC
2. General Description and Block Diagram
The PFS123 is an MTP-based CMOS 8-bit microcontroller with 8-bit ADC. It employs RISC architecture and all
the instructions are executed in one cycle except that some instructions are two cycles that handle indirect
memory access.
Up to 3KW MTP program memory and 256 bytes data SRAM are inside. One up to 14 channels 12-bit R-Type
ADC is built inside the chip with multiple reference voltage sources selectable. PFS123 also provides four
hardware timers: one is 16-bit timer, two are 8-bit timers with PWM generation, and one new triple 11-bit timer
with SuLED PWM generation (PWMG0, PWMG1 & PWMG2) are included. PFS123 also supports one hardware
comparator and VDD/2 LCD bias voltage generator for LCD display application.
©Copyright 2020, PADAUK Technology Co. Ltd
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PFS123
8bit MTP MCU with 12-bit R-Type ADC
3. Pin Assignment and Description
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8bit MTP MCU with 12-bit R-Type ADC
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PFS123
8bit MTP MCU with 12-bit R-Type ADC
Pin Type &
Buffer Type
Pin Name
Description
The functions of this pin can be:
(1) Bit 7 of port A. It can be configured as digital input or two-state output, with
pull-high resistor.
IO
PA7 /
X1
ST /
(2) X1 is Crystal XIN(X1) when crystal oscillator is used.
If this pin is used for crystal oscillator, bit 7 of padier register must be programmed “0”
to avoid leakage current. This pin can be used to wake-up system during sleep mode;
however, wake-up function is also disabled if bit 7 of padier register is “0”.
CMOS
Pin Name Pin Type &
Description
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8bit MTP MCU with 12-bit R-Type ADC
Buffer Type
The functions of this pin can be:
(1) Bit 6 of port A. It can be configured as digital input or two-state output, with
pull-high resistor.
IO
PA6 /
X2
ST /
(2) X2 is Crystal XOUT(X2) when crystal oscillator is used.
If this pin is used for crystal oscillator, bit 6 of padier register must be programmed “0”
to avoid leakage current. This pin can be used to wake-up system during sleep mode;
however, wake-up function is also disabled if bit 6 of padier register is “0”.
CMOS
The functions of this pin can be:
(1) Bit 5 of port A. It can be configured as digital input or open-drain output , with
pull-high resistor.
PA5 /
IO (OD)
ST /
(2) Hardware reset.
PRSTB /
PG2PWM
(3) Output of 11-bit PWM generator PWMG2
CMOS
This pin can be used to wake-up system during sleep mode; however, wake-up
function is also disabled if bit 5 of padier register is “0”. Please put 33Ω resistor in
series to have high noise immunity when this pin is in input mode.
The functions of this pin can be:
(1) Bit 4 of port A. It can be configured as digital input or two-state output, with
pull-high resistor.
(2) Channel 9 of ADC analog input.
PA4 /
AD9 /
(3) Plus input source of comparator
IO
(4) Minus input source 1 of comparator
CIN+ /
ST /
(5) External interrupt line 1. It can be used as an external interrupt line 1. Both rising
edge and falling edge are accepted to request interrupt service and configurable
by register setting.
CIN1- /
INT1 /
CMOS /
Analog
PG1PWM
(6) Output of 11-bit PWM generator PWMG1
When this pin is configured as analog input, please use bit 4 of register padier to
disable the digital input to prevent current leakage. The bit 4 of padier register can be
set to “0” to disable digital input; wake-up from power-down by toggling this pin is also
disabled.
The functions of this pin can be:
(1) Bit 3 of port A. It can be configured as digital input or two-state output, with
pull-high resistor.
PA3 /
AD8 /
(2) Channel 8 of ADC analog input
IO
(3) Minus input source 0 of comparator
ST /
CIN0- /
(4) PWM output from Timer2
CMOS /
Analog
TM2PWM /
PG2PWM
(5) Output of 11-bit PWM generator PWMG2
When this pin is configured as analog input, please use bit 3 of register padier to
disable the digital input to prevent current leakage. The bit 3 of padier register can be
set to “0” to disable digital input; wake-up from power-down by toggling this pin is also
disabled.
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8bit MTP MCU with 12-bit R-Type ADC
Pin Type &
Buffer Type
Pin Name
Description
The functions of this pin can be:
(1) Bit 0 of port A. It can be configured as digital input or two-state output, with
pull-high resistor.
(2) Channel 10 of ADC analog input
(3) Output of comparator
PA0 /
AD10 /
CO /
IO
(4) External interrupt line 0. It can be used as an external interrupt line 0. Both rising
edge and falling edge are accepted to request interrupt service and configurable
by register setting.
ST /
CMOS /
Analog
INT0 /
PG0PWM
(5) Output of 11-bit PWM generator PWMG0
When this pin is configured as analog input, please use bit 0 of register padier to
disable the digital input to prevent current leakage. The bit 0 of padier register can be
set to “0” to disable digital input; wake-up from power-down by toggling this pin is also
disabled.
The functions of this pin can be:
(1) Bit 7 of port B. It can be configured as digital input or two-state output, with
pull-high resistor independently by software
(2) Channel 7 of ADC analog input
PB7 /
AD7 /
IO
(3) Minus input source 5 of comparator
ST /
CIN5- /
(4) PWM output from Timer3
CMOS /
Analog
TM3PWM /
PG1PWM
(5) Output of 11-bit PWM generator PWMG1
When this pin is configured as analog input, please use bit 7 of register pbdier to
disable the digital input to prevent current leakage. The bit 7 of pbdier register can be
set to “0” to disable digital input; wake-up from power-down by toggling this pin is also
disabled.
The functions of this pin can be:
(1) Bit 6 of port B. It can be configured as digital input or two-state output, with
pull-high resistor independently by software.
(2) Channel 6 of ADC analog input
PB6 /
AD6 /
(3) COM4 to provide (1/2 VDD) for LCD display
(4) Minus input source 4 of comparator
IO
COM4 /
ST /
CIN4- /
(5) PWM output from Timer3
CMOS /
Analog
TM3PWM /
PG1PWM /
PG0PWM
(6) Output of 11-bit PWM generator PWMG1
(7) Output of 11-bit PWM generator PWMG0
When this pin is configured as analog input, please use bit 6 of register pbdier to
disable the digital input to prevent current leakage. The bit 6 of pbdier register can be
set to “0” to disable digital input; wake-up from power-down by toggling this pin is also
disabled.
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8bit MTP MCU with 12-bit R-Type ADC
Pin Type &
Buffer Type
Pin Name
Description
The functions of this pin can be:
(1) Bit 5 of port B. It can be configured as digital input or two-state output, with
pull-high resistor independently by software.
(2) Channel 5 of ADC analog input
PB5 /
AD5 /
(3) COM3 to provide (1/2 VDD) for LCD display
(4) External interrupt line 0. It can be used as an external interrupt line 0. Both rising
edge and falling edge are accepted to request interrupt service and configurable
by register setting.
IO
COM3 /
ST /
INT0 /
CMOS /
Analog
(5) PWM output from Timer3
TM3PWM /
PG0PWM /
PG2PWM
(6) Output of 11-bit PWM generator PWMG0
(7) Output of 11-bit PWM generator PWMG2
When this pin is configured as analog input, please use bit 5 of register pbdier to
disable the digital input to prevent current leakage. The bit 5 of pbdier register can
be set to “0” to disable digital input; wake-up from power-down by toggling this pin is
also disabled.
The functions of this pin can be:
(1) Bit 4 of port B. It can be configured as digital input or two-state output, with
pull-high resistor independently by software.
PB4 /
AD4 /
IO
(2) Channel 4 of ADC analog input
ST /
(3) PWM output from Timer2
(4) Output of 11-bit PWM generator PWMG0
TM2PWM /
PG0PWM
CMOS /
Analog
When this pin is configured as analog input, please use bit 4 of register pbdier to
disable the digital input to prevent current leakage. The bit 4 of pbdier register can
be set to “0” to disable digital input; wake-up from power-down by toggling this pin is
also disabled.
The functions of this pin can be:
(1) Bit 3 of port B. It can be configured as digital input or two-state output, with
pull-high / pull-low resistor independently by software.
(2) Channel 3 of ADC analog input
IO
PB3 /
AD3 /
ST /
(3) Output of 11-bit PWM generator PWMG2
CMOS /
Analog
When this pin is configured as analog input, please use bit 3 of register pbdier to
disable the digital input to prevent current leakage. The bit 3 of pbdier register can
be set to “0” to disable digital input; wake-up from power-down by toggling this pin is
also disabled.
PG2PWM
The functions of this pin can be:
(1) Bit 2 of port B. It can be configured as digital input or two-state output, with
pull-high / pull-low resistor independently by software.
(2) Channel 2 of ADC analog input
PB2 /
AD2 /
IO
ST /
(3) COM2 to provide (1/2 VDD) for LCD display
COM2 /
(4) PWM output from Timer2
CMOS /
Analog
TM2PWM /
PG2PWM
(5) Output of 11-bit PWM generator PWMG2
When this pin is configured as analog input, please use pbdier.2 to disable the digital
input to prevent current leakage. The pbdier.2 can be set to “0” to disable digital
input; wake-up from power-down by toggling this pin is also disabled.
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8bit MTP MCU with 12-bit R-Type ADC
Pin Type &
Buffer Type
Pin Name
Description
The functions of this pin can be:
(1) Bit 1 of port B. It can be configured as digital input or two-state output, with
pull-high resistor independently by software.
PB1 /
AD1 /
COM1 /
Vref
IO
(2) Channel 1 of ADC analog input
ST /
(3) COM1 to provide (1/2 VDD) for LCD display
CMOS /
Analog
(4) External reference high voltage for ADC
When this pin is configured as analog input, please use bit 1 of register pbdier to
disable the digital input to prevent current leakage. The bit 1 of pbdier register can
be set to “0” to disable digital input; wake-up from power-down by toggling this pin is
also disabled.
The functions of this pin can be:
(1) Bit 0 of port B. It can be configured as digital input or two-state output, with
pull-high resistor independently by software.
(2) Channel 0 of ADC analog input
PB0 /
AD0 /
IO
(3) COM0 to provide (1/2 VDD) for LCD display
ST /
(4) External interrupt line 1. It can be used as an external interrupt line 1. Both rising
edge and falling edge are accepted to request interrupt service and configurable
by register setting.
COM0 /
INT1
CMOS /
Analog
When this pin is configured as analog input, please use bit 0 of register pbdier to
disable the digital input to prevent current leakage. The bit 0 of pbdier register can be
set to “0” to disable digital input; wake-up from power-down by toggling this pin is also
disabled.
The functions of this pin can be:
(1) Bit 3 of port B. It can be configured as digital input or two-state output, with
pull-high resistor independently by software.
IO
PC3 /
ST /
PG1PWM
(2) Output of 11-bit PWM generator PWMG1
CMOS
The bit 3 of pcdier register can be set to “0” to disable digital input; wake-up from
power-down by toggling this pin is also disabled.
The functions of this pin can be:
(1) Bit 2 of port C. It can be configured as digital input or two-state output, with
pull-high resistor independently by software.
IO
PC2 /
AD12 /
(2) Channel 12 of ADC analog input
ST /
(3) Output of 11-bit PWM generator PWMG0
CMOS /
Analog
PG0PWM
When this pin is configured as analog input, please use bit 2 of register pcdier to
disable the digital input to prevent current leakage. The bit 2 of pcdier register can be
set to “0” to disable digital input; wake-up from power-down by toggling this pin is
also disabled.
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PFS123
8bit MTP MCU with 12-bit R-Type ADC
Pin Type &
Buffer Type
Pin Name
Description
The functions of this pin can be:
(1) Bit 1 of port C. It can be configured as digital input or two-state output, with
pull-high / pull-low resistor independently by software.
(2) Channel 11 of ADC analog input
IO
PC1 /
AD11
ST /
CMOS /
Analog
When this pin is configured as analog input, please use bit 1 of register pcdier to
disable the digital input to prevent current leakage. The bit 1 of pcdier register can be
set to “0” to disable digital input; wake-up from power-down by toggling this pin is also
disabled.
The functions of this pin can be:
(1) Bit 0 of port C. It can be configured as digital input or two-state output, with
pull-high / pull-low resistor independently by software.
(2) Output of 11-bit PWM generator PWMG2
IO
PC0 /
ST /
PG2PWM
CMOS
The bit 0 of pcdier register can be set to “0” to disable digital input; wake-up from
power-down by toggling this pin is also disabled.
VDD: Digital positive power
VDD/
VDD/
AVDD: Analog positive power
AVDD
AVDD
VDD is the IC power supply while AVDD is the ADC power supply. AVDD and VDD
are double bonding internally and they have the same external pin.
GND: Digital negative power
GND /
AGND
GND /
AGND
AGND: Analog negative power
GND is the IC ground pin while AGND is the ADC ground pin. AGND and GND are
double bonding internally and they have the same external pin.
Notes: IO: Input/Output; ST: Schmitt Trigger input; OD: Open Drain; Analog: Analog input pin
CMOS: CMOS voltage level
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8bit MTP MCU with 12-bit R-Type ADC
4. Device Characteristics
4.1. AC/DC Device Characteristics
All data are acquired under the conditions of Ta = -20oC ~ 70 oC, VDD=5.0V, fSYS =2MHz unless noted.
Symbol
Description
Operating Voltage
Min
2.2*
-5
Typ
Max
5.5
5
Unit
V
Conditions (Ta=25oC)
VDD
5.0
* Subject to LVR tolerance
LVR% Low Voltage Reset Tolerance
System clock (CLK)* =
IHRC/2
%
0
0
0
8M
4M
2M
V
V
V
DD ≧ 3.5V
DD ≧ 2.5V
DD ≧ 2.2V
fSYS
IHRC/4
Hz
IHRC/8
ILRC
93K
VDD = 5.0V
Pcycle
VPOR
Program cycle
Power On Reset Voltage
1000
cycles
2.0*
0.75
87
* Subject to LVR tolerance
mA fSYS=IHRC/16=1MIPS@5.0V
Operating Current
IOP
IPD
uA
uA
uA
fSYS=ILRC=96KHz@5.0V
fSYS= 0Hz,VDD=5.0V
fSYS= 0Hz,VDD=3.3V
Power Down Current
0.2
(by stopsys command)
Power Save Current
0.1
VDD =5.0V; fSYS= ILRC
IPS
VIL
VIH
2.5
uA
V
(by stopexe command)
Input low voltage for IO lines
Only ILRC module is enabled.
0
0.1 VDD
VDD
0.8 VDD
0.7 VDD
PA5
Input high voltage for IO lines
V
VDD
Other IO
IO lines Sink current
PB4, PB5 (Normal)
PB4, PB5 (Strong)
PC0, PC2, PC3
Other IOs
10
IOL
40
mA VDD=5.0V, VOL=0.5V
30
10
IO lines Drive current
PB4, PB5 (Normal)
PB4, PB5 (Strong)
PA5
5
IOH
20
mA VDD=5.0V, VOH=4.5V
0
Other IOs
5
VIN
Input voltage
-0.3
VDD+0.3
1
V
IINJ (PIN) Injected current on pin
mA VDD +0.3≧VIN≧ -0.3
VDD =5.0V, PB2/PB3/PC0/PC1
VDD =5.0V, Other IO
76
100
52
V
V
V
DD =3.3V, PB2/PB3/PC1/PC1
RPH
Pull-high Resistance
Pull-low Resistance
KΩ
200
30
DD =3.3V, Other IO
DD =2.2V, PB2/PB3/PC1/PC1
450
65
VDD =2.2V, Other IO
VDD =5.0V, PB2/PB3/PC0/PC1
RPL
45
KΩ
VDD =3.3V, PB2/PB3/PC0/PC1
28
VDD =2.2V, PB2/PB3/PC0/PC1
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PFS123
8bit MTP MCU with 12-bit R-Type ADC
Symbol
Description
Min
Typ
1.20*
16*
Max
Unit
Conditions (Ta=25oC)
VDD =2.2V ~ 5.5V
VBG
Band-gap Reference Voltage
1.145*
15.76*
15.20*
1.255*
16.24*
16.80*
V
-20oC <Ta<70oC*
MHz 25oC, VDD =2.2V~5.5V
Frequency of IHRC after
fIHRC
VDD =2.2V~5.5V,
0oC <Ta<70oC*
calibration *
16*
tINT
VADC
VAD
Interrupt pulse width
ADC working voltage
AD Input Voltage
30
2.2
0
ns
V
VDD = 5.0V
VDD
VDD
V
12
10
0.9
0.8
2
0oC <Ta<50oC*
-20oC <Ta<70oC*
@5V
ADrs
ADC resolution
bit
ADcs
ADclk
ADC current consumption
mA
us
@3V
ADC clock period
2.2V ~ 5.5V
ADC conversion time
tADCONV (tADCLK is the period of the
selected AD conversion clock)
16
tADCLK 12-bit resolution
AD DNL ADC Differential Non-Linearity
±4*
±8*
5*
LSB
LSB
mV
V
12-bit resolution LSB
12-bit resolution LSB
@ VDD =3V
AD INL ADC Integral Non-Linearity
ADos
VDR
ADC offset
RAM data retention voltage*
1.5
in stop mode
8k
misc[1:0]=00 (default)
misc[1:0]=01
16k
tWDT
Watchdog timeout period
TILRC
64k
256k
45
misc[1:0]=10
misc[1:0]=11
Wake-up time period (fast)
Wake-up time period (slow)
Where TILRC is the time
period of ILRC
tWUP
TILRC
3000
System boot-up period from
power-on for slow boot-up
System boot-up period from
power-on for Fast boot-up
External reset pulse width
50
ms
us
VDD =5V
tSBP
750
VDD =5V
tRST
120
-
us
@ VDD =5V
CPos
CPcm
Comparator offset*
Comparator input common
mode*
±10
±20
VDD -1.5
500
mV
0
V
CPspt
CPmc
Comparator response time*
Stable time to change
comparator mode
Comparator current
consumption
100
2.5
ns
us
Both Rising and Falling
7.5
CPcs
20
uA
VDD = 3.3V
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8bit MTP MCU with 12-bit R-Type ADC
*These parameters are for design reference, not tested for each chip.
4.2. Absolute Maximum Ratings
Supply Voltage ……………………………......
2.2V ~ 5.5V
*If VDD is over the maximum rating, it may lead to a permanent damage of IC.
Input Voltage …………………………………..
-0.3V ~ VDD + 0.3V
Operating Temperature .................................. -20oC ~ 70oC
Junction Temperature ………………………… 150°C
Storage Temperature ………………………… -50°C ~ 125°C
4.3. Typical ILRC frequency vs. VDD
ILRC Frequency vs. VDD
100
95
90
Avg.
85
80
2 2.4 2.8 3.2 3.6 4 4.4 4.8 5.2 5.6 6
VDD (Volt)
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8bit MTP MCU with 12-bit R-Type ADC
4.4. Typical IHRC frequency deviation vs. VDD (calibrated to 16MHz)
IHRC Frequency Deviation vs. VDD
0.4
0.2
0.0
-0.2
-0.4
-0.6
-0.8
-1.0
Avg.
2.0 2.4 2.8 3.2 3.6 4.0 4.4 4.8 5.2 5.6 6.0
VDD (Volt)
4.5. Typical ILRC Frequency vs. Temperature
ILRC Drift
110
105
100
95
VDD=5.0V
VDD=4.0V
VDD=3.3V
VDD=2.5V
90
85
80
-40 -30 -20 -10 0 10 25 35 45 55 65 75 85
Temperature (degree C)
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8bit MTP MCU with 12-bit R-Type ADC
4.6. Typical IHRC Frequency vs. Temperature (calibrated to 16MHz)
IHRC Drift
2
1.5
1
0.5
0
VDD=5.0V
VDD=4.0V
VDD=3.3V
VDD=2.5V
VDD=2.0V
-0.5
-1
-1.5
-2
-2.5
-40 -30 -20 -10 0 10 25 35 45 55 65 75 85
Temperature (degree C)
4.7. Typical operating current vs. VDD @ system clock = ILRC/n
Conditions:
ON: ILRC, Band-gap, LVR; OFF: IHRC, EOSC, T16, TM2, TM3, ADC modules;
IO: PA0:0.5Hz output toggle and no loading, others: input and no floating
ILRC/n vs. VDD
100
90
80
70
60
50
40
30
ILRC/1
ILRC/4
ILRC/16
2
2.5
3
3.5
4
4.5
5
5.5
VDD (V)
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8bit MTP MCU with 12-bit R-Type ADC
4.8. Typical operating current vs. VDD @ system clock = IHRC/n
Conditions:
ON: IHRC, Band-gap, LVR; OFF: ILRC, EOSC, T16, TM2, TM3, ADC modules;
IO: PA0:0.5Hz output toggle and no loading, others: input and no floating
IHRC/n vs. VDD
1.6
IHRC/2
1.4
1.2
1
IHRC/4
IHRC/8
IHRC/16
IHRC/32
IHRC/64
0.8
0.6
0.4
0.2
0
2
2.5
3
3.5
4
4.5
5
5.5
VDD (V)
4.9. Typical operating current vs. VDD @ system clock = 4MHz EOSC / n
Conditions:
ON: EOSC[6,5] = [1,1], Band-gap, LVR; OFF: IHRC, ILRC, T16, TM2, TM3, ADC modules;
IO: PA0:0.5Hz output toggle and no loading, others: input and no floating
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8bit MTP MCU with 12-bit R-Type ADC
4.10.Typical operating current vs. VDD @ system clock = 32KHz EOSC / n
Conditions:
ON: EOSC[6,5] = [0,1], Band-gap, LVR; OFF: IHRC, ILRC, T16, TM2, TM3, ADC modules;
IO: PA0:0.5Hz output toggle and no loading, others: input and no floating
4.11.Typical operating current vs. VDD @ system clock = 1MHz EOSC / n
Conditions:
ON: EOSC[6,5] = [1,0], Band-gap, LVR; OFF: IHRC, ILRC, T16, TM2, TM3, ADC modules;
IO: PA0:0.5Hz output toggle and no loading, others: input and no floating
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8bit MTP MCU with 12-bit R-Type ADC
4.12.Typical IO driving current (IOH) and sink current (IOL)
IoH vs. VDD (Drive = Normal)
25
20
15
10
5
PB4/PB5
Others
0
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
VDD (V)
IoH vs. VDD (Drive = Low)
IoH
10
8
6
4
2
0
2.0
2.5
3.0
3.5
VDD (V)
4.0
4.5
5.0
5.5
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PFS123
8bit MTP MCU with 12-bit R-Type ADC
IoL vs. VDD (Drive = Normal)
50
45
40
35
30
25
20
15
10
5
PB4/PB5
PC0/PC2/PC3
PA5
Others
0
2.0
2.5
3.0
3.5
VDD (V)
4.0
4.5
5.0
5.5
IoL vs. VDD (Drive = Low)
40
35
30
25
20
15
10
5
PC0/PC2/PC3
Others
PA5
0
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
VDD (V)
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8bit MTP MCU with 12-bit R-Type ADC
4.13. Typical IO input high/low threshold voltage (VIH/VIL)
Vih, Vil vs. VDD
Vih PA5
Vil PA5
Vil Others
Vih Others
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0.0
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
VDD (V)
4.14. Typical resistance of IO pull high/low device
Pull High Resistor
700
600
500
400
300
200
100
0
Others
PA5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
VDD (V)
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PFS123
8bit MTP MCU with 12-bit R-Type ADC
Pull High Resistor
68
67
66
65
64
63
PB2
PB3
PC1
PC0
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
VDD (V)
Pull Low Resistance
82
PB2
81
80
79
78
77
76
75
74
PB3
PC0
PC1
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
VDD (V)
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8bit MTP MCU with 12-bit R-Type ADC
4.15. Typical power down current (IPD) and power save current (IPS)
stopsys power down current vs. VDD
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0.0
stopsys
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
VDD (V)
stopexe power save current vs. VDD
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0.0
stopexe
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
VDD (V)
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8bit MTP MCU with 12-bit R-Type ADC
5. Functional Description
5.1. Program Memory - MTP
The MTP (Multiple Time Programmable) program memory is used to store the program instructions to be
executed. The MTP program memory may contains the data, tables and interrupt entry. After reset, the
program will start from the initial address 0x000 which is GOTO FPPA0 instruction usually. The interrupt entry
is 0x10 if used, the last 32 addresses are reserved for system using, like checksum, serial number, etc. The
MTP program memory for PFS123 is 3KW that is partitioned as Table 1. The MTP memory from address
0XBC0 to 0xBFF is for system using, address space from 0x001 to 0x00F and from 0x011 to 0XBBF are user
program spaces.
Address
0x000
0x001
•
Function
GOTO FPPA0 instruction
User program
•
0x00F
0x010
0x011
•
User program
Interrupt entry address
User program
•
0xBBF
0XBC0
•
User program
System Using
•
0xBFF
System Using
Table 1: Program Memory Organization
5.2. Boot Procedure
POR (Power-On-Reset) is used to reset PFS123 when power up. The boot up time can be optional fast or
normal. Customer must ensure the stability of supply voltage after power up no matter which option is chosen,
the power up sequence is shown in the Fig. 1 and tSBP is the boot up time.
Fig.1: Power-Up Sequence
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8bit MTP MCU with 12-bit R-Type ADC
1.2.1. Timing charts for reset conditions
LVR level
SBP
VDD
LVR
t
Program
Execution
Boot up from LVR detection
VDD
t
SBP
WD
Time Out
Program
Execution
Boot up from Watch Dog Time Out
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8bit MTP MCU with 12-bit R-Type ADC
5.3. Data Memory - SRAM
The access of data memory can be byte or bit operation. Besides data storage, the SRAM data memory is also
served as data pointer of indirect access method and the stack memory.
The stack memory is defined in the data memory. The stack pointer is defined in the stack pointer register; the
depth of stack memory of each processing unit is defined by the user. The arrangement of stack memory fully
flexible and can be dynamically adjusted by the user.
For indirect memory access mechanism, the data memory is used as the data pointer to address the data byte.
All the data memory could be the data pointer; it’s quite flexible and useful to do the indirect memory access.
Since the data width is 8-bit, all the 256 bytes data memory of PFS123 can be accessed by indirect access
mechanism.
5.4. Oscillator and clock
There are three oscillator circuits provided by PFS123: external crystal oscillator (EOSC), internal high RC
oscillator (IHRC) and internal low RC oscillator (ILRC), and these three oscillators are enabled or disabled by
registers eoscr.7, clkmd.4 and clkmd.2 independently. User can choose one of these three oscillators as
system clock source and use clkmd register to target the desired frequency as system clock to meet different
applications.
Oscillator Module
EOSC
Enable/Disable
eoscr.7
IHRC
clkmd.4
ILRC
clkmd.2
Table 2: Three oscillation circuits
5.4.1. Internal High RC oscillator and Internal Low RC oscillator
After boot-up, the IHRC and ILRC oscillators are enabled. The frequency of IHRC can be calibrated to
eliminate process variation by ihrcr register; normally it is calibrated to 16MHz. Please refer to the
measurement chart for IHRC frequency verse VDD and IHRC frequency verse temperature. The frequency of
ILRC will vary by process, supply voltage and temperature, please refer to DC specification and do not use for
accurate timing application.
5.4.2. Chip calibration
The IHRC frequency and band-gap reference voltage may be different chip by chip due to manufacturing
variation, PFS123 provide the IHRC frequency calibration to eliminate this variation, and this function can be
selected when compiling user’s program and the command will be inserted into user’s program automatically.
The calibration command is shown as below:
.ADJUST_IC SYSCLK=IHRC/(p1), IHRC=(p2)MHz, VDD=(p3)V;
Where, p1=2, 4, 8, 16, 32; In order to provide different system clock.
p2=14 ~ 18; In order to calibrate the chip to different frequency, 16MHz is the usually one.
p3=2.5 ~ 5.5; In order to calibrate the chip under different supply voltage.
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8bit MTP MCU with 12-bit R-Type ADC
5.4.3. IHRC Frequency Calibration and System Clock
During compiling the user program, the options for IHRC calibration and system clock are shown as Table 3:
SYSCLK
○ Set IHRC / 2
○ Set IHRC / 4
○ Set IHRC / 8
○ Set IHRC / 16
○ Set IHRC / 32
○ Set ILRC
CLKMD
IHRCR
Calibrated
Calibrated
Calibrated
Description
= 34h (IHRC / 2)
= 14h (IHRC / 4)
= 3Ch (IHRC / 8)
IHRC calibrated to 16MHz, CLK=8MHz (IHRC/2)
IHRC calibrated to 16MHz, CLK=4MHz (IHRC/4)
IHRC calibrated to 16MHz, CLK=2MHz (IHRC/8)
IHRC calibrated to 16MHz, CLK=1MHz (IHRC/16)
IHRC calibrated to 16MHz, CLK=0.5MHz (IHRC/32)
IHRC calibrated to 16MHz, CLK=ILRC
= 1Ch (IHRC / 16) Calibrated
= 7Ch (IHRC / 32) Calibrated
= E4h (ILRC / 1)
No change
Calibrated
○ Disable
No Change IHRC not calibrated, CLK not changed
Table 3: Options for IHRC Frequency Calibration
Usually, .ADJUST_IC will be the first command after boot up, in order to set the target operating frequency
whenever starting the system. The program code for IHRC frequency calibration is executed only one time that
occurs in writing the codes into MTP memory; after then, it will not be executed again. If the different option for
IHRC calibration is chosen, the system status is also different after boot. The following shows the status of
PFS123 for different option:
(1) .ADJUST_IC
SYSCLK=IHRC/2, IHRC=16MHz, VDD=5V
After boot up, CLKMD = 0x34:
IHRC frequency is calibrated to 16MHz@VDD=5V and IHRC module is enabled
System CLK = IHRC/2 = 8MHz
Watchdog timer is disabled, ILRC is enabled, PA5 is in input mode
(2) .ADJUST_IC
SYSCLK=IHRC/4, IHRC=16MHz, VDD=3.3V
After boot up, CLKMD = 0x14:
IHRC frequency is calibrated to 16MHz@VDD=3.3V and IHRC module is enabled
System CLK = IHRC/4 = 4MHz
Watchdog timer is disabled, ILRC is enabled, PA5 is in input mode
(3) .ADJUST_IC
SYSCLK=IHRC/8, IHRC=16MHz, VDD=2.5V
After boot up, CLKMD = 0x3C:
IHRC frequency is calibrated to 16MHz@VDD=2.5V and IHRC module is enabled
System CLK = IHRC/8 = 2MHz
Watchdog timer is disabled, ILRC is enabled, PA5 is in input mode
SYSCLK=IHRC/16, IHRC=16MHz, VDD=2.5V
(4) .ADJUST_IC
After boot up, CLKMD = 0x1C:
IHRC frequency is calibrated to 16MHz@VDD=2.5V and IHRC module is enabled
System CLK = IHRC/16 = 1MHz
Watchdog timer is disabled, ILRC is enabled, PA5 is in input mode
(5) .ADJUST_IC
SYSCLK=IHRC/32, IHRC=16MHz, VDD=5V
After boot up, CLKMD = 0x7C:
IHRC frequency is calibrated to 16MHz@VDD=5V and IHRC module is enabled
System CLK = IHRC/32 = 500KHz
Watchdog timer is disabled, ILRC is enabled, PA5 is in input mode
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8bit MTP MCU with 12-bit R-Type ADC
(6) .ADJUST_IC
SYSCLK=ILRC, IHRC=16MHz, VDD=5V
After boot up, CLKMD = 0XE4:
IHRC frequency is calibrated to 16MHz@VDD=5V and IHRC module is disabled
System CLK = ILRC
Watchdog timer is disabled, ILRC is enabled, PA5 is input mode
(7) .ADJUST_IC
DISABLE
After boot up, CLKMD is not changed (Do nothing):
IHRC is not calibrated and IHRC module is disabled
System CLK = ILRC or IHRC/64
Watchdog timer is enabled, ILRC is enabled, PA5 is in input mode
5.4.4. External Crystal Oscillator
If crystal oscillator is used, a crystal or resonator is required between X1 and X2. Fig.2 shows the hardware
connection under this application; the range of operating frequency of crystal oscillator can be from 32 KHz to
4MHz, depending on the crystal placed on; higher frequency oscillator than 4MHz is NOT supported.
(Select driving current for oscillator)
eoscr[6:5]
(Enable crystal oscillator)
eoscr.7
C1
PA7/X1
System clock = EOSC
PA6/X2
C2
The values of C1 and C2 should depend on
the specification of crystal.
Fig.2: Connection of crystal oscillator
Besides crystal, external capacitor and options of PFS123 should be fine tuned in eoscr (0x0a) register to have
good sinusoidal waveform. The eoscr.7 is used to enable crystal oscillator module, eoscr.6 and eoscr.5 are
used to set the different driving current to meet the requirement of different frequency of crystal oscillator:
eoscr.[6:5]=01 : Low driving capability, for lower frequency, ex: 32KHz crystal oscillator
eoscr.[6:5]=10 : Middle driving capability, for middle frequency, ex: 1MHz crystal oscillator
eoscr.[6:5]=11 : High driving capability, for higher frequency, ex: 4MHz crystal oscillator
Table 4 shows the recommended values of C1 and C2 for different crystal oscillator; the measured start-up
time under its corresponding conditions is also shown. Since the crystal or resonator had its own characteristic,
the capacitors and start-up time may be slightly different for different type of crystal or resonator, please refer to
its specification for proper values of C1 and C2.
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PFS123
8bit MTP MCU with 12-bit R-Type ADC
Measured
Frequency
C1
C2
Conditions
Start-up time
6ms
4MHz
1MHz
32KHz
4.7pF
10pF
22pF
4.7pF
10pF
22pF
(eoscr[6:5]=11, misc.6=0)
(eoscr[6:5]=10, misc.6=0)
(eoscr[6:5]=01, misc.6=0)
11ms
450ms
Table 4: Recommend values of C1 and C2 for crystal and resonator oscillators
When using the crystal oscillator, user must pay attention to the stable time of oscillator after enabling it, the
stable time of oscillator will depend on frequency “crystal type” external capacitor and supply voltage. Before
switching the system to the crystal oscillator, user must make sure the oscillator is stable; the reference
program is shown as below:
void
{
FPPA0 (void)
. ADJUST_IC SYSCLK=IHRC/16, IHRC=16MHz, VDD=5V
$
$
EOSCR
Enable, 4MHz;
// EOSCR = 0b110_00000;
T16M EOSC, /1, BIT13;
// T16 receive 2^14=16384 clocks of crystal EOSC,
// Intrq.T16 =>1, crystal EOSC Is stable
WORD
count =
0;
stt16 count;
Intrq.T16
=
0;
do
{
nop; }while(!Intrq.T16);
// count from 0x0000 to 0x2000, then set INTRQ.T16
// switch system clock to EOSC;
clkmd=
0xB4;
Clkmd.4 = 0;
...
// disable IHRC
Please notice that the crystal oscillator should be fully turned off before entering the power-down mode, in
order to avoid unexpected wakeup event.
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PFS123
8bit MTP MCU with 12-bit R-Type ADC
5.4.5. System Clock and LVR level
The clock source of system clock comes from EOSC, IHRC and ILRC, the hardware diagram of system clock
in the PFS123 is shown as Fig.3.
clkmd[7:5]
÷2, ÷4, ÷8,
IHRC
÷16, ÷32, ÷64
System
clock
M
÷1, ÷4, ÷16
ILRC
CLK
U
X
÷1, ÷2, ÷4, ÷8
EOSC
Fig.3: Options of System Clock
User can choose different operating system clock depends on its requirement; the selected operating system
clock should be combined with supply voltage and LVR level to make system stable. The LVR level will be
selected during compilation, and the lowest LVR levels can be chosen for different operating frequencies.
Please refer to Section 4.1.
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PFS123
8bit MTP MCU with 12-bit R-Type ADC
5.4.6. System Clock Switching
After IHRC calibration, user may want to switch system clock to a new frequency or may switch system clock at
any time to optimize the system performance and power consumption. Basically, the system clock of PFS123
can be switched among IHRC, ILRC and EOSC by setting the clkmd register at any time; system clock will be
the new one after writing to clkmd register immediately. Please notice that the original clock module can NOT
be turned off at the same time as writing command to clkmd register. The examples are shown as below and
more information about clock switching, please refer to the “Help” -> “Application Note” -> “IC Introduction” ->
“Register Introduction” -> CLKMD”.
Case 1: Switching system clock from ILRC to IHRC/2
…
//
//
//
//
system clock is ILRC
CLKMD.4
CLKMD
// CLKMD.2
…
=
=
=
1;
turn on IHRC first to improve anti-interference ability
switch to IHRC/2, ILRC CAN NOT be disabled here
if need, ILRC CAN be disabled at this time
0x34;
0;
Case 2: Switching system clock from ILRC to EOSC
…
//
//
//
system clock is ILRC
CLKMD
CLKMD.2
…
=
=
0xA6;
0;
switch to IHRC,ILRC CAN NOT be disabled here
ILRC CAN be disabled at this time
Case 3: Switching system clock from IHRC/2 to ILRC
…
//
//
//
system clock is IHRC/2
CLKMD
CLKMD.4
…
=
=
0xF4;
0;
switch to ILRC,IHRC CAN NOT be disabled here
IHRC CAN be disabled at this time
Case 4: Switching system clock from IHRC/2 to EOSC
…
//
//
//
system clock is IHRC/2
CLKMD
CLKMD.4
…
=
=
0XB0;
0;
switch to EOSC,IHRC CAN NOT be disabled here
IHRC CAN be disabled at this time
Case 5: Switching system clock from IHRC/2 to IHRC/4
…
//
//
system clock is IHRC/2, ILRC is enabled here
switch to IHRC/4
CLKMD
…
=
0X14;
Case 6: System may hang if it is to switch clock and turn off original oscillator at the same time
…
//
system clock is ILRC
CLKMD
=
0x30;
//
CAN NOT switch clock from ILRC to IHRC/2 and
turn off ILRC oscillator at the same time
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PDK-DS-PFS123-EN_V000-Aug. 26, 2020
PFS123
8bit MTP MCU with 12-bit R-Type ADC
5.5. Comparator
One hardware comparator is built inside the PFS123; Fig.4 shows its hardware diagram. It can compare
signals between two pins or with either internal reference voltage Vinternal R or internal band-gap reference
voltage. The two signals to be compared, one is the plus input and the other one is the minus input. For the
minus input of comparator can be PA3, PA4, Internal band-gap 1.20 volt, PB6, PB7 or Vinternal R selected by bit
[3:1] of gpcc register, and the plus input of comparator can be PA4 or Vinternal R selected by bit 0 of gpcc register.
The output result can be enabled to output to PA0 directly, or sampled by Time2 clock (TM2_CLK) which
comes from Timer2 module. The output can be also inversed the polarity by bit 4 of gpcc register, the
comparator output can be used to request interrupt service.
Fig.4: Hardware diagram of comparator
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PFS123
8bit MTP MCU with 12-bit R-Type ADC
5.5.1 Internal reference voltage (Vinternal R
)
The internal reference voltage Vinternal R is built by series resistance to provide different level of reference
voltage, bit 4 and bit 5 of gpcs register are used to select the maximum and minimum values of Vinternal R
and bit [3:0] of gpcs register are used to select one of the voltage level which is deivided-by-16 from the
defined maximum level to minimum level. Fig.5 to Fig.8 shows four conditions to have different reference
voltage Vinternal R. By setting the gpcs register, the internal reference voltage Vinternal R can be ranged from
(1/32)*VDD to (3/4)*VDD.
Case 1 : gpcs.5=0 & gpcs.4=0
16 stages
VDD
8R
8R
8R
gpcs.4=0
gpcs.4=1
gpcs.5=1
R
R
R
R
gpcs.5=0
MUX
gpcs[3:0]
V internal R = (3/4) VDD ~ (1/4) VDD + (1/32) VDD
@ gpcs[3:0] = 1111 ~ gpcs[3:0] = 0000
1
4
(n+1)
32
V internal R
=
*
VDD +
*
VDD, n = gpcs[3:0] in decimal
Fig.5: Vinternal R hardware connection if gpcs.5=0 and gpcs.4=0
Case 2 : gpcs.5=0 & gpcs.4= 1
16 stages
VDD
8R
8R
8R
gpcs.4=0
gpcs.4=1
gpcs.5=1
R
R
R
R
gpcs.5=0
MUX
gpcs[3:0]
V internal R = (2/3) VDD ~ (1/24) VDD
@ gpcs[3:0] = 1111 ~ gpcs[3:0] = 0000
(n+1)
V internal R
=
*
VDD, n = gpcs[3:0] in decimal
24
Fig.6: Vinternal R hardware connection if gpcs.5=0 and gpcs.4=1
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PFS123
8bit MTP MCU with 12-bit R-Type ADC
Case 3 : gpcs.5=1 & gpcs.4= 0
16 stages
VDD
8R
8R
8R
gpcs.4=0
gpcs.4=1
gpcs.5=1
R
R
R
R
gpcs.5=0
MUX
gpcs[3:0]
V internal R = (3/5) VDD ~ (1/5) VDD + (1/40) VDD
@ gpcs[3:0] = 1111 ~ gpcs[3:0] = 0000
1
5
(n+1)
40
V internal R
=
*
VDD +
*
VDD, n = gpcs[3:0] in decimal
Fig.7: Vinternal R hardware connection if gpcs.5=1 and gpcs.4=0
Case 4 : gpcs.5=1 & gpcs.4=1
16 stages
VDD
8R
8R
8R
gpcs.4=0
gpcs.4=1
gpcs.5=1
R
R
R
R
gpcs.5=0
MUX
gpcs[3:0]
V internal R = (1/2) VDD ~ (1/32) VDD
@ gpcs[3:0] = 1111 ~ gpcs[3:0] = 0000
(n+1)
V internal R
=
*
VDD, n = gpcs[3:0] in decimal
32
Fig.8: Vinternal R hardware connection if gpcs.5=1 and gpcs.4=1
©Copyright 2020, PADAUK Technology Co. Ltd
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8bit MTP MCU with 12-bit R-Type ADC
5.5.2 Using the comparator
Case I:
Choosing PA3 as minus input and Vinternal R with (18/32)*VDD voltage level as plus input. Vinternal R is
configured as the above Figure “gpcs[5:4] = 2b’00” and gpcs [3:0] = 4b’1001 (n=9) to have Vinternal R
(1/4)*VDD + [(9+1)/32]*VDD = [(9+9)/32]*VDD = (18/32)*VDD.
=
gpcs = 0b0_0_00_1001;
gpcc = 0b1_0_0_0_000_0;
padier = 0bxxxx_0_xxx;
// Vinternal R = VDD*(18/32)
// enable comp, - input: PA3, + input: Vinternal R
// disable PA3 digital input to prevent leakage current
or
$ GPCS
$ GPCC
VDD*18/32;
Enable, N_PA3, P_R;
// - input: N_xx,+ input: P_R(Vinternal R)
PADIER = 0bxxxx_0_xxx;
Case 2:
Choosing Vinternal R as minus input with (22/40)*VDD voltage level and PA4 as plus input, the comparator
result will be inversed and then output to PA0. Vinternal R is configured as the above Figure “gpcs[5:4] =
2b’10” and gpcs [3:0] = 4b’1101 (n=13) to have Vinternal R = (1/5)*VDD + [(13+1)/40]*VDD = [(13+9)/40]*VDD
(22/40)*VDD.
=
gpcs = 0b1_0_10_1101;
gpcc = 0b1_0_0_1_011_1;
// output to PA0,Vinternal R = VDD*(22/40)
// Inverse output, - input: Vinternal R, + input: PA4
// disable PA4 digital input to prevent leakage current
padier
= 0bxxx_0_xxxx;
or
$ GPCS
$ GPCC
Output, VDD*22/40;
Enable, Inverse, N_R, P_PA4; // - input: N_R(Vinternal R),+ input: P_xx
PADIER = 0bxxx_0_xxxx;
Note: When selecting output to PA0 output, GPCS will affect the PA3 output function in ICE. Though the
IC is fine, be careful to avoid this error during emulation.
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PFS123
8bit MTP MCU with 12-bit R-Type ADC
5.5.3 Using the comparator and band-gap 1.20V
The internal band-gap module can provide 1.20 volt, it can measure the external supply voltage level. The
band-gap 1.20 volt is selected as minus input of comparator and Vinternal R is selected as plus input, the
supply voltage of Vinternal R is VDD, the VDD voltage level can be detected by adjusting the voltage level of
Vinternal R to compare with band-gap. If N (gpcs[3:0] in decimal) is the number to let Vinternal R closest to
band-gap 1.20 volt, the supply voltage VDD can be calculated by using the following equations:
For using Case 1: VDD = [ 32 / (N+9) ] * 1.20 volt ;
For using Case 2: VDD = [ 24 / (N+1) ] * 1.20 volt ;
For using Case 3: VDD = [ 40 / (N+9) ] * 1.20 volt ;
For using Case 4: VDD = [ 32 / (N+1) ] * 1.20 volt ;
Case 1:
$ GPCS VDD*12/40;
// 4.0V * 12/40 = 1.2V
$ GPCC Enable, BANDGAP, P_R; // - input: BANDGAP, + input: P_R(Vinternal R
)
….
if (GPC_Out)
// or GPCC.6
{
// when VDD﹥4V
}
else
{
}
// when VDD﹤4V
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PDK-DS-PFS123-EN_V000-Aug. 26, 2020
PFS123
8bit MTP MCU with 12-bit R-Type ADC
5.6 VDD/2 LCD Bias Voltage Generator
There are five pins, PB0, PB1, PB2, PB5 and PB6, can be selected as the COM ports for LCD applications. By
setting misc.4=1, these five COM ports are able to output VDD, VDD/2, GND three levels voltage.
A COM port can still output VDD & GND by selecting 1 or 0 for pb.x in output mode (pbc.x=1) like a normal IO
port. Additionally, a COM port can also output VDD/2 by switching it to input mode (pbc.x=0). However, keep in
mind to turn off the pull-high resistor pbph.x and pbdier.x to prevent the output voltage level from disturbing.
Fig.9 shows how to use this function.
VDD
VDD/2
GND
Pin set to output high
Pin set to input
Pin set to output low
Fig. 9: Using VDD/2 LCD bias voltage generator
Note: ICE does NOT support the VDD/2 function of PB0.
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PDK-DS-PFS123-EN_V000-Aug. 26, 2020
PFS123
8bit MTP MCU with 12-bit R-Type ADC
5.7 16-bit Timer (Timer16)
A 16-bit hardware timer (Timer16) is implemented in the PFS123, the clock sources of Timer16 may come from
system clock (CLK), clock of external crystal oscillator (EOSC), internal high RC oscillator (IHRC), internal low
RC oscillator (ILRC), PA4 and PA0, a multiplex is used to select clock output for the clock source. Before
sending clock to the counter16, a pre-scaling logic with divided-by-1, 4, 16, and 64 is used for wide range
counting. The 16-bit counter performs up-counting operation only, the counter initial values can be stored from
memory by stt16 instruction and the counting values can be loaded to memory by ldt16 instruction. A selector is
used to select the interrupt condition of Timer16, whenever overflow occurs, the Timer16 interrupt can be
triggered. The hardware diagram of Timer16 is shown as Fig.10. The interrupt source of Timer16 comes from
one of bit 8 to 15 of 16-bit counter, and the interrupt type can be rising edge trigger or falling edge trigger which
is specified in the bit 5 of integs register (IO address 0x0C).
PA4
Fig.10: Hardware diagram of Timer16
When using the Timer16, the syntax for Timer16 has been defined in the .INC file. There are three parameters
to define the Timer16; 1st parameter is used to define the clock source of Timer16, 2nd parameter is used to
define the pre-scalar and the last one is to define the interrupt source. The detail description is shown as
below:
T16M
IO_RW
0x06
$ 7~5:STOP, SYSCLK, X, PA4_F, IHRC, EOSC, ILRC, PA0_F
$ 4~3:/1, /4, /16, /64
// 1st par.
// 2nd par.
// 3rd par.
$ 2~0:BIT8, BIT9, BIT10, BIT11, BIT12, BIT13, BIT14, BIT15
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8bit MTP MCU with 12-bit R-Type ADC
User can define the parameters of T16M based on system requirement, some examples are shown below and
more examples please refer to “Help Application Note IC Introduction Register Introduction T16M” in
IDE utility.
$ T16M SYSCLK, /64, BIT15;
// choose (SYSCLK/64) as clock source, every 2^16 clock to set INTRQ.2=1
// if using System Clock = IHRC / 2 = 8 MHz
// SYSCLK/64 = 8 MHz/64 = 125KHz, about every 512 mS to generate INTRQ.2=1
$ T16M EOSC, /1, BIT13;
// choose (EOSC/1) as clock source, every 2^14 clocks to generate INTRQ.2=1
// if EOSC=32768 Hz, 32768 Hz/(2^14) = 2Hz, every 0.5S to generate INTRQ.2=1
$ T16M PA0_F, /1, BIT8;
// choose PA0 as clock source, every 2^9 to generate INTRQ.2=1
// receiving every 512 times PA0 to generate INTRQ.2=1
$ T16M STOP;
// stop Timer16 counting
If Timer16 is operated at free running, the frequency of interrupt can be described as below:
FINTRQ_T16M = Fclock source ÷ P ÷ 2n+1
Where, F is the frequency of selected clock source to Timer16;
P is the selection of t16m [4:3]; (1, 4, 16, 64)
N is the nth bit selected to request interrupt service, for example: n=10 if bit 10 is selected.
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PDK-DS-PFS123-EN_V000-Aug. 26, 2020
PFS123
8bit MTP MCU with 12-bit R-Type ADC
5.8 8-bit Timer (Timer2/Timer3) with PWM generation
Two 8-bit hardware timers (Timer2 and Timer3) with PWM generation are implemented in the PFS123. The
following descriptions thereinafter are for Timer2 only. It is because Timer3 have same structure with Timer2.
Please refer to Fig.11 shown the hardware diagram of Timer2, the clock sources of Timer2 may come from
system clock, internal high RC oscillator (IHRC), internal low RC oscillator (ILRC), external crystal oscillator
(EOSC), PA0, PB0, PA4 and comparator. Bit [7:4] of register tm2c are used to select the clock of Timer2. If
IHRC is selected for Timer2 clock source, the clock sent to Timer2 will keep running when using ICE in halt
state. The output of Timer2 can be sent to pin PB2, PA3 or PB4, depending on bit [3:2] of tm2c register. A clock
pre-scaling module is provided with divided-by- 1, 4, 16, and 64 options, controlled by bit [6:5] of tm2s register;
one scaling module with divided-by-1~31 is also provided and controlled by bit [4:0] of tm2s register. In
conjunction of pre-scaling function and scaling function, the frequency of Timer2 clock (TM2_CLK) can be wide
range and flexible.
The Timer2 counter performs 8-bit up-counting operation only; the counter values can be set or read back by
tm2ct register. The 8-bit counter will be clear to zero automatically when its values reach for upper bound
register, the upper bound register is used to define the period of timer or duty of PWM. There are two operating
modes for Timer2: period mode and PWM mode; period mode is used to generate periodical output waveform
or interrupt event; PWM mode is used to generate PWM output waveform with optional 6-bit to 8-bit PWM
resolution, Fig.12 shows the timing diagram of Timer2 for both period mode and PWM mode.
Fig.11: Timer2 hardware diagram
The output of Timer3 can be sent to pin PB5, PB6 or PB7.
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PFS123
8bit MTP MCU with 12-bit R-Type ADC
Time out and
Time out and
Time out and
Interrupt request
Interrupt request
Interrupt request
Counter
0xFF
bound
Counter
0xFF
Counter
0x3F
bound
bound
Time
Time
Time
Time
Time
Event Trigger
Event Trigger
Event Trigger
Output-pin
Output-pin
Output-pin
Time
Mode 0 – Period Mode
Mode 1 – 8-bit PWM Mode
Mode 1 – 6-bit PWM Mode
Fig.12: Timing diagram of Timer2 in period mode and PWM mode (tm2c.1=1)
A Code Option GPC_PWM is for the applications which need the generated PWM waveform to be controlled by
the comparator result. If the Code Option GPC_PWM is selected, the PWM output stops while the comparator
output is 1 and then the PWM output turns on while the comparator output goes back to 0, as shown in Fig. 13.
PWM Output
Comparator
Output
Fig.13:Comparator controls the output of PWM waveform
5.8.1 Using the Timer2 to generate periodical waveform
If periodical mode is selected, the duty cycle of output is always 50%; its frequency can be summarized as
below:
Frequency of Output = Y ÷ [2 × (K+1) × S1 × (S2+1) ]
Where,
Y = tm2c[7:4] : frequency of selected clock source
K = tm2b[7:0] : bound register in decimal
S1 = tm2s[6:5] : pre-scalar (S1= 1, 4, 16, 64)
S2 = tm2s[4:0] : scalar register in decimal (S2= 0 ~ 31)
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PFS123
8bit MTP MCU with 12-bit R-Type ADC
Example 1:
Example 2:
Example 3:
tm2c = 0b0001_1000, Y=8MHz
tm2b = 0b0111_1111, K=127
tm2s = 0b0_00_00000, S1=1, S2=0
frequency of output = 8MHz ÷ [ 2 × (127+1) × 1 × (0+1) ] = 31.25KHz
tm2c = 0b0001_1000, Y=8MHz
tm2b = 0b0111_1111, K=127
tm2s[7:0] = 0b0_11_11111, S1=64 , S2 = 31
frequency = 8MHz ÷ ( 2 × (127+1) × 64 × (31+1) ) =15.25Hz
tm2c = 0b0001_1000, Y=8MHz
tm2b = 0b0000_1111, K=15
tm2s = 0b0_00_00000, S1=1, S2=0
frequency = 8MHz ÷ ( 2 × (15+1) × 1 × (0+1) ) = 250KHz
Example 4:
tm2c = 0b0001_1000, Y=8MHz
tm2b = 0b0000_0001, K=1
tm2s = 0b0_00_00000, S1=1, S2=0
frequency = 8MHz ÷ ( 2 × (1+1) × 1 × (0+1) ) =2MHz
The sample program for using the Timer2 to generate periodical waveform from PA3 is shown as below:
Void FPPA0 (void)
{
. ADJUST_IC SYSCLK=IHRC/2, IHRC=16MHz, VDD=5V
…
tm2ct = 0x00;
tm2b = 0x7f;
tm2s = 0b0_00_00001;
//
//
8-bit PWM, pre-scalar = 1, scalar = 2
system clock, output=PA3, period mode
tm2c = 0b0001_10_0_0;
while(1)
{
nop;
}
}
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5.8.2 Using the Timer2 to generate 8-bit PWM waveform
If 8-bit PWM mode is selected, it should set tm2c[1]=1 and tm2s[7]=0, the frequency and duty cycle of
output waveform can be summarized as below:
Frequency of Output = Y ÷ [256 × S1 × (S2+1) ]
Duty of Output = [( K+1 ) ÷ 256]×100%
Where, Y = tm2c[7:4] : frequency of selected clock source
K = tm2b[7:0] : bound register in decimal
S1= tm2s[6:5] : pre-scalar (S1= 1, 4, 16, 64)
S2 = tm2s[4:0] : scalar register in decimal (S2= 0 ~ 31)
Example 1:
tm2c = 0b0001_1010, Y=8MHz
tm2b = 0b0111_1111, K=127
tm2s = 0b0_00_00000, S1=1, S2=0
frequency of output = 8MHz ÷ ( 256 × 1 × (0+1) ) = 31.25KHz
duty of output = [(127+1) ÷ 256] × 100% = 50%
Example 2:
tm2c = 0b0001_1010, Y=8MHz
tm2b = 0b0111_1111, K=127
tm2s = 0b0_11_11111, S1=64, S2=31
frequency of output = 8MHz ÷ ( 256 × 64 × (31+1) ) = 15.25Hz
duty of output = [(127+1) ÷ 256] × 100% = 50%
Example 3:
tm2c = 0b0001_1010, Y=8MHz
tm2b = 0b1111_1111, K=255
tm2s = 0b0_00_00000, S1=1, S2=0
PWM output keep high
duty of output = [(255+1) ÷ 256] × 100% = 100%
Example 4:
tm2c = 0b0001_1010, Y=8MHz
tm2b = 0b0000_1001, K = 9
tm2s = 0b0_00_00000, S1=1, S2=0
frequency of output = 8MHz ÷ ( 256 × 1 × (0+1) ) = 31.25KHz
duty of output = [(9+1) ÷ 256] × 100% = 3.9%
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The sample program for using the Timer2 to generate PWM waveform from PA3 is shown as below:
void
{
FPPA0 (void)
.ADJUST_IC
SYSCLK=IHRC/2, IHRC=16MHz, VDD=5V
tm2ct = 0x00;
tm2b = 0x7f;
tm2s = 0b0_00_00001;
//
//
8-bit PWM, pre-scalar = 1, scalar = 2
system clock, output=PA3, PWM mode
tm2c = 0b0001_10_1_0;
while(1)
{
nop;
}
}
5.8.3 Using the Timer2 to generate 6-bit PWM waveform
If 6-bit PWM mode is selected, it should set tm2c[1]=1 and tm2s[7]=1, the frequency and duty cycle of
output waveform can be summarized as below:
Frequency of Output = Y ÷ [64 × S1 × (S2+1) ]
Duty of Output = [( K+1 ) ÷ 64] × 100%
Where, tm2c[7:4] = Y : frequency of selected clock source
tm2b[7:0] = K : bound register in decimal
tm2s[6:5] = S1 : pre-scalar (S1= 1, 4, 16, 64)
tm2s[4:0] = S2 : scalar register in decimal (S2= 0 ~ 31)
Users can set Timer2 to be 7-bit PWM mode instead of 6-bit mode by using TMx_Bit code option. At that
time, the calculation factors of the above equations become 128 instead of 64.
Example 1:
tm2c = 0b0001_1010, Y=8MHz
tm2b = 0b0001_1111, K=31
tm2s = 0b1_00_00000, S1=1, S2=0
frequency of output = 8MHz ÷ ( 64 × 1 × (0+1) ) = 125KHz
duty = [(31+1) ÷ 64] × 100% = 50%
Example 2:
tm2c = 0b0001_1010, Y=8MHz
tm2b = 0b0001_1111, K=31
tm2s = 0b1_11_11111, S1=64, S2=31
frequency of output = 8MHz ÷ ( 64 × 64 × (31+1) ) = 61.03 Hz
duty of output = [(31+1) ÷ 64] × 100% = 50%
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Example 3:
tm2c = 0b0001_1010, Y=8MHz
tm2b = 0b0011_1111, K=63
tm2s = 0b1_00_00000, S1=1, S2=0
PWM output keep high
duty of output = [(63+1) ÷ 64] × 100% = 100%
Example 4:
tm2c = 0b0001_1010, Y=8MHz
tm2b = 0b0000_0000, K=0
tm2s = 0b1_00_00000, S1=1, S2=0
frequency = 8MHz ÷ ( 64 × 1 × (0+1) ) = 125KHz
duty = [(0+1) ÷ 64] × 100% =1.5%
5.9 11-bit PWM Generator
One set of triple 11-bit SuLED (Super LED) hardware PWM generator is implemented in the PFS123. It consists
of three PWM generators (PWMG0, PWMG1 & PWMG2). Their individual outputs are listed as below:
PWMG0 – PA0, PB4, PB5, PC2, PB6 (available if PWMG1 doesn’t select PB6)
PWMG1 – PA4, PB6, PB7, PC3
PWMG2 – PA3, PB2, PB3, PA5 (open drain output only), PC0, PB5 (available if PWMG0 doesn’t select PB5)
Note: PDK5S-I-S01/2(B) doesn’t support the function of the set of 11-bit SuLED hardware PWM generators.
5.9.1 PWM Waveform
A PWM output waveform (Fig.14) has a time-base (TPeriod = Time of Period) and a time with output high
level (Duty Cycle). The frequency of the PWM output is the inverse of the period (fPWM = 1/TPeriod).
Fig.14: PWM Output Waveform
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5.9.2 Hardware Diagram
Fig.15 shows the hardware diagram of the whole set of SuLED 11-bit hardware PWM generators. Those
three PWM generators use a common Up-Counter and clock source selector to create the time base, and
so the start points (the rising edge) of the PWM cycle are synchronized. The clock source can be IHRC or
system clock. The PWM signal output pins that can be selected via pwmgxc register selection. The period
of PWM waveform is defined by the common PWM upper bound high and low registers, and the duty cycle
of individual PWM waveform is defined by the individual set in the PWM duty high and low registers.
The additional OR and XOR logic of PWMG0 channel is used to create the complementary switching
waveforms with dead zone control. Selecting code option GPC_PWM can also control the generated
PWM waveform by the comparator result.
Fig.15: Hardware diagram of whole set of triple SuLED 11-bit PWM generators
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0x7FF
Counter_Bound[10:1]
Duty[10:0]
Time
Time
Output
Timing Diagram for 11- bit PWM generation
Output
Fig.16: Output Timing Diagram of 11-bit PWM Generator
5.9.3 Equations for 11-bit PWM Generator
PWM Frequency FPWM = F clock source ÷ [ P × (CB10_1 + 1) ]
PWM Duty(in time) = (1 / FPWM) × ( DB10_1 + DB0 × 0.5 + 0.5) ÷ (CB10_1 + 1)
PWM Duty(in percentage) = ( DB10_1 + DB0 × 0.5 + 0.5) ÷ (CB10_1 + 1) × 100%
Where,
P=PWMGCLK[6:4]; pre-scalar P=1,2,4,8,16,32,64,128
DB10_1 = Duty_Bound[10:1] = {PWMGxDTH[7:0], PWMGxDTL[7:6]}, duty bound
DB0 = Duty_Bound[0] = PWMGxDTL[5]
CB10_1 = Counter_Bound[10:1] = {PWMGCUBH[7:0], PWMGCUBL[7:6]}, counter bound
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5.9.4 PWM Waveforms with Complementary Dead Zones
Based on the specific 11 bit PWM architecture of PFS123, here we employ PWM2 output and PWM0 inverse
output after PWM0 xor PWM1 to generate two PWM waveforms with complementary dead zones.
Example program is as follows:
#define dead_zone
#define PWM_Pulse
10
50
//
//
dead time = 10% * (1/PWM_Frequency) us
set 50% as PWM duty cycle
#define PWM_Pulse_1
#define PWM_Pulse_2
#define switch_time
35
//
//
//
set 35% as PWM duty cycle
set 60% as PWM duty cycle
adjusting switch time
60
400*2
//Note: To avoid noise, switch_time must be a multiple of PWM period. In this example PWM period = 400us,
// so switch_time = 400*2 us.
void FPPA0 (void)
{
.ADJUST_IC
SYSCLK=IHRC/16, IHRC=16MHz, VDD=5V;
//******* Generating fixed duty cycle waveform ************************
//------ Set the counter upper bound and duty cycle -----------------
PWMG0DTL
PWMG0DTH
=
=
0x00;
PWM_Pulse + dead_zone;
PWMG1DTL
PWMG1DTH
=
=
0x00;
dead_zone;
// After PWMG0 xor PWMG, PWM duty cycle=PWM_Pulse%
PWMG2DTL
PWMG2DTH
=
0x00;
=
PWM_Pulse + dead_zone*2;
PWMGCUBL
PWMGCUBH
=
=
0x00;
100;
//---- Configure clock and pre-scalar ------------------
$ PWMGCLK Enable, /1, sysclk;
//------- Output control -----------------------------
$ PWMG0CEnable,Inverse,PWM_Gen,PA0,gen_xor;
//
//
//
//
After PWMG0 xor PWMG,
output the inversed waveform through PA0
disable PWMG1 output
$ PWMG1C Enable, PWMG1,disable;
$ PWMG2C
Enable, PA3;
output PWMG2 waveform through PA3
while(1)
{
//******** Switching duty cycle ********************************
// To avoid the possible instant disappearance of dead zone, user should comply with the following
// instruction sequence.
// When increase the duty cycle: 50%/60%
→
35%
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PWMG0DTL =
PWMG0DTH =
PWMG2DTL =
PWMG2DTH =
0x00;
PWM_Pulse_1 + dead_zone;
0x00;
PWM_Pulse_1 + dead_zone*2;
.delay
switch_time
// When decrease the duty cycle: 35% → 60%
PWMG2DTL =
PWMG2DTH =
PWMG0DTL =
PWMG0DTH =
0x00;
PWM_Pulse_2 + dead_zone*2;
0x00;
PWM_Pulse_2 + dead_zone;
.delay
switch_time
}
}
The following figures show the waveforms at different condition.
1. The PWM waveform in a fixed-duty cycle:
PWM2
Dead Zone
PWM0
Fig.17: Complementary PWM waveform with dead zones
2. PWM waveform when switching two duty cycles:
PWM2
Dead Zone
35%
60%
35%
PWM0
Fig.18: Complementary PWM waveform with dead zones
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User can find that above example only provides dead zone where PWM are both in high. If need dead
zone where PWM are both in low, you can realize it by resetting each control register’s Inverse like:
$ PWMG0C Enable,PWM_Gen,PA0,gen_xor;
$ PWMG2C Enable, Inverse, PA3;.
5.10 WatchDog Timer
The watchdog timer (WDT) is a counter with clock coming from ILRC. WDT can be cleared by power-on-reset
or by command wdreset at any time. There are four different timeout periods of watchdog timer to be chosen
by setting the misc register, it is:
8k ILRC clocks period if register misc[1:0]=00 (default)
16k ILRC clocks period if register misc[1:0]=01
64k ILRC clocks period if register misc[1:0]=10
256k ILRC clocks period if register misc[1:0]=11
The frequency of ILRC may drift a lot due to the variation of manufacture, supply voltage and temperature; user
should reserve guard band for save operation. Besides, the watchdog period will also be shorter than expected
after Reset or Wakeup events. It is suggested to clear WDT by wdreset command after these events to ensure
enough clock periods before WDT timeout.
When WDT is timeout, PFS123 will be reset to restart the program execution. The relative timing diagram of
watchdog timer is shown as Fig.19.
VDD
t
SBP
WD
Time Out
Program
Execution
Watch Dog Time Out Sequence
Fig.19: Sequence of Watch Dog Time Out
5.11 Interrupt
There are eight interrupt lines for PFS123:
External interrupt PA0/PB5
External interrupt PB0/PA4
ADC interrupt
Timer16 interrupt
GPC interrupt
PWMG interrupt
Timer2 interrupt
Timer3 interrupt
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Every interrupt request line has its own corresponding interrupt control bit to enable or disable it; the hardware
diagram of interrupt function is shown as Fig.20. All the interrupt request flags are set by hardware and cleared
by writing intrq register. When the request flags are set, it can be rising edge, falling edge or both, depending
on the setting of register integs. All the interrupt request lines are also controlled by engint instruction (enable
global interrupt) to enable interrupt operation and disgint instruction (disable global interrupt) to disable it.
The stack memory for interrupt is shared with data memory and its address is specified by stack register sp.
Since the program counter is 16 bits width, the bit 0 of stack register sp should be kept 0. Moreover, user can
use pushaf / popaf instructions to store or restore the values of ACC and flag register to / from stack memory.
Since the stack memory is shared with data memory, the stack position and level are arranged by the compiler
in Mini-C project. When defining the stack level in ASM project, users should arrange their locations carefully to
prevent address conflicts.
Fig.20: Hardware diagram of interrupt controller
Once the interrupt occurs, its operation will be:
The program counter will be stored automatically to the stack memory specified by register sp.
New sp will be updated to sp+2.
Global interrupt will be disabled automatically.
The next instruction will be fetched from address 0x010.
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During the interrupt service routine, the interrupt source can be determined by reading the intrq register.
Note: Even if INTEN=0, INTRQ will be still triggered by the interrupt source.
After finishing the interrupt service routine and issuing the reti instruction to return back, its operation will be:
The program counter will be restored automatically from the stack memory specified by register sp.
New sp will be updated to sp-2.
Global interrupt will be enabled automatically.
The next instruction will be the original one before interrupt.
User must reserve enough stack memory for interrupt, two bytes stack memory for one level interrupt and four
bytes for two levels interrupt. For interrupt operation, the following sample program shows how to handle the
interrupt, noticing that it needs four bytes stack memory to handle interrupt and pushaf.
void
{
FPPA0
(void)
...
$
INTEN PA0;
// INTEN =1; interrupt request when PA0 level changed
// clear INTRQ
INTRQ
ENGINT
...
=
0;
// global interrupt enable
DISGINT
...
// global interrupt disable
}
void
{
Interrupt (void)
// interrupt service routine
PUSHAF
// store ALU and FLAG register
// If INTEN.PA0 will be opened and closed dynamically,
// user can judge whether INTEN.PA0 =1 or not.
// Example: If (INTEN.PA0 && INTRQ.PA0) {…}
// If INTEN.PA0 is always enable,
// user can omit the INTEN.PA0 judgement to speed up interrupt service routine.
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If (INTRQ.PA0)
{
// Here for PA0 interrupt service routine
INTRQ.PA0 = 0;
// Delete corresponding bit (take PA0 for example)
...
}
...
// X : INTRQ = 0;
// It is not recommended to use INTRQ = 0 to clear all at the end of the
// interrupt service routine.
// It may accidentally clear out the interrupts that have just occurred
// and are not yet processed.
POPAF
}
// restore ALU and FLAG register
5.12 Power-Save and Power-Down
There are three operational modes defined by hardware: ON mode, Power-Save mode and Power-Down
modes. ON mode is the state of normal operation with all functions ON, Power-Save mode (“stopexe”) is the
state to reduce operating current and CPU keeps ready to continue, Power-Down mode (“stopsys”) is used to
save power deeply. Therefore, Power-Save mode is used in the system which needs low operating power with
wake-up periodically and Power-Down mode is used in the system which needs power down deeply with
seldom wake-up.
5.12.1 Power-Save mode (“stopexe”)
Using “stopexe” instruction to enter the Power-Save mode, only system clock is disabled, remaining all
the oscillator modules active. For CPU, it stops executing; however, for Timer16, counter keep counting
if its clock source is not the system clock. Wake-up from input pins can be considered as a continuation
of normal execution, the detail information for Power-Save mode shows below:
(1) IHRC and EOSC oscillator modules: No change, keep active if it was enabled.
(2) ILRC oscillator modules: must remain enabled, need to start with ILRC when be wakening up
(3) System clock: Disable, therefore, CPU stops execution.
(4) MTP memory is turned off.
(5) Timer counter: Stop counting if its clock source is system clock or the corresponding oscillator module
is disabled; otherwise, it keeps counting. (The Timer contains TM16, TM2, TM3, PWMG0, PWMG1,
PWMG2.)
(6) Wake-up sources:
a. IO toggle wake-up: IO toggling in digital input mode (PxC bit is 1 and PxDIER bit is 1)
b. Timer wake-up: If the clock source of Timer is not the SYSCLK, the system will be awakened
when the Timer counter reaches the set value.
c. Comparator wake-up: It need setting GPCC.7=1 and GPCS.6=1 to enable the comparator
wake-up function at the same time.
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An example shows how to use Timer16 to wake-up from “stopexe”:
$ T16M
ILRC, /1, BIT8
// Timer16 setting
$ INTEGS BIT_R, xxx;
// BITx 0 to 1 will trigger (default)
…
WORD
STT16
stopexe;
…
count =
count;
0;
The initial counting value of Timer16 is zero and the system will be woken up after the Timer16 counts 256
ILRC clocks.
5.12.2 Power-Down mode (“stopsys”)
Power-Down mode is the state of deeply power-saving with turning off all the oscillator modules. By using
the “stopsys” instruction, this chip will be put on Power-Down mode directly. The following shows the
internal status of PFS123 detail when “stopsys” command is issued:
(1) All the oscillator modules are turned off.
(2) MTP memory is turned off.
(3) The contents of SRAM and registers remain unchanged.
(4) Wake-up sources: IO toggle in digital mode. (PxDIER bit is 1)
Wake-up from input pins can be considered as a continuation of normal execution. To minimize power
consumption, all the I/O pins should be carefully manipulated before entering power-down mode. The
reference sample program for power down is shown as below:
CLKMD
CLKMD.4
…
=
=
0xF4;
0;
//
//
Change clock from IHRC to ILRC
disable IHRC
while (1)
{
}
STOPSYS;
//
//
//
enter power-down
if (…) break;
if wakeup happen and check OK, then return to high speed,
else stay in power-down mode again.
CLKMD =
0x34;
//
Change clock from ILRC to IHRC/2
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5.12.3 Wake-up
After entering the Power-Down or Power-Save modes, the PFS123 can be resumed to normal operation
by toggling IO pins. Wake-up from timer are available for Power-Save mode ONLY. Table 5 shows the
differences in wake-up sources between STOPSYS and STOPEXE.
Differences in wake-up sources between STOPSYS and STOPEXE
IO Toggle
Yes
Timer wake-up
STOPSYS
STOPEXE
No
Yes
Yes
Table 5: Differences in wake-up sources between Power-Save mode and Power-Down mode
When using the IO pins to wake-up the PFS123, registers padier should be properly set to enable the
wake-up function for every corresponding pin. The time for normal wake-up is about 3000 ILRC clocks
counting from wake-up event; fast wake-up can be selected to reduce the wake-up time by misc register,
and the time for fast wake-up is about 45 ILRC clocks from IO toggling.
Suspend mode
STOPEXE suspend
or
Wake-up mode
Wake-up time (tWUP) from IO toggle
45 * TILRC,
Where TILRC is the time period of ILRC
Fast wake-up
STOPSYS suspend
STOPEXE suspend
or
3000 * TILRC
,
Normal wake-up
Where TILRC is the clock period of ILRC
STOPSYS suspend
Please notice that when Fast boot-up is selected, no matter which wake-up mode is selected in misc.5,
the wake-up mode will be forced to be FAST. If Normal boot-up is selected, the wake-up mode is
determined by misc.5.
5.13 IO Pins
All the pins can be independently set into two states output or input by configuring the data registers (pa, pb,
pc), control registers (pac, pbc, pcc) and pull-high registers (paph, pbph, pcph). Four pins of them, PB2,
PB3, PC0 & PC1, have additional pull-low registers (pbpl.2, pbpl.3, pcpl.0, pcpl.1). All these pins have
Schmitt-trigger input buffer and output driver with CMOS level. When it is set to output low, the pull-high /
pull-low resistor is turned off automatically. If user wants to read the pin state, please notice that it should be
set to input mode before reading the data port; if user reads the data port when it is set to output mode, the
reading data comes from data register, NOT from IO pad. As an example, Table 6 shows the configuration
table of bit 0 of port A. The hardware diagram of IO buffer is also shown as Fig.21.
pa.0 pac.0 paph.0
Description
Input without pull-high resistor
X
X
0
1
1
0
0
1
1
1
0
1
X
0
1
Input with pull-high resistor
Output low without pull-high resistor
Output high without pull-high resistor
Output high with pull-high resistor
Table 6: PA0 Configuration Table
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Fig. 21: Hardware diagram of IO buffer
PB4 and PB5 can adjust their drive and sink current by code option PB4_PB5_Drive.
Other than PA5, all the IO pins have the same structure; PA5 can be open-drain ONLY when setting to output
mode (without Q1). The corresponding bits in registers padier / pbdier / pcdier should be set to low to prevent
leakage current for those pins are selected to be analog function. When PFS123 is put in power-down or
power-save mode, every pin can be used to wake-up system by toggling its state. Therefore, those pins
needed to wake-up system must be set to input mode and set the corresponding bits of registers pxdier to
high. The same reason, padier.0 should be set high when PA0 is used as external interrupt pin, and so for
other external interrupt pins: PB0, PA4 and PB5.
5.14 Reset and LVR
5.14.1 Reset
There are many causes to reset the PFS123, once reset is asserted, most of all the registers in PFS123 will
be set to default values, system should be restarted once abnormal cases happen, or by jumping program
counter to address 0x0. The data memory is in uncertain state when reset comes from power-up and LVR;
however, the content will be kept when reset comes from PRSTB pin or WDT timeout.
5.14.2 LVR reset
By code option, there are many different levels of LVR for reset; usually, user selects LVR reset level to be
in conjunction with operating frequency and supply voltage.
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5.15 Analog-to-Digital Conversion (ADC) module
Fig. 22: ADC Block Diagram
There are 8 registers when using the ADC module, which are:
ADC Control Register (adcc)
ADC Regulator Control Register (adcrgc)
ADC Mode Register (adcm)
ADC Result Register (adcrh, adcrl)
Port A/B/C Digital Input Enable Register (padier, pbdier, pcdier)
The following steps are required to do the AD conversion procedure:
(1) Configure the voltage reference high by adcrgc register
(2) Configure the AD conversion clock by adcm register
(3) Configure the pin as analog input by padier, pbdier, pcdier register
(4) Select the ADC input channel by adcc register
(5) Enable the ADC module by adcc register
(6) Execute the AD conversion and check if ADC data is ready
set ‘1’ to addc.6 to start the conversion and check whether addc.6 is ‘1’
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(7) Read the ADC result registers
5.15.1 The input requirement for AD conversion
For the AD conversion to meet its specified accuracy, the charge holding capacitor (CHOLD) must be allowed
to fully charge to the voltage reference high level and discharge to the voltage reference low level. The
analog input model is shown as Fig.23, the signal driving source impedance (Rs) and the internal sampling
switch impedance (Rss) will affect the required time to charge the capacitor CHOLD directly. The internal
sampling switch impedance may vary with ADC supply voltage; the signal driving source impedance will
affect accuracy of analog input signal. User must ensure the measured signal is stable before sampling;
therefore, the maximum signal driving source impedance is highly dependent on the frequency of signal to
be measured. The recommended maximum impedance for analog driving source is about 10KΩ under
500KHz input frequency.
Fig. 23: Analog Input Model
5.15.2 Select the reference high voltage
The ADC reference high voltage can be selected via bit[7] of register adcrgc and its option can be VDD or
PB1 from external pin.
5.15.3 ADC clock selection
Before starting the AD conversion, the minimum signal acquisition time should be met for the selected
analog input signal, the selection of ADCLK must be met the minimum signal acquisition time.
The clock of ADC module (ADCLK) can be selected by adcm register; there are 8 possible options for
ADCLK from CLK÷1 to CLK÷128 (CLK is the system clock). Due to the signal acquisition time TACQ is one
clock period of ADCLK, the ADCLK must meet that requirement. The recommended ADC clock is to
operate at 2us.
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5.15.4 Configure the analog pins
There are 14 analog signals can be selected for AD conversion, 13 analog input signals come from external
pins and one is from internal band-gap reference voltage 1.2V. For those external pins defined as analog
input, to avoid leakage current from the digital circuit of the shared IO ports, please always remember to
disable the digital input function (set the corresponding bit of padier, pbdier or pcdier register to be 0).
Due to the measurement signals of ADC are very small; user should avoid the measured signal to be
interfered during the measurement period. Thus, the selected pin should (1) be set to input mode (2) turn
off weak pull-high and pull-low resistor (3) set the corresponding pin to analog input by port A/B/C digital
input disable register (padier / pbdier / pcdier).
5.15.5 Using the ADC
The following example shows how to use ADC with PB0~PB3.
First, defining the selected pins:
PBC
=
=
=
=
0B_XXXX_0000;
0B_XXXX_0000;
0B_XXXX_00XX;
0B_XXXX_0000;
//
//
//
//
PB0 ~ PB3 as Input
PBPH
PBPL
PBDIER
PB0 ~ PB3 without pull-high resistor
PB2 ~ PB3 without pull-low resistor
PB0 ~ PB3 digital input is disabled
Next, setting ADCC register, example as below:
$
$
$
ADCC Enable, PB3;
ADCC Enable, PB2;
ADCC Enable, PB0;
//
//
//
set PB3 as ADC input
set PB2 as ADC input
set PB0 as ADC input
Next, setting ADCM register, example as below:
$
$
ADCM /16;
ADCM /8;
//
//
recommend /16 @System Clock=8MHz
recommend /8 @System Clock=4MHz
Next, delay 400us, example as below:
.Delay 8*400;
.Delay 4*400;
//
//
System Clock=8MHz
System Clock=4MHz
Then, start the ADC conversion:
AD_START =
1;
// start ADC conversion
while(!AD_DONE) NULL;
// wait ADC conversion result
Finally, it can read ADC result when AD_DONE is high:
WORD
Data$1
Data$0
Data
Data;
//
two bytes result: ADCRH and ADCRL
=
=
=
ADCRH;
ADCRL;
Data >> 4;
The ADC can be disabled by using the following method:
ADCC Disable;
$
or
ADCC
=
0;
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5.15.6 How to calculate ADC input voltage VIN
For PFS122, only VDD but not 1.2V bandgap voltage can be selected as the VREF of the ADC. When VDD
is not regulated, users have to use the reading of 1.2V bandgap voltage to deduce the input voltage (VIN)
by the ratio of the readings. The principle is as below:
V
BG / VDD = NBG / 4096 ....(1)
VIN / VDD = NIN / 4096 ....(2)
Where VIN is the analog input voltage
BG is the 1.2V bandgap voltage
V
NIN is the corresponding ADC reading of VIN
NBG is the corresponding ADC reading of VBG
VDD is the VDD at the measuring instant
4096 is the full swing reading when VIN=VDD (12bit: 212 = 4096)
(2)/(1) we get
VIN/VBG = NIN/NBG
And so
VIN = NIN / NBG *VBG
It means users can firstly get the readings for VIN and VBG respectively in a very short period that VDD
remains unchanged. And then use multiplication and division program module or use look-up table
method to finally get the VIN voltage.
If necessary, please contact FAE for demo code reference.
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8bit MTP MCU with 12-bit R-Type ADC
6. IO Registers
6.1. ACC Status Flag Register (flag), IO address = 0x00
Bit Reset R/W
Description
7 - 4
3
-
-
Reserved. Please do not use.
0
R/W
OV (Overflow Flag). This bit is set to be 1 whenever the sign operation is overflow.
AC (Auxiliary Carry Flag). There are two conditions to set this bit, the first one is carry out
of low nibble in addition operation and the other one is borrow from the high nibble into low
nibble in subtraction operation.
2
0
R/W
C (Carry Flag). There are two conditions to set this bit, the first one is carry out in addition
operation, and the other one is borrow in subtraction operation. Carry is also affected by
shift with carry instruction.
1
0
0
0
R/W
R/W
Z (Zero Flag). This bit will be set when the result of arithmetic or logic operation is zero;
Otherwise, it is cleared.
6.2. Stack Pointer Register (sp), IO address = 0x02
Bit Reset R/W
Description
Stack Pointer Register. Read out the current stack pointer, or write to change the stack
pointer.
7 - 0 R/W
-
6.3. Clock Mode Register (clkmd), IO address = 0x03
Bit Reset R/W
Description
System clock (CLK) selection:
Type 0, clkmd[3]=0 Type 1, clkmd[3]=1
000: IHRC÷4
001: IHRC÷2
010: reserved
011: EOSC÷4
100: EOSC÷2
101: EOSC
000: IHRC÷16
001: IHRC÷8
010: ILRC÷16 (ICE does NOT Support.)
011: IHRC÷32
7 - 5
111
R/W
100: IHRC÷64
101: EOSC÷8
110: ILRC÷4
11x: reserved.
111: ILRC (default)
4
3
1
0
R/W Internal High RC Enable. 0 / 1: disable / enable
Clock Type Select. This bit is used to select the clock type in bit [7:5].
R/W
0 / 1: Type 0 / Type 1.
Internal Low RC Enable. 0 / 1: disable / enable
R/W
2
1
If ILRC is disabled, watchdog timer is also disabled.
1
0
1
0
R/W Watch Dog Enable. 0 / 1: disable / enable
R/W Pin PA5/PRSTB function. 0 / 1: PA5 / PRSTB.
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6.4. Interrupt Enable Register (inten), IO address = 0x04
Bit
7
Reset
R/W
Description
0
0
0
0
0
0
0
0
R/W
Enable interrupt from Timer3. 0 / 1: disable / enable
6
R/W Enable interrupt from Timer2. 0 / 1: disable / enable
R/W Enable interrupt from PWMG. 0 / 1: disable / enable
5
4
R/W
Enable interrupt from comparator. 0 / 1: disable / enable
3
R/W Enable interrupt from ADC. 0 / 1: disable / enable
R/W Enable interrupt from Timer16 overflow. 0 / 1: disable / enable
R/W Enable interrupt from PB0/PA4. 0 / 1: disable / enable
R/W Enable interrupt from PA0/PB5. 0 / 1: disable / enable
2
1
0
6.5. Interrupt Request Register (intrq), IO address = 0x05
Bit Reset R/W
Description
Interrupt Request from Timer3, this bit is set by hardware and cleared by software.
0 / 1: No request / Request
7
6
5
4
3
2
1
0
-
-
-
-
-
-
-
-
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Interrupt Request from Timer2, this bit is set by hardware and cleared by software.
0 / 1: No request / Request
Interrupt Request from PWMG, this bit is set by hardware and cleared by software.
0 / 1: No request / Request
Interrupt Request from comparator, this bit is set by hardware and cleared by software.
0 / 1: No request / Request
Interrupt Request from ADC, this bit is set by hardware and cleared by software.
0 / 1: No request / Request
Interrupt Request from Timer16, this bit is set by hardware and cleared by software.
0 / 1: No request / Request
Interrupt Request from pin PB0/PA4, this bit is set by hardware and cleared by software.
0 / 1: No request / Request
Interrupt Request from pin PA0/PB5, this bit is set by hardware and cleared by software.
0 / 1: No Request / request
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8bit MTP MCU with 12-bit R-Type ADC
6.6. Timer16 mode Register (t16m), IO address = 0x06
Bit
Reset R/W
Description
Timer16 Clock source selection.
000: disable
001: CLK (system clock)
010: reserved
7 - 5
000
R/W 011: PA4 falling edge (from external pin)
100: IHRC
101: EOSC
110: ILRC
111: PA0 falling edge (from external pin)
Timer16 clock pre-divider.
00: ÷1
4 - 3
00
R/W 01: ÷4
10: ÷16
11: ÷64
Interrupt source selection. Interrupt event happens when the selected bit status is changed.
0 : bit 8 of Timer16
1 : bit 9 of Timer16
2 : bit 10 of Timer16
R/W 3 : bit 11 of Timer16
4 : bit 12 of Timer16
5 : bit 13 of Timer16
6 : bit 14 of Timer16
7 : bit 15 of Timer16
2 - 0
000
6.7. External Oscillator setting Register (eoscr), IO address = 0x0a
Bit
Reset R/W
Description
7
0
WO Enable external crystal oscillator. 0 / 1 : Disable / Enable
External crystal oscillator selection.
00 : reserved
6 - 5
00
WO 01 : Low driving capability, for lower frequency, ex: 32KHz crystal oscillator
10 : Middle driving capability, for middle frequency, ex: 1MHz crystal oscillator
11 : High driving capability, for higher frequency, ex: 4MHz crystal oscillator
4 - 1
0
-
-
Reserved. Please keep 0 for future compatibility.
0
WO Power-down the Band-gap and LVR hardware modules. 0 / 1: normal / power-down.
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8bit MTP MCU with 12-bit R-Type ADC
6.8. Interrupt Edge Select Register (integs), IO address = 0x0c
Bit
Reset
R/W
Description
7 - 5
-
-
Reserved.
Timer16 edge selection.
4
0
WO 0 : rising edge of the selected bit to trigger interrupt
1 : falling edge of the selected bit to trigger interrupt
PB0/PA4 edge selection.
00: both rising edge and falling edge of the selected bit to trigger interrupt
WO 01: rising edge of the selected bit to trigger interrupt
10: falling edge of the selected bit to trigger interrupt
11: reserved.
3 - 2
00
PA0/PB5 edge selection.
00 : both rising edge and falling edge of the selected bit to trigger interrupt
WO 01 : rising edge of the selected bit to trigger interrupt
10 : falling edge of the selected bit to trigger interrupt
11 : reserved.
1 - 0
00
6.9. Port A Digital Input Enable Register (padier), IO address = 0x0d
Bit
Reset
R/W
Description
Enable PA7 digital input and wake-up event.
1 / 0 : enable / disable
7
1
WO
This bit should be set to low to prevent leakage current when external crystal oscillator is
used. If this bit is set to low, PA7 can NOT be used to wake-up the system.
Enable PA6 digital input and wake-up event.
1 / 0 : enable / disable
6
5
1
1
WO
WO
This bit should be set to low to prevent leakage current when external crystal oscillator is
used. If this bit is set to low, PA6 can NOT be used to wake-up the system.
Enable PA5 digital input and wake-up event.
1 / 0 : enable / disable
This bit can be set to low to disable wake-up from PA5 toggling.
Enable PA4 digital input, wake-up event and interrupt request.
1 / 0 : enable / disable
4
1
WO
This bit should be set to low when PA4 is assigned as AD input to prevent leakage
current. If this bit is set to low, PA4 can NOT be used to wake-up the system and interrupt
request from this pin.
Enable PA3 digital input and wake-up event.
1 / 0 : enable / disable
3
2 - 1
0
1
1
1
WO
WO
WO
This bit should be set to low when PA3 is assigned as AD input to prevent leakage
current. If this bit is set to low, PA3 can NOT be used to wake-up the system.
Reserved.
Enable PA0 digital input, wake-up event and interrupt request.
1 / 0 : enable / disable
This bit can be set to low to prevent leakage current when PA0 is assigned as AD input,
and to disable wake-up from PA0 toggling and interrupt request from this pin.
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6.10.Port B Digital Input Enable Register (pbdier), IO address = 0x0e
Bit
Reset R/W
Description
Enable PB7~PB6 digital input and wake-up event.
1 / 0 : enable / disable
7 - 6
11
1
WO
These bits can be set to low to prevent leakage current when PB7~PB6 are assigned as AD
inputs. When disable is selected, the wake-up function from these pins are also disabled.
Enable PB5 digital input, wake-up event and interrupt request.
1 / 0 : enable / disable
5
4 - 1
0
WO This bit should be set to low when PB5 is assigned as AD input to prevent leakage current. If
this bit is set to low, PB5 can NOT be used to wake-up the system and interrupt request from
this pin.
Enable PB4~PB1 digital input and wake-up event.
1 / 0 : enable / disable
1111
WO
These bits can be set to low to prevent leakage current when PB4~PB1 are assigned as AD
inputs. When disable is selected, the wake-up function from these pins are also disabled.
Enable PB0 digital input, wake-up event and interrupt request.
1 / 0 : enable / disable
1
WO This bit should be set to low when PB0 is assigned as AD input to prevent leakage current. If
this bit is set to low, PB0 can NOT be used to wake-up the system and interrupt request from
this pin.
6.11.Port C Digital Input Enable Register (pcdier), IO address = 0x0f
Bit
Reset R/W
Description
7 - 4
-
-
Reserved.
Enable PC3~PC0 digital input and wake-up event.
1 / 0 : enable / disable
3 - 0
0xF
WO These bits can be set to low to prevent leakage current when PC2~PC1 are assigned as AD
inputs. When disable is selected, the wake-up function and interrupt requests from these
pins are also disabled.
Note: Detail settings please refer to Section 9.3.
6.12. Port A Data Register (pa), IO address = 0x10
Bit
Reset R/W
0x00 R/W Data register for Port A.
Description
7 - 0
6.13. Port A Control Register (pac), IO address = 0x11
Bit
Reset R/W
Description
Port A control registers. This register is used to define input mode or output mode for each
corresponding pin of port A. 0 / 1: input / output
7 - 0
0x00
R/W
Please note that PA5 can be INPUT or OUTPUT LOW ONLY, the output state will be tri-state
when PA5 is programmed into output mode with data 1.
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8bit MTP MCU with 12-bit R-Type ADC
6.14. Port A Pull-High Register (paph), IO address = 0x12
Bit
Reset R/W
Description
Port A pull-high register. This register is used to enable the internal pull-high device on each
7 - 0
0x00 R/W corresponding pin of port A and this pull high function is active only for input mode.
0 / 1 : disable / enable
6.15. Port B Data Register (pb), IO address = 0x13
Bit
Reset R/W
0x00 R/W Data register for Port B.
Description
7 - 0
6.16. Port B Control Register (pbc), IO address = 0x14
Bit
Reset R/W
Description
Port B control register. This register is used to define input mode or output mode for each
corresponding pin of port B. 0 / 1: input / output
7 - 0
0x00 R/W
6.17. Port B Pull-High Register (pbph), IO address = 0x15
Bit
Reset R/W
Description
Port B pull-high register. This register is used to enable the internal pull-high device on each
corresponding pin of port B and this pull high function is active only for input mode.
0 / 1 : disable / enable
7 - 0
0x00 R/W
6.18. Port C Data Register (pc), IO address = 0x16
Bit
Reset R/W
Description
7 - 4
3 - 0
-
-
Reserved.
0x00
R/W Data register for Port C.
6.19. Port C Control Register (pcc), IO address = 0x17
Bit
Reset R/W
Description
7 - 4
-
-
Reserved.
Port C control register. This register is used to define input mode or output mode for each
corresponding pin of port C. 0 / 1: input / output
3 - 0
0x00
R/W
6.20. Port C Pull-High Register (pcph), IO address = 0x18
Bit
Reset R/W
Description
7 - 4
-
-
Reserved.
Port C pull-high register. This register is used to enable the internal pull-high device on each
corresponding pin of port C and this pull high function is active only for input mode.
0 / 1 : disable / enable
3 - 0
0x00
R/W
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8bit MTP MCU with 12-bit R-Type ADC
6.21. Port B Pull-Low Register (pbpl), IO address = 0x19
Bit
7 - 4
3
Reset R/W
Description
-
0
0
-
-
Reserved.
R/W Port PB3 pull-low register. 0 / 1 : disable / enable
R/W Port PB2 pull-low register. 0 / 1 : disable / enable
2
1 - 0
-
Reserved.
6.22. Port C Pull-Low Register (pcpl), IO address = 0x1a
Bit
7 - 2
1
Reset R/W
Description
-
-
Reserved.
0
0
R/W Port PC1 pull-low register. 0 / 1 : disable / enable
R/W Port PC0 pull-low register. 0 / 1 : disable / enable
0
6.23. ADC Control Register (adcc), IO address = 0x20
Bit
Reset
R/W
Description
Enable ADC function. 0/1: Disable/Enable.
7
0
R/W
ADC process control bit.
6
0
R/W
Write “1” to start conversion
Read “1” to indicate the ADC is ready or end of conversion.
Channel selector. These four bits are used to select input signal for AD conversion.
0000: PB0/AD0,
0001: PB1/AD1,
0010: PB2/AD2,
0011: PB3/AD3,
0100: PB4/AD4,
0101: PB5/AD5,
0110: PB6/AD6,
5 - 2
0000
R/W
0111: PB7/AD7,
1000: PA3/AD8,
1001: PA4/AD9,
1010: PA0/AD10,
1011: PC1/AD11, (PA1 for ICE at this address)
1100: PC2/AD12, (PC1 for ICE at this address)
1111: (Channel F) Band-gap reference voltage
Others: reserved
0 - 1
-
-
Reserved. (keep 0 for future compatibility)
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8bit MTP MCU with 12-bit R-Type ADC
6.24. ADC Mode Register (adcm), IO address = 0x21
Bit
Reset
R/W
Description
Reserved. (keep 0 for future compatibility)
7 - 4
-
-
ADC clock source selection.
000: CLK (system clock) ÷ 1,
001: CLK (system clock) ÷ 2,
010: CLK (system clock) ÷ 4,
011: CLK (system clock) ÷ 8,
100: CLK (system clock) ÷ 16,
101: CLK (system clock) ÷ 32,
110: CLK (system clock) ÷ 64,
111: CLK (system clock) ÷ 128,
Reserved.
3 - 1
000
R/W
0
-
-
6.25. ADC Result High Register (adcrh), IO address = 0x22
Bit Reset
R/W
Description
These eight read-only bits will be the bit [11:4] of AD conversion result. The bit 7 of this
register is the MSB of ADC result for any resolution.
7 - 0
-
RO
6.26. ADC Result Low Register (adcrl), IO address = 0x23
Bit
Reset
R/W
RO
-
Description
These four bits will be the bit [3:0] of AD conversion result.
Reserved
7 - 4
3 - 0
-
-
6.27. ADC Regulator Control Register (adcrgc), IO address = 0x24
Bit
Reset R/W
Description
ADC reference high voltage.
7
0
-
WO 0: VDD
1: External PIN (PB1)
Reserved.
6 - 0
-
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6.28. MISC Register (misc), IO address = 0x26
Bit
Reset R/W
Description
Reserved. (keep 0 for future compatibility)
7 - 6
-
-
Enable fast Wake up. Fast wake-up is NOT supported when EOSC is enabled.
0: Normal wake up.
5
4
0
WO
The wake-up time is 3000 ILRC clocks (Not for fast boot-up)
1: Fast wake up.
The wake-up time is 45 ILRC clocks.
Enable VDD/2 LCD bias voltage generator
0 / 1 : Disable / Enable (ICE cannot be dynamically switched)
0
WO If Code Option selects LCD output, but MISC.4 does not set to 1, then the VDD/2 bias cannot
be output on the IC. However, the emulator is always OK. Two above phenomena are
different.
3
2
-
-
Reserved.
Disable LVR function.
0 / 1 : Enable / Disable
Watch dog time out period
00: 8k ILRC clock period
0
WO
1 - 0
00
WO 01: 16k ILRC clock period
10: 64k ILRC clock period
11: 256k ILRC clock period
6.29. Comparator Control Register (gpcc), IO address = 0x2b
Bit
Reset
R/W
Description
Enable comparator. 0 / 1 : disable / enable
7
0
R/W When this bit is set to enable, please also set the corresponding analog input pins to be
digital disable to prevent IO leakage.
Comparator result of comparator.
6
5
4
-
RO
0: plus input < minus input
1: plus input > minus input
Select whether the comparator result output will be sampled by TM2_CLK?
0
0
R/W 0: result output NOT sampled by TM2_CLK
1: result output sampled by TM2_CLK
Inverse the polarity of result output of comparator.
R/W 0: polarity is NOT inversed.
1: polarity is inversed.
Selection the minus input (-) of comparator.
000 : PA3
001 : PA4
010 : Internal 1.20 volt band-gap reference voltage
3 - 1
000
R/W
011 : Vinternal R
100 : PB6 (not for EV5)
101 : PB7 (not for EV5)
11X: reserved
Selection the plus input (+) of comparator.
R/W 0 : Vinternal R
0
0
1 : PA4
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8bit MTP MCU with 12-bit R-Type ADC
6.30. Comparator Selection Register (gpcs), IO address = 0x2c
Bit
Reset
R/W
Description
Comparator output enable (to PA0).
0 / 1 : disable / enable
7
0
WO
Wakeup by comparator enable. (The comparator wakeup effectively when gpcc.6 electrical
level changed)Reserved.
0 / 1 : disable / enable
6
0
WO
5
4
0
0
WO Selection of high range of comparator.
WO Selection of low range of comparator.
Selection the voltage level of comparator.
3 - 0
0000
WO
0000 (lowest) ~ 1111 (highest)
6.31. Timer2 Control Register (tm2c), IO address = 0x30
Bit Reset
R/W
Description
Timer2 clock selection.
0000 : disable
0001 : CLK
0010 : IHRC or IHRC *2 (by code option TMx_source)
0011 : EOSC
0100 : ILRC
0101 : comparator output (ICE does NOT support.)
1000 : PA0 (rising edge)
7 - 4
0000
R/W
1001 : ~PA0 (falling edge)
1010 : PB0 (rising edge)
1011 : ~PB0 (falling edge)
1100 : PA4 (rising edge)
1101 : ~PA4 (falling edge)
Others: reserved
Notice: In ICE mode and IHRC is selected for Timer2 clock, the clock sent to Timer2 does
NOT be stopped, Timer2 will keep counting when ICE is in halt state.
Timer2 output selection.
00 : disable
01 : PB2
3 - 2
00
R/W
10 : PA3
11 : PB4
Timer2 mode selection.
1
0
0
0
R/W
R/W
0 / 1 : period mode / PWM mode
Enable to inverse the polarity of Timer2 output.
0 / 1: disable / enable
6.32. Timer2 Counter Register (tm2ct), IO address = 0x31
Bit
Reset
R/W
Description
7 - 0
0x00
R/W
Bit [7:0] of Timer2 counter register.
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PFS123
8bit MTP MCU with 12-bit R-Type ADC
6.33. Timer2 Scalar Register (tm2s), IO address = 0x32
Bit
Reset
R/W
Description
PWM resolution selection.
0 : 8-bit
7
0
WO
1 : 6-bit or 7-bit (by code option TMx_bit)
Timer2 clock pre-scalar.
00 : ÷ 1
6 - 5
00
WO
WO
01 : ÷ 4
10 : ÷ 16
11 : ÷ 64
4 - 0 00000
Timer2 clock scalar.
6.34. Timer2 Bound Register (tm2b), IO address = 0x33
Bit
Reset R/W
0x00 WO Timer2 bound register.
Description
7 - 0
6.35. Timer3 Control Register (tm3c), IO address = 0x34
Bit Reset
R/W
Description
Timer3 clock selection.
0000 : disable
0001 : CLK
0010 : IHRC or IHRC *2 (by code option TMx_source)
0011 : EOSC
0100 : ILRC
0101 : comparator output
1000 : PA0 (rising edge)
7 - 4
0000
R/W
1001 : ~PA0 (falling edge)
1010 : PB0 (rising edge)
1011 : ~PB0 (falling edge)
1100 : PA4 (rising edge)
1101 : ~PA4 (falling edge)
Others: reserved
Notice: In ICE mode and IHRC is selected for Timer3 clock, the clock sent to Timer3 does
NOT be stopped, Timer3 will keep counting when ICE is in halt state.
Timer3 output selection.
00 : disable
3 - 2
00
R/W 01 : PB5
10 : PB6
11 : PB7
Timer3 mode selection.
1
0
0
0
R/W
R/W
0 / 1 : period mode / PWM mode
Enable to inverse the polarity of Timer3 output.
0 / 1: disable / enable
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PFS123
8bit MTP MCU with 12-bit R-Type ADC
6.36. Timer3 Counter Register (tm3ct), IO address = 0x35
Bit
Reset R/W
0x00 R/W Bit [7:0] of Timer2 counter register.
Description
7 - 0
6.37. Timer3 Scalar Register (tm3s), IO address = 0x36
Bit
Reset
R/W
Description
PWM resolution selection.
0 : 8-bit
7
0
WO
1 : 6-bit or 7-bit (by code option TMx_bit)
Timer3 clock pre-scalar.
00 : ÷ 1
6 - 5
00
WO
WO
01 : ÷ 4
10 : ÷ 16
11 : ÷ 64
4 - 0 00000
Timer3 clock scalar.
6.38. Timer3 Bound Register (tm3b), IO address = 0x37
Bit
Reset
R/W
Description
7 - 0
0x00
WO
Timer3 bound register.
6.39. PWMG0 control Register (pwmg0c), IO address = 0x40
Bit
Reset
R/W
Description
7
-
-
Reserved.
6
5
-
RO
Output status of PWMG0 generator.
0
WO Enable to inverse the polarity of PWMG0 generator output. 0 / 1: disable / enable.
PWMG0 output selection.
4
3 - 1
0
0
000
0
WO 0: PWMG0 Output
1: PWMG0 XOR PWMG1 or PWMG0 OR PWMG1 (by pwmg0c.0)
PWMG0 Output Port Selection
000: PWMG0 Output Disable
001: PWMG0 Output to PB5
010: PWMG0 Output to PC2
R/W
011: PWMG0 Output to PA0
100: PWMG0 Output to PB4
101: PWMG0 Output to PB6 (Available if the PB6 is not assigned to output PWMG1)
others: Reserved
PWMG0 output pre- selection.
R/W 0: PWMG0 XOR PWMG1
1: PWMG0 OR PWMG1
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PDK-DS-PFS123-EN_V000-Aug. 26, 2020
PFS123
8bit MTP MCU with 12-bit R-Type ADC
6.40. PWMG Clock Register (pwmgclk), IO address = 0x41
Bit
Reset
R/W
Description
PWMG Disable/ Enable
7
0
WO 0: PWMG Disable
1: PWMG Enable
PWMG clock pre-scalar.
000: ÷1
001: ÷2
010: ÷4
011: ÷8
6 - 4
000
WO
100: ÷16
101: ÷32
110: ÷64
111: ÷128
3 - 1
0
-
-
Reserved.
PWMG clock source selection
0
WO 0: System Clock
1: IHRC or IHRC*2 (by code option PWM_Source)
6.41. PWMG0 Duty Value High Register (pwmg0dth), IO address = 0x42
Bit
Reset
R/W
Description
7 - 0
-
WO Bit[10:3] of PWMG0 Duty.
6.42. PWMG0 Duty Value Low Register (pwmg0dtl), IO address = 0x43
Bit
Reset
R/W
Description
7 - 5
-
WO Bit[2:0] of PWMG0 Duty.
4 - 0
-
-
Reserved.
Note: It’s necessary to write PWMG0 Duty_Value Low Register before writing PWMG0 Duty_Value High Register.
6.43. PWMG Counter Upper Bound High Register (pwmgcubh ), IO address = 0x44
Bit
Reset
R/W
Description
7 - 0
-
WO Bit[10:3] of PWMG Counter Bound.
6.44. PWMG Counter Upper Bound Low Register (pwmgcubl ), IO address = 0x45
Bit
Reset
R/W
Description
7 - 6
-
WO Bit[2:1] of PWMG Counter Bound.
5 - 0
-
-
Reserved.
©Copyright 2020, PADAUK Technology Co. Ltd
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PDK-DS-PFS123-EN_V000-Aug. 26, 2020
PFS123
8bit MTP MCU with 12-bit R-Type ADC
6.45. PWMG1 control Register (pwmg1c), IO address = 0x46
Bit
Reset
R/W
Description
7
-
-
Reserved.
6
5
-
RO
Output status of PWMG1 generator.
0
R/W Enable to inverse the polarity of PWMG1 generator output. 0 / 1: disable / enable.
PWMG1 output selection:
0: PWMG1
1: PWMG2
4
0
R/W
PWMG1 Output Port Selection:
000: PWMG1 Output Disable
001: PWMG1 Output to PB6
3 - 1
000
R/W 010: PWMG1 Output to PC3
011: PWMG1 Output to PA4
100: PWMG1 Output to PB7
1xx: Reserved
0
-
R/W Reserved.
6.46. PWMG1 Duty Value High Register (pwmg1dth), IO address = 0x48
Bit
Reset
R/W
Description
7 - 0
-
WO Bit[10:3] of PWMG1 Duty
6.47. PWMG1 Duty Value Low Register (pwmg1dtl), IO address = 0x49
Bit
Reset
R/W
Description
7 - 5
-
WO Bit[2:0] of PWMG1 Duty.
4 - 0
-
-
Reserved.
Note: It’s necessary to write PWMG1 Duty_Value Low Register before writing PWMG1 Duty_Value High Register.
©Copyright 2020, PADAUK Technology Co. Ltd
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PDK-DS-PFS123-EN_V000-Aug. 26, 2020
PFS123
8bit MTP MCU with 12-bit R-Type ADC
6.48. PWMG2 control Register (pwmg2c), IO address = 0x4C
Bit
Reset
R/W
Description
7
-
-
Reserved.
6
5
-
RO
Output status of PWMG2 generator.
0
R/W Enable to inverse the polarity of PWMG2 generator output. 0 / 1: disable / enable.
PWMG2 output selection:
0: PWMG2
4
0
R/W
1: PWMG2 ÷2
PWMG2 Output Port Selection:
000: PWMG2 Output Disable
001: PWMG2 Output to PB3
010: PWMG2 Output to PC0
3 - 1
000
R/W 011: PWMG2 Output to PA3
100: PWMG2 Output to PB2
101: PWMG2 Output to PA5
110: PWMG2 Output to PB5 (Available if the PB5 is not assigned to output PWMG0)
111: Reserved
0
-
R/W Reserved.
6.49. PWMG2 Duty Value High Register (pwmg2dth), IO address = 0x4E
Bit
Reset
R/W
Description
7 - 0
-
WO Bit[10:3] of PWMG2 Duty.
6.50. PWMG2 Duty Value Low Register (pwmg2dtl), IO address = 0x4F
Bit
Reset
R/W
Description
7 - 5
-
WO Bit[2:0] of PWMG2 Duty.
4 - 0
-
-
Reserved.
Note: It’s necessary to write PWMG2 Duty_Value Low Register before writing PWMG2 Duty_Value High Register.
©Copyright 2020, PADAUK Technology Co. Ltd
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PDK-DS-PFS123-EN_V000-Aug. 26, 2020
PFS123
8bit MTP MCU with 12-bit R-Type ADC
7. Instructions
Symbol
Description
ACC
a
Accumulator (Abbreviation of accumulator)
Accumulator (symbol of accumulator in program)
sp
flag
I
Stack pointer
ACC status flag register
Immediate data
&
Logical AND
|
Logical OR
←
^
Movement
Exclusive logic OR
+
Add
-
〜
〒
OV
Z
Subtraction
NOT (logical complement, 1’s complement)
NEG (2’s complement)
Overflow (The operational result is out of range in signed 2’s complement number system)
Zero (If the result of ALU operation is zero, this bit is set to 1)
Carry (The operational result is to have carry out for addition or to borrow carry for subtraction in
unsigned number system)
C
Auxiliary Carry
AC
(If there is a carry out from low nibble after the result of ALU operation, this bit is set to 1)
Only addressed in 0~0x7F (0~127) is allowed
M.n
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PDK-DS-PFS123-EN_V000-Aug. 26, 2020
PFS123
8bit MTP MCU with 12-bit R-Type ADC
7.1. Data Transfer Instructions
mov
mov
mov
mov
mov
a, I
Move immediate data into ACC.
Example: mov a, 0x0f;
Result: a ← 0fh;
Affected flags: 『N』Z 『N』C 『N』AC 『N』OV
M, a
a, M
Move data from ACC into memory
Example: mov
MEM, a;
Result: MEM ← a
Affected flags: 『N』Z 『N』C 『N』AC 『N』OV
Move data from memory into ACC
Example: mov
a, MEM ;
Result: a ← MEM; Flag Z is set when MEM is zero.
Affected flags: 『Y』Z 『N』C 『N』AC 『N』OV
a, IO
Move data from IO into ACC
Example: mov
a, pa ;
Result: a ← pa; Flag Z is set when pa is zero.
Affected flags: 『Y』Z 『N』C 『N』AC 『N』OV
IO, a
Move data from ACC into IO
Example: mov
Result: pb ← a
pb, a;
Affected flags: 『N』Z 『N』C 『N』AC 『N』OV
Load high byte data in OTP program memory to ACC by using index as OTP address. It needs
2T to execute this instruction.
ldtabh index
Example: ldtabh index;
Result:
a ← {bit 15~8 of OTP [index]};
Affected flags: 『N』Z 『N』C 『N』AC 『N』OV
Application Example:
------------------------------------------------------------------------------------------------------------------------
word
...
ROMptr ;
// declare a pointer of ROM in RAM
mov
mov
mov
mov
...
a, la@TableA ;
lb@ROMptr, a ;
a, ha@TableA ;
// assign pointer to ROM TableA (LSB)
// save pointer to RAM (LSB)
// assign pointer to ROM TableA (MSB)
hb@ROMptr, a ; // save pointer to RAM (MSB)
ldtabh
...
ROMptr ;
dc
// load TableA MSB to ACC (ACC=0X02)
0x0234, 0x0042, 0x0024, 0x0018 ;
TableA :
------------------------------------------------------------------------------------------------------------------------
©Copyright 2020, PADAUK Technology Co. Ltd
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PDK-DS-PFS123-EN_V000-Aug. 26, 2020
PFS123
8bit MTP MCU with 12-bit R-Type ADC
ldtabl index
Load low byte data in OTP to ACC by using index as OTP address. It needs 2T to execute this
instruction.
Example: ldtabl index;
Result:
a ← {bit7~0 of OTP [index]};
Affected flags: 『N』Z 『N』C 『N』AC 『N』OV
Application Example:
------------------------------------------------------------------------------------------------------------------------
word
...
ROMptr ;
// declare a pointer of ROM in RAM
mov
mov
mov
mov
...
a, la@TableA ;
lb@ROMptr, a ;
a, ha@TableA ;
// assign pointer to ROM TableA (LSB)
// save pointer to RAM (LSB)
// assign pointer to ROM TableA (MSB)
hb@ROMptr, a ; // save pointer to RAM (MSB)
ROMptr ; // load TableA LSB to ACC (ACC=0x34)
dc 0x0234, 0x0042, 0x0024, 0x0018 ;
ldtabl
...
TableA :
------------------------------------------------------------------------------------------------------------------------
Move 16-bit counting values in Timer16 to memory in word.
Example: ldt16 word;
ldt16 word
Result:
word ← 16-bit timer
Affected flags: 『N』Z 『N』C 『N』AC 『N』OV
Application Example:
------------------------------------------------------------------------------------------------------------------------
word
…
T16val ;
// declare a RAM word
clear
clear
stt16
…
lb@ T16val ;
hb@ T16val ;
T16val ;
// clear T16val (LSB)
// clear T16val (MSB)
// initial T16 with 0
set1
…
t16m.5 ;
// enable Timer16
set0
ldt16
….
t16m.5 ;
T16val ;
// disable Timer 16
// save the T16 counting value to T16val
------------------------------------------------------------------------------------------------------------------------
©Copyright 2020, PADAUK Technology Co. Ltd
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PDK-DS-PFS123-EN_V000-Aug. 26, 2020
PFS123
8bit MTP MCU with 12-bit R-Type ADC
stt16 word
Store 16-bit data from memory in word to Timer16.
Example: stt16 word;
Result:
16-bit timer ←word
Affected flags: 『N』Z 『N』C 『N』AC 『N』OV
Application Example:
------------------------------------------------------------------------------------------------------------------------
word
…
T16val ;
// declare a RAM word
mov
mov
mov
mov
stt16
…
a, 0x34 ;
lb@ T16val , a ;
a, 0x12 ;
// move 0x34 to T16val (LSB)
hb@ T16val , a ; // move 0x12 to T16val (MSB)
T16val ; // initial T16 with 0x1234
----------------------------------------------------------------------------------------------------------------------
Idxm a, index
Move data from specified memory to ACC by indirect method. It needs 2T to execute this
instruction.
Example: idxm a, index;
Result:
a ← [index], where index is declared by word.
Affected flags: 『N』Z 『N』C 『N』AC 『N』OV
Application Example:
------------------------------------------------------------------------------------------------------------------------
word
…
RAMIndex ;
// declare a RAM pointer
mov
mov
mov
mov
…
a, 0x5B ;
// assign pointer to an address (LSB)
// save pointer to RAM (LSB)
lb@RAMIndex, a ;
a, 0x00 ;
// assign 0x00 to an address (MSB), should be 0
// save pointer to RAM (MSB)
hb@RAMIndex, a ;
idxm
a, RAMIndex ;
// move memory data in address 0x5B to ACC
------------------------------------------------------------------------------------------------------------------------
Idxm index, a Move data from ACC to specified memory by indirect method. It needs 2T to execute this
instruction.
Example: idxm index, a;
Result:
[index] ← a; where index is declared by word.
Affected flags: 『N』Z 『N』C 『N』AC 『N』OV
Application Example:
------------------------------------------------------------------------------------------------------------------------
word
…
RAMIndex ;
// declare a RAM pointer
mov
mov
mov
mov
…
a, 0x5B ;
// assign pointer to an address (LSB)
// save pointer to RAM (LSB)
lb@RAMIndex, a ;
a, 0x00 ;
// assign 0x00 to an address (MSB), should be 0
hb@RAMIndex, a ; // save pointer to RAM (MSB)
mov
idxm
a, 0xA5 ;
RAMIndex, a ;
// mov 0xA5 to memory in address 0x5B
------------------------------------------------------------------------------------------------------------------------
©Copyright 2020, PADAUK Technology Co. Ltd
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PDK-DS-PFS123-EN_V000-Aug. 26, 2020
PFS123
8bit MTP MCU with 12-bit R-Type ADC
xch
M
Exchange data between ACC and memory
Example: xch MEM ;
Result:
MEM ← a , a ← MEM
Affected flags: 『N』Z 『N』C 『N』AC 『N』OV
pushaf
Move the ACC and flag register to memory that address specified in the stack pointer.
Example: pushaf;
Result:
[sp] ← {flag, ACC};
sp ← sp + 2 ;
Affected flags: 『N』Z 『N』C 『N』AC 『N』OV
Application Example:
------------------------------------------------------------------------------------------------------------------------
.romadr 0x10 ;
// ISR entry address
pushaf ;
…
// put ACC and flag into stack memory
// ISR program
…
// ISR program
popaf ;
reti ;
// restore ACC and flag from stack memory
------------------------------------------------------------------------------------------------------------------------
Restore ACC and flag from the memory which address is specified in the stack pointer.
Example: popaf;
popaf
Result:
{Flag, ACC} ← [sp] ;
Affected flags: 『Y』Z 『Y』C 『Y』AC 『Y』OV
sp ← sp - 2
;
©Copyright 2020, PADAUK Technology Co. Ltd
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PDK-DS-PFS123-EN_V000-Aug. 26, 2020
PFS123
8bit MTP MCU with 12-bit R-Type ADC
7.2. Arithmetic Operation Instructions
add
add
add
a, I
Add immediate data with ACC, then put result into ACC
Example: add a, 0x0f ;
Result: a ← a + 0fh
Affected flags: 『Y』Z 『Y』C 『Y』AC 『Y』OV
a, M
M, a
Add data in memory with ACC, then put result into ACC
Example: add
a, MEM ;
Result: a ← a + MEM
Affected flags: 『Y』Z 『Y』C 『Y』AC 『Y』OV
Add data in memory with ACC, then put result into memory
Example: add
MEM, a;
Result: MEM ← a + MEM
Affected flags: 『Y』Z 『Y』C 『Y』AC 『Y』OV
addc a, M
addc M, a
Add data in memory with ACC and carry bit, then put result into ACC
Example: addc
a, MEM ;
Result: a ← a + MEM + C
Affected flags: 『Y』Z 『Y』C 『Y』AC 『Y』OV
Add data in memory with ACC and carry bit, then put result into memory
Example: addc
MEM, a ;
Result: MEM ← a + MEM + C
Affected flags: 『Y』Z 『Y』C 『Y』AC 『Y』OV
addc
addc
a
Add carry with ACC, then put result into ACC
Example: addc
a ;
Result: a ← a + C
Affected flags: 『Y』Z 『Y』C 『Y』AC 『Y』OV
M
Add carry with memory, then put result into memory
Example: addc
MEM ;
Result: MEM ← MEM + C
Affected flags: 『Y』Z 『Y』C 『Y』AC 『Y』OV
nadd a, M
Add negative logic (2’s complement) of ACC with memory
Example: nadd
a, MEM ;
Result: a ← 〒a + MEM
Affected flags: 『Y』Z 『Y』C 『Y』AC 『Y』OV
nadd M, a
Add negative logic (2’s complement) of memory with ACC
Example: nadd
MEM, a ;
Result: MEM ← 〒MEM + a
Affected flags: 『Y』Z 『Y』C 『Y』AC 『Y』OV
sub
sub
a, I
Subtraction immediate data from ACC, then put result into ACC
Example: sub
a, 0x0f;
Result: a ← a - 0fh ( a + [2’s complement of 0fh] )
Affected flags: 『Y』Z 『Y』C 『Y』AC 『Y』OV
a, M
Subtraction data in memory from ACC, then put result into ACC
Example: sub
Result: a ← a - MEM ( a + [2’s complement of M] )
Affected flags: 『Y』Z 『Y』C 『Y』AC 『Y』OV
a, MEM ;
©Copyright 2020, PADAUK Technology Co. Ltd
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PDK-DS-PFS123-EN_V000-Aug. 26, 2020
PFS123
8bit MTP MCU with 12-bit R-Type ADC
sub
M, a
Subtraction data in ACC from memory, then put result into memory
Example: sub
MEM, a;
Result: MEM ← MEM - a ( MEM + [2’s complement of a] )
Affected flags: 『Y』Z 『Y』C 『Y』AC 『Y』OV
subc a, M
subc M, a
Subtraction data in memory and carry from ACC, then put result into ACC
Example: subc
a, MEM;
Result: a ← a – MEM - C
Affected flags: 『Y』Z 『Y』C 『Y』AC 『Y』OV
Subtraction ACC and carry bit from memory, then put result into memory
Example: subc
MEM, a ;
Result: MEM ← MEM – a - C
Affected flags: 『Y』Z 『Y』C 『Y』AC 『Y』OV
subc
subc
a
Subtraction carry from ACC, then put result into ACC
Example: subc
a;
Result: a ← a - C
Affected flags: 『Y』Z 『Y』C 『Y』AC 『Y』OV
M
Subtraction carry from the content of memory, then put result into memory
Example: subc
MEM;
Result: MEM ← MEM - C
Affected flags: 『Y』Z 『Y』C 『Y』AC 『Y』OV
inc
M
Increment the content of memory
Example: inc
MEM ;
Result: MEM ← MEM + 1
Affected flags: 『Y』Z 『Y』C 『Y』AC 『Y』OV
dec
M
Decrement the content of memory
Example: dec
MEM;
Result: MEM ← MEM - 1
Affected flags: 『Y』Z 『Y』C 『Y』AC 『Y』OV
clear
M
Clear the content of memory
Example: clear
Result: MEM ← 0
Affected flags: 『N』Z 『N』C 『N』AC 『N』OV
MEM ;
©Copyright 2020, PADAUK Technology Co. Ltd
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PFS123
8bit MTP MCU with 12-bit R-Type ADC
7.3. Shift Operation Instructions
sr
a
Shift right of ACC, shift 0 to bit 7
Example: sr a ;
Result: a (0,b7,b6,b5,b4,b3,b2,b1) ← a (b7,b6,b5,b4,b3,b2,b1,b0), C ← a(b0)
Affected flags: 『N』Z 『Y』C 『N』AC 『N』OV
src
a
Shift right of ACC with carry bit 7 to flag
Example: src a ;
Result: a (c,b7,b6,b5,b4,b3,b2,b1) ← a (b7,b6,b5,b4,b3,b2,b1,b0), C ← a(b0)
Affected flags: 『N』Z 『Y』C 『N』AC 『N』OV
Shift right the content of memory, shift 0 to bit 7
Example: sr MEM ;
sr
M
Result: MEM(0,b7,b6,b5,b4,b3,b2,b1) ← MEM(b7,b6,b5,b4,b3,b2,b1,b0), C ← MEM(b0)
Affected flags: 『N』Z 『Y』C 『N』AC 『N』OV
Shift right of memory with carry bit 7 to flag
src
sl
M
Example: src MEM ;
Result: MEM(c,b7,b6,b5,b4,b3,b2,b1) ← MEM (b7,b6,b5,b4,b3,b2,b1,b0), C ← MEM(b0)
Affected flags: 『N』Z 『Y』C 『N』AC 『N』OV
a
Shift left of ACC shift 0 to bit 0
Example: sl a ;
Result: a (b6,b5,b4,b3,b2,b1,b0,0) ← a (b7,b6,b5,b4,b3,b2,b1,b0), C ← a (b7)
Affected flags: 『N』Z 『Y』C 『N』AC 『N』OV
Shift left of ACC with carry bit 0 to flag
slc
sl
a
Example: slc a ;
Result: a (b6,b5,b4,b3,b2,b1,b0,c) ← a (b7,b6,b5,b4,b3,b2,b1,b0), C ← a(b7)
Affected flags: 『N』Z 『Y』C 『N』AC 『N』OV
Shift left of memory, shift 0 to bit 0
M
Example: sl MEM ;
Result: MEM (b6,b5,b4,b3,b2,b1,b0,0) ← MEM (b7,b6,b5,b4,b3,b2,b1,b0), C ← MEM(b7)
Affected flags: 『N』Z 『Y』C 『N』AC 『N』OV
Shift left of memory with carry bit 0 to flag
slc
M
Example: slc MEM ;
Result: MEM (b6,b5,b4,b3,b2,b1,b0,C) ← MEM (b7,b6,b5,b4,b3,b2,b1,b0), C ← MEM (b7)
Affected flags: 『N』Z 『Y』C 『N』AC 『N』OV
Swap the high nibble and low nibble of ACC
swap
a
Example: swap
Result: a (b3,b2,b1,b0,b7,b6,b5,b4) ← a (b7,b6,b5,b4,b3,b2,b1,b0)
Affected flags: 『N』Z 『N』C 『N』AC 『N』OV
a ;
©Copyright 2020, PADAUK Technology Co. Ltd
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PFS123
8bit MTP MCU with 12-bit R-Type ADC
7.4. Logic Operation Instructions
and
and
and
or
a, I
a, M
M, a
a, I
Perform logic AND on ACC and immediate data, then put result into ACC
Example: and a, 0x0f ;
Result: a ← a & 0fh
Affected flags: 『Y』Z 『N』C 『N』AC 『N』OV
Perform logic AND on ACC and memory, then put result into ACC
Example: and
a, RAM10 ;
Result: a ← a & RAM10
Affected flags: 『Y』Z 『N』C 『N』AC 『N』OV
Perform logic AND on ACC and memory, then put result into memory
Example: and
MEM, a ;
Result: MEM ← a & MEM
Affected flags: 『Y』Z 『N』C 『N』AC 『N』OV
Perform logic OR on ACC and immediate data, then put result into ACC
Example: or
a, 0x0f ;
Result: a ← a | 0fh
Affected flags: 『Y』Z 『N』C 『N』AC 『N』OV
or
a, M
Perform logic OR on ACC and memory, then put result into ACC
Example: or
a, MEM ;
Result: a ← a | MEM
Affected flags: 『Y』Z 『N』C 『N』AC 『N』OV
or
M, a
a, I
Perform logic OR on ACC and memory, then put result into memory
Example: or
MEM, a ;
Result: MEM ← a | MEM
Affected flags: 『Y』Z 『N』C 『N』AC 『N』OV
xor
xor
Perform logic XOR on ACC and immediate data, then put result into ACC
Example: xor
a, 0x0f ;
Result: a ← a ^ 0fh
Affected flags: 『Y』Z 『N』C 『N』AC 『N』OV
IO, a
Perform logic XOR on ACC and IO register, then put result into IO register
Example: xor
pa, a ;
Result: pa ← a ^ pa ; // pa is the data register of port A
Affected flags: 『N』Z 『N』C 『N』AC 『N』OV
xor
xor
a, M
M, a
Perform logic XOR on ACC and memory, then put result into ACC
Example: xor
a, MEM ;
Result: a ← a ^ RAM10
Affected flags: 『Y』Z 『N』C 『N』AC 『N』OV
Perform logic XOR on ACC and memory, then put result into memory
Example:
xor
MEM, a ;
Result:
MEM ← a ^ MEM
Affected flags: 『Y』Z 『N』C 『N』AC 『N』OV
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8bit MTP MCU with 12-bit R-Type ADC
not
a
Perform 1’s complement (logical complement) of ACC
Example: not a ;
Result: a ← 〜a
Affected flags: 『Y』Z 『N』C 『N』AC 『N』OV
Application Example:
------------------------------------------------------------------------------------------------------------------------
mov
not
a, 0x38 ;
a ;
// ACC=0X38
// ACC=0XC7
------------------------------------------------------------------------------------------------------------------------
Perform 1’s complement (logical complement) of memory
not
M
Example: not
MEM ;
Result: MEM ← 〜MEM
Affected flags: 『Y』Z 『N』C 『N』AC 『N』OV
Application Example:
------------------------------------------------------------------------------------------------------------------------
mov
mov
not
a, 0x38 ;
mem, a ;
mem ;
// mem = 0x38
// mem = 0xC7
------------------------------------------------------------------------------------------------------------------------
Perform 2’s complement of ACC
neg
a
Example: neg
a;
Result: a ← 〒a
Affected flags: 『Y』Z 『N』C 『N』AC 『N』OV
Application Example:
------------------------------------------------------------------------------------------------------------------------
mov
neg
a, 0x38 ;
a ;
// ACC=0X38
// ACC=0XC8
------------------------------------------------------------------------------------------------------------------------
Perform 2’s complement of memory
neg
M
Example: neg
MEM;
Result: MEM ← 〒MEM
Affected flags: 『Y』Z 『N』C 『N』AC 『N』OV
Application Example:
------------------------------------------------------------------------------------------------------------------------
mov
mov
not
a, 0x38 ;
mem, a ;
mem ;
// mem = 0x38
// mem = 0xC8
------------------------------------------------------------------------------------------------------------------------
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8bit MTP MCU with 12-bit R-Type ADC
comp
a, M
Compare ACC with the content of memory
Example: comp a, MEM;
Result: Flag will be changed by regarding as ( a - MEM )
Affected flags: 『Y』Z 『Y』C 『Y』AC 『Y』OV
Application Example:
------------------------------------------------------------------------------------------------------------------------
mov
mov
comp
mov
mov
mov
comp
a, 0x38 ;
mem, a ;
a, mem ;
a, 0x42 ;
mem, a ;
a, 0x38 ;
a, mem ;
// Z flag is set as 1
// C flag is set as 1
------------------------------------------------------------------------------------------------------------------------
Compare ACC with the content of memory
comp
M, a
Example: comp
MEM, a;
Result: Flag will be changed by regarding as ( MEM - a )
Affected flags: 『Y』Z 『Y』C 『Y』AC 『Y』OV
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PFS123
8bit MTP MCU with 12-bit R-Type ADC
7.5. Bit Operation Instructions
set0 IO.n
set1 IO.n
swapc IO.n
Set bit n of IO port to low
Example: set0 pa.5 ;
Result: set bit 5 of port A to low
Affected flags: 『N』Z 『N』C 『N』AC 『N』OV
Set bit n of IO port to high
Example: set1 pb.5 ;
Result: set bit 5 of port B to high
Affected flags: 『N』Z 『N』C 『N』AC 『N』OV
Swap the nth bit of IO port with carry bit
Example: swapc
IO.0;
Result: C ← IO.0 , IO.0 ← C
When IO.0 is a port to output pin, carry C will be sent to IO.0;
When IO.0 is a port from input pin, IO.0 will be sent to carry C;
Affected flags: 『N』Z 『Y』C 『N』AC 『N』OV
Application Example1 (serial output) :
------------------------------------------------------------------------------------------------------------------------
...
set1
...
pac.0 ;
// set PA.0 as output
set0
swapc
set1
swapc
...
flag.1 ;
pa.0 ;
// C=0
// move C to PA.0 (bit operation), PA.0=0
// C=1
flag.1 ;
pa.0 ;
// move C to PA.0 (bit operation), PA.0=1
------------------------------------------------------------------------------------------------------------------------
Application Example2 (serial input) :
------------------------------------------------------------------------------------------------------------------------
...
set0
...
pac.0 ;
// set PA.0 as input
swapc
src
pa.0 ;
a ;
// read PA.0 to C (bit operation)
// shift C to bit 7 of ACC
swapc
src
pa.0 ;
a ;
// read PA.0 to C (bit operation)
// shift new C to bit 7, old C
...
------------------------------------------------------------------------------------------------------------------------
Set bit n of memory to low
set0 M.n
set1 M.n
Example: set0 MEM.5 ;
Result: set bit 5 of MEM to low
Affected flags: 『N』Z 『N』C 『N』AC 『N』OV
Set bit n of memory to high
Example: set1 MEM.5 ;
Result: set bit 5 of MEM to high
Affected flags: 『N』Z 『N』C 『N』AC 『N』OV
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PFS123
8bit MTP MCU with 12-bit R-Type ADC
7.6. Conditional Operation Instructions
ceqsn a, I
Compare ACC with immediate data and skip next instruction if both are equal.
Flag will be changed like as (a ← a – I)
Example: ceqsn
a, 0x55 ;
MEM ;
error ;
inc
goto
Result: If a=0x55, then “goto error”; otherwise, “inc MEM”.
Affected flags: 『Y』Z 『Y』C 『Y』AC 『Y』OV
Compare ACC with memory and skip next instruction if both are equal.
Flag will be changed like as (a ← a - M)
ceqsn a, M
Example: ceqsn
a, MEM;
Result: If a=MEM, skip next instruction
Affected flags: 『Y』Z 『Y』C 『Y』AC 『Y』OV
cneqsn a, M
Compare ACC with memory and skip next instruction if both are not equal.
Flag will be changed like as (a ← a - M)
Example: cneqsn
a, MEM;
Result: If a≠MEM, skip next instruction
Affected flags: 『Y』Z 『Y』C 『Y』AC 『Y』OV
cneqsn a, I
Compare ACC with immediate data and skip next instruction if both are no equal.
Flag will be changed like as (a ← a - I)
Example: cneqsn
a,0x55 ;
MEM ;
error ;
inc
goto
Result: If a≠0x55, then “goto error”; Otherwise, “inc MEM”.
Affected flags: 『Y』Z 『Y』C 『Y』AC 『Y』OV
Check IO bit and skip next instruction if it’s low
t0sn IO.n
t1sn IO.n
t0sn M.n
t1sn M.n
Example: t0sn
pa.5;
Result: If bit 5 of port A is low, skip next instruction
Affected flags: 『N』Z 『N』C 『N』AC 『N』OV
Check IO bit and skip next instruction if it’s high
Example: t1sn
pa.5 ;
Result: If bit 5 of port A is high, skip next instruction
Affected flags: 『N』Z 『N』C 『N』AC 『N』OV
Check memory bit and skip next instruction if it’s low
Example: t0sn MEM.5 ;
Result: If bit 5 of MEM is low, then skip next instruction
Affected flags: 『N』Z 『N』C 『N』AC 『N』OV
Check memory bit and skip next instruction if it’s high
EX: t1sn MEM.5 ;
Result: If bit 5 of MEM is high, then skip next instruction
Affected flags: 『N』Z 『N』C 『N』AC 『N』OV
Increment ACC and skip next instruction if ACC is zero
izsn
a
Example: izsn
Result:
a;
a
←
a + 1,skip next instruction if a = 0
Affected flags: 『Y』Z 『Y』C 『Y』AC 『Y』OV
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8bit MTP MCU with 12-bit R-Type ADC
dzsn
izsn
a
Decrement ACC and skip next instruction if ACC is zero
Example: dzsn
Result:
a;
A
←
A - 1,skip next instruction if a = 0
Affected flags: 『Y』Z 『Y』C 『Y』AC 『Y』OV
M
Increment memory and skip next instruction if memory is zero
Example: izsn
Result: MEM
MEM;
MEM + 1, skip next instruction if MEM= 0
←
Affected flags: 『Y』Z 『Y』C 『Y』AC 『Y』OV
dzsn
M
Decrement memory and skip next instruction if memory is zero
Example: dzsn
Result: MEM
Affected flags: 『Y』Z 『Y』C 『Y』AC 『Y』OV
MEM;
←
MEM - 1, skip next instruction if MEM = 0
7.7. System control Instructions
call
label
Function call, address can be full range address space
Example: call
function1;
pc + 1
Result: [sp]
←
pc
sp
←
←
function1
sp + 2
Affected flags: 『N』Z 『N』C 『N』AC 『N』OV
goto label
Go to specific address which can be full range address space
Example: goto
error;
Result: Go to error and execute program.
Affected flags: 『N』Z 『N』C 『N』AC 『N』OV
Place immediate data to ACC, then return
Example: ret 0x55;
ret
I
Result:
A ← 55h
ret ;
Affected flags: 『N』Z 『N』C 『N』AC 『N』OV
Return to program which had function call
Example: ret;
ret
Result:
sp ← sp - 2
pc ← [sp]
Affected flags: 『N』Z 『N』C 『N』AC 『N』OV
Return to program that is interrupt service routine. After this command is executed, global
interrupt is enabled automatically.
reti
nop
Example: reti;
Affected flags: 『N』Z 『N』C 『N』AC 『N』OV
No operation
Example: nop;
Result: nothing changed
Affected flags: 『N』Z 『N』C 『N』AC 『N』OV
Reset Watchdog timer.
wdreset
Example: wdreset ;
Result: Reset Watchdog timer.
Affected flags: 『N』Z 『N』C 『N』AC 『N』OV
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8bit MTP MCU with 12-bit R-Type ADC
pcadd
a
Next program counter is current program counter plus ACC.
Example: pcadd a;
Result: pc ← pc + a
Affected flags: 『N』Z 『N』C 『N』AC 『N』OV
Application Example:
------------------------------------------------------------------------------------------------------------------------
…
mov
pcadd
goto
goto
goto
goto
…
a, 0x02 ;
a ;
// PC <- PC+2
// jump here
err1 ;
correct ;
err2 ;
err3 ;
correct:
// jump here
…
------------------------------------------------------------------------------------------------------------------------
Enable global interrupt enable
engint
Example: engint;
Result: Interrupt request can be sent to CPU
Affected flags: 『N』Z 『N』C 『N』AC 『N』OV
Disable global interrupt enable
disgint
stopsys
stopexe
Example: disgint ;
Result: Interrupt request is blocked from CPU
Affected flags: 『N』Z 『N』C 『N』AC 『N』OV
System halt.
Example: stopsys;
Result: Stop the system clocks and halt the system
Affected flags: 『N』Z 『N』C 『N』AC 『N』OV
CPU halt. The oscillator module is still active to output clock, however, system clock is disabled
to save power.
Example: stopexe;
Result: Stop the system clocks and keep oscillator modules active.
Affected flags: 『N』Z 『N』C 『N』AC 『N』OV
Reset the whole chip, its operation will be same as hardware reset.
Example: reset;
reset
Result: Reset the whole chip.
Affected flags: 『N』Z 『N』C 『N』AC 『N』OV
7.8. Summary of Instructions Execution Cycle
goto, call, idxm, pcadd, ret, reti, ldtabl, ldtabh
2T
2T
1T
1T
Condition is fulfilled.
ceqsn, cneqsn,t0sn, t1sn, dzsn, izsn
Condition is not fulfilled.
Others
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PFS123
8bit MTP MCU with 12-bit R-Type ADC
7.9. Summary of affected flags by Instructions
Instruction
mov a, I
Z
-
C
-
AC OV Instruction
Z
-
C
-
AC OV Instruction
Z
Y
-
C
-
AC OV
-
-
-
-
mov M, a
mov IO, a
idxm a, index
pushaf
-
-
-
-
mov a, M
ldt16 word
idxm index, a
popaf
-
-
-
-
mov a, IO
stt16 word
Y
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
xch
M
-
-
-
-
-
-
-
-
Y
Y
Y
Y
Y
Y
Y
-
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
-
Y
Y
Y
Y
Y
Y
Y
-
Y
Y
Y
Y
Y
Y
Y
-
add a, I
Y
Y
Y
Y
Y
Y
-
Y
Y
Y
Y
Y
Y
-
Y
Y
Y
Y
Y
Y
-
Y
Y
Y
Y
Y
Y
-
add a, M
addc M, a
nadd a, M
sub a, M
subc M, a
Y
Y
Y
Y
Y
Y
-
Y
Y
Y
Y
Y
Y
Y
Y
Y
-
Y
Y
Y
Y
Y
Y
-
Y
Y
Y
Y
Y
Y
-
add M, a
addc a, M
addc
a
addc
M
nadd M, a
sub a, I
sub M, a
subc a, M
subc
dec
src
a
subc
clear
M
M
inc
sr a
src
sl
M
M
a
sr
M
-
Y
Y
-
-
M
-
-
-
sl
a
-
-
-
slc
a
-
-
-
-
-
-
-
M
-
-
-
slc
and
M
-
-
-
swap
and
a
-
-
and
a, I
Y
Y
Y
Y
-
-
a, M
Y
Y
-
-
-
M, a
Y
Y
Y
-
or a, I
-
-
-
or a, M
-
-
-
or M, a
-
-
-
xor
xor
a, I
-
-
-
xor
not
IO, a
-
-
-
-
xor
not
a, M
M, a
a
-
-
-
a
Y
-
-
-
M
Y
Y
-
-
-
Y
-
-
Y
-
neg
Y
Y
-
-
-
-
neg
M
Y
-
-
-
-
-
comp a, M
set1 IO.n
Y
-
comp M, a
set0 M.n
Y
-
Y
-
Y
-
set0 IO.n
set1 M.n
ceqsn a, M
t0sn IO.n
-
-
-
Y
-
-
Y
-
swapc IO.n
cneqsn a,M
-
Y
Y
-
-
ceqsn a, I
cneqsn a, I
Y
Y
Y
Y
Y
Y
Y
Y
Y
-
Y
-
Y
Y
Y
-
-
t1sn IO.n
-
-
t0sn M.n
-
-
-
-
t1sn M.n
-
-
-
-
izsn
a
Y
Y
Y
Y
Y
Y
Y
Y
dzsn
call
a
Y
-
Y
-
Y
-
Y
-
izsn
M
Y
-
Y
-
Y
-
Y
-
dzsn
M
label
goto label
ret
I
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
ret
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
reti
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
nop
pcadd
a
engint
disgint
reset
stopsys
wdreset
stopexe
ldtabl index
ldtabh index
7.10. BIT definition
Bit access of RAM is only available for address from 0x00 to 0x7F.
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8bit MTP MCU with 12-bit R-Type ADC
8. Code Options
Option
Selection
Description
MTP content is protected and program cannot be read back
MTP content is not protected so program can be read back
Select LVR = 4.0V
Enable
Disable
4.0V
Security
3.5V
Select LVR = 3.5V
3.0V
Select LVR = 3.0V
2.7V
Select LVR = 2.7V
LVR
2.5V
Select LVR = 2.5V
2.2V
Select LVR = 2.2V
2.0V
Select LVR = 2.0V
1.8V
Select LVR = 1.8V
Slow
Please refer to tWUP and tSBP in Section 4.1
Please refer to tWUP and tSBP in Section 4.1
INTEN/ INTRQ.Bit0 is from PA.0
INTEN/ INTRQ.Bit0 is from PB.5
INTEN/ INTRQ.Bit1 is from PB.0
INTEN/ INTRQ.Bit1 is from PA.4
PB4 & PB5 Drive/ Sink Current is Normal
PB4 & PB5 Drive/ Sink Current is Strong (ICE does NOT support.)
The comparator will trigger an interrupt on both the rising edge or falling edge
Boot-up_Time
Interrupt Src0
Interrupt Src1
PB4_PB5_Drive
Comparator
Fast
PA.0
PB.5
PB.0
PA.4
Normal
Strong
All_Edge
Rising_Edge The comparator will trigger an interrupt on the rising edge
Falling_Edge The comparator will trigger an interrupt on the falling edge
Edge
Disable
Enable
16MHZ
Comparator does not control all PWM outputs
GPC_PWM
Comparator controls all PWM outputs (ICE does NOT support.)
When Pwmgclk.0= 1, PWMG clock source = IHRC = 16MHZ
When Pwmgclk.0= 1, PWMG clock source = IHRC*2 = 32MHZ
(ICE does NOT support.)
PWM_Source
TMx_Source
32MHZ
16MHZ
When tm2c[7:4]= 0010, TM2 clock source = IHRC = 16MHZ
When tm3c[7:4]= 0010, TM3 clock source = IHRC = 16MHZ
When tm2c[7:4]= 0010, TM2 clock source = IHRC*2 = 32MHZ
When tm3c[7:4]= 0010, TM3 clock source = IHRC*2 = 32MHZ
(ICE does NOT support.)
32MHZ
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8bit MTP MCU with 12-bit R-Type ADC
Option
Selection
Description
When tm2s.7=1, TM2 PWM resolution is 6 Bit
When tm3s.7=1, TM3 PWM resolution is 6 Bit
When tm2s.7=1, TM2 PWM resolution is 7 Bit
When tm3s.7=1, TM3 PWM resolution is 7 Bit
(ICE does NOT support.)
6 Bit
TMx_Bit
7 Bit
9. Special Notes
This chapter is to remind user who use PFS123 series IC in order to avoid frequent errors upon operation.
9.1. Warning
User must read all application notes of the IC by detail before using it. Please download the related application
notes from the following link:
http://www.padauk.com.tw/tw/technical/index.aspx
9.2. Using IC
9.2.1. IO pin usage and setting
(1) IO pin is set to be digital input
When IO is set as digital input, the level of Vih and Vil would changes with the voltage and temperature.
Please follow the minimum value of Vih and the maximum value of Vil.
The value of internal pull high resistor would also changes with the voltage, temperature and pin voltage.
It is not the fixed value.
(2) If IO pin is set to be digital input and enable wake-up function
Configure IO pin as input.
Set corresponding bit to “1” in PXDIER.
If those IO pins of PA that are not used, such as PADIER [1:2], it should be set low in order to prevent
them from leakage.
The function of PCDIER register of PFS123 series IC is different from the ICE. Detail settings please
refer to Section 9.3.
(3) PA5 is set to be output pin
PA5 can be set to be Open-Drain output pin only, output high requires adding pull-high resistor.
(4) PA5 is set to be PRSTB input pin
Configure PA5 as input.
Set CLKMD.0=1 to enable PA5 as PRSTB input pin.
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8bit MTP MCU with 12-bit R-Type ADC
(5) PA5 is set to be input pin and to connect with a push button or a switch by a long wire
Needs to put a >10Ω resistor in between PA5 and the long wire.
Avoid using PA5 as input in such application.
(6) PA7 and PA6 as external crystal oscillator
Configure PA7 and PA6 as input
Disable PA7 and PA6 internal pull-up resistor
Configure PADIER register to set PA6 and PA7 as analog input
EOSCR register bit [6:5] selects corresponding crystal oscillator frequency :
01 : for lower frequency, ex : 32KHz
10 : for middle frequency, ex : 455KHz, 1MHz
11 : for higher frequency, ex : 4MHz
Program EOSCR.7 =1 to enable crystal oscillator
Ensure EOSC working well before switching from IHRC or ILRC to EOSC
Note: Please read the PMC-APN013 carefully. According to PMC-APN013,, the crystal oscillator should be
used reasonably. If the following situations happen to cause IC start-up slowly or non-startup, PADAUK
Technology is not responsible for this: the quality of the user's crystal oscillator is not good, the usage
conditions are unreasonable, the PCB cleaner leakage current, or the PCB layouts are unreasonable.
9.2.2. Interrupt
(1) When using the interrupt function, the procedure should be:
Step1: Set INTEN register, enable the interrupt control bit
Step2: Clear INTRQ register
Step3: In the main program, using ENGINT to enable CPU interrupt function
Step4: Wait for interrupt. When interrupt occurs, enter to Interrupt Service Routine
Step5: After the Interrupt Service Routine being executed, return to the main program
* Use DISGINT in the main program to disable all interrupts
* When interrupt service routine starts, use PUSHAF instruction to save ALU and FLAG
register. POPAF instruction is to restore ALU and FLAG register before RETI as below:
void Interrupt (void)
{
// Once the interrupt occurs, jump to interrupt service routine
// enter DISGINT status automatically, no more interrupt is
accepted
PUSHAF;
…
POPAF;
}
// RETI will be added automatically. After RETI being executed, ENGINT status
will be restored
(2) INTEN and INTRQ have no initial values. Please set required value before enabling interrupt function.
(3) There are two sets of external IO pin interrupt source. Every set is decided by code option Interrupt Src0
and Interrupt Src1 corresponding to the unique interrupt pin. Please comply with the inten / intrq / integs
register when selecting IO pin.
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PFS123
8bit MTP MCU with 12-bit R-Type ADC
9.2.3. System clock switching
System clock can be switched by CLKMD register. Please notice that, NEVER switch the system clock and
turn off the original clock source at the same time. For example: When switching from clock A to clock B,
please switch to clock B first; and after that turn off the clock A oscillator through CLKMD.
Example : Switch system clock from ILRC to IHRC/2
CLKMD
=
0x36;
0;
// switch to IHRC, ILRC can not be disabled here
// ILRC can be disabled at this time
CLKMD.2 =
ERROR: Switch ILRC to IHRC and turn off ILRC simultaneously
CLKMD 0x50; // MCU will hang
=
9.2.4. Watchdog
Watchdog will be inactive once ILRC is disabled.
9.2.5. TIMER time out
When select $ INTEGS BIT_R (default value) and T16M counter BIT8 to generate interrupt, if T16M counts
from 0, the first interrupt will occur when the counter reaches to 0x100 (BIT8 from 0 to 1) and the second
interrupt will occur when the counter reaches 0x300 (BIT8 from 0 to 1). Therefore, selecting BIT8 as 1 to
generate interrupt means that the interrupt occurs every 512 counts. Please notice that if T16M counter is
restarted, the next interrupt will occur once Bit8 turns from 0 to 1.
If select $ INTEGS BIT_F(BIT triggers from 1 to 0) and T16M counter BIT8 to generate interrupt, the T16M
counter changes to an interrupt every 0x200/0x400/0x600/. Please pay attention to two differences with setting
INTEGS methods.
9.2.6. IHRC
(1) The IHRC frequency calibration is performed when IC is programmed by the writer.
(2) Because the characteristic of the Epoxy Molding Compound (EMC) would some degrees affects the
IHRC frequency (either for package or COB), if the calibration is done before molding process, the actual
IHRC frequency after molding may be deviated or becomes out of spec. Normally , the frequency is
getting slower a bit.
(3) It usually happens in COB package or Quick Turnover Programming (QTP). And PADAUK would not
take any responsibility for this situation.
(4) Users can make some compensatory adjustments according to their own experiences. For example,
users can set IHRC frequency to be 0.5% ~ 1% higher and aim to get better re-targeting after molding.
9.2.7. LVR
User can set MISC.2 as “1” to disable LVR. However, VDD must be kept as exceeding the lowest working
voltage of chip; Otherwise IC may work abnormally.
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PFS123
8bit MTP MCU with 12-bit R-Type ADC
9.2.8. Programming Writing
Please use PDK5S-P-003 to program. PDK3S-P-002 or older versions do not support programming PFS123.
Jumper connection: Please follow the instruction inside the writer software to connect the jumper.
Please select the following program mode according to the actual situation.
Normal Programming Mode
Range of application:
Single-Chip-Package IC with programming at the writer IC socket or on the handler.
Multi-Chip-Package(MCP) with PFS123. Be sure its connected IC and devices will not be damaged by
the following voltages, and will not clam the following voltages.
The voltage conditions in normal programming mode:
(1) VDD is 7.5V, and the maximum supply current is up to about 20mA.
(2) PA5 is 8.0V.
(3) The voltages of other program pins (except GND) are the same as VDD.
Important Cautions:
You MUST follow the instructions on APN004 and APN011 for programming IC on the handler.
Connecting a 0.01uF capacitor between VDD and GND at the handler port to the IC is always good
for suppressing disturbance. But please DO NOT connect with >0.01uF capacitor, otherwise,
programming mode may be fail.
Limited-Voltage Programming Mode
Range of application:
On-Board writing. Its peripheral circuits and devices will not be damaged by the following voltages, and
will not clam the following voltages. Please refer to On-Board Writing for more details.
Multi-Chip-Package(MCP) with PFS123. Please be sure that its connected IC and devices will not be
damaged by the following voltages, and will not clam the following voltages.
The voltage conditions in Limited-Voltage programming mode:
(1) VDD is 5.0V, and the maximum supply current is up to about 20mA.
(2) PA5 is 8.0V.
(3) The voltage of other program pins (except GND) is the same as VDD.
Please select "MTP On-Board VDD Limitation" or "On-Board Program" on the writer screen to enable the
limited-voltage programming mode. (Please refer to the file of Writer “PDK5S-P-003 UM”).
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PFS123
8bit MTP MCU with 12-bit R-Type ADC
On-board Writing
PFS123 can support On-board writing. On-Board Writing is known as the situation that the IC has to be
programmed when the IC itself and other peripheral circuits and devices have already been mounted on the
PCB. Five wires of PDK5S-P-003 are used for On-Board Writing: ICPCK, ICPDA, VDD, GND and ICVPP. They
are used to connect PA3, PA6, VDD, GND and PA5 of the IC correspondingly.
The above figure shows the connection for PFS123 on-board writing. In this figure, ☆can be either resistors
or capacitors. They are used to isolate the programming signal wires from the peripheral circuit. it should
be≧10KΩfor resistance while ≦220pF for capacitance.
Notice:
In general, the limited-voltage programming mode is used in On-board Writing, Please refers to the 13.2
for more detail about limited-voltage programming mode.
Any zener diode ≦5.0V, or any circuitry which clam the 5.0V to be created SHOULD NOT be
connected between VDD and GND of the PCB.
Any capacitor ≧500uF SHOULD NOT be connected between VDD and GND of the PCB.
In general, the writing signal pins PA3, PA5 and PA6 SHOULD NOT be considered as strong output
pins.
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PFS123
8bit MTP MCU with 12-bit R-Type ADC
9.3. Using ICE
(1) PDK5S-I-S01/2(B) supports PFS123 MCU emulation, the following items should be noted when using
PDK5S-I-S01/2(B) to emulate PFS123:
PDK5S-I-S01/2(B) doesn’t support the instruction NMOV/SWAP/NADD/COMP with RAM.
PDK5S-I-S01/2(B) doesn’t support SYSCLK=ILRC/16.
PDK5S-I-S01/2(B) doesn’t support the dynamic setting of function misc.4 (Only fix to 0 or 1)
PDK5S-I-S01/2(B) doesn’t support the function Tm2.gpcrs/Tm3.gpcrs.
PDK5S-I-S01/2(B) doesn’t support band-gap reference voltage for ADC channel F of ADCRGC [3:2].
Only 1.2V exists and is fixed.
PDK5S-I-S01/2(B) doesn’t support the code options: PB4_PB5_Drive, GPC_PWM, TMx_source,
PWM_Source and TMx_bit.
PDK5S-I-S01/2(B) doesn’t support SuLED PWM generation and related registers.
PDK5S-I-S01/2(B) doesn’t support VDD/2 function of PB0.
PDK5S-I-S01/2(B) has different setting of PC2 and PC1 in adcc.
PDK5S-I-S01/2(B) only supports 240 bytes RAM for data memory.
The PCDIER register of the PDK5S-I-S01/2(B) emulator is different from the real chip. The PCDIER[0]
of the PDK5S-I-S01/2(B) is used to set PC0~PC3 to be digital input whereas PCDIER[1] is used to
set PC4~ PC7 to be digital input. It is recommended not to set PCDIER.
When using PB1 in ADCRGC, PA1 must float.
When using GPCC output, PA3 will be influenced.
When simulating PWM waveform, please check the waveform during program running. When the ICE
is suspended or single-step running, its waveform may be inconsistent with the reality.
The ILRC frequency of the PDK5S-I-S01/2(B) simulator is different from the actual IC and is
uncalibrated, with a frequency range of about 34K~38KHz.
Fast Wakeup time is different from PDK5S-I-S01/2(B): 128 SysClk, PFS123: 45 ILRC
Watch dog time out period is different from PDK5S-I-S01/2(B):
WDT period
misc[1:0]=00
misc[1:0]=01
misc[1:0]=10
misc[1:0]=11
PDK5S-I-S01/2(B)
2048 * TILRC
PFS123
8192 * TILRC
16384 * TILRC
65536 * TILRC
262144 * TILRC
4096 * TILRC
16384 * TILRC
256 * TILRC
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