PMC156-S16_技术文档

PMC156/PMS156 Series

8bit OTP Type IO Controller

Data Sheet

Version 1.06 –Dec. 12, 2018

6F-6, No.1, Sec. 3, Gongdao 5th Rd., Hsinchu City 30069, Taiwan, R.O.C.

TEL: 886-3-572-8688  www.padauk.com.tw

PMC156/PMS156 Series

8bit OTP Type IO Controller

IMPORTANT NOTICE

PADAUK Technology reserves the right to make changes to its products or to terminate

production of its products at any time without notice. Customers are strongly

recommended to contact PADAUK Technology for the latest information and verify

whether the information is correct and complete before placing orders.

PADAUK Technology products are not warranted to be suitable for use in life-support

applications or other critical applications. PADAUK Technology assumes no liability for

such applications. Critical applications include, but are not limited to, those that may

involve potential risks of death, personal injury, fire or severe property damage.

PADAUK Technology assumes no responsibility for any issue caused by a customer’s

product design. Customers should design and verify their products within the ranges

guaranteed by PADAUK Technology. In order to minimize the risks in customers’ products,

customers should design a product with adequate operating safeguards.

Page 2 of 71

PDK-DS-PMX156-EN_V106 – Dec. 12, 2018

PMC156/PMS156 Series

8bit OTP Type IO Controller

Table of Contents

1. Features...............................................................................................................................7

1.1.

1.2.

1.3.

1.4.

Special Features...................................................................................................................7

System Features...................................................................................................................7

CPU Features .......................................................................................................................7

Package Information .............................................................................................................8

2. General Description and Block Diagram ..........................................................................9

3. Pin Assignment and Functional Description..................................................................10

4. Device Characteristics .....................................................................................................15

4.1.

4.2.

4.3.

4.4.

4.5.

4.6.

4.7.

4.8.

4.9.

DC/AC Characteristics ........................................................................................................15

Absolute Maximum Ratings.................................................................................................16

Typical IHRC Frequency vs. VDD (calibrated to 16MHz).....................................................17

Typical ILRC Frequency vs. VDD........................................................................................17

Typical IHRC Frequency vs. Temperature (calibrated to 16MHz)........................................18

Typical ILRC Frequency vs. Temperature...........................................................................18

Typical Operating Current vs. VDD and CLK=IHRC/n.........................................................19

Typical Operating Current vs. VDD and CLK=ILRC/n..........................................................19

Typical Lowest Operating Current vs. VDD and CLK=ILRC/n .............................................20

4.10. Typical operating current vs. VDD @ system clock = 4MHz EOSC / n................................20

4.11. Typical operating current vs. VDD @ system clock = 32kHz EOSC / n ...............................21

4.12. Typical IO pull high resistance.............................................................................................21

4.13. Typical IO driving current (I_OH) and sink current (I_OL) ...........................................................22

4.14. Typical IO input high / low threshold voltage (V_IH/V_IL) ..........................................................22

4.15. Typical VDD/2 Bias output voltage......................................................................................23

4.16. Typical power down current (I_PD) and power save current (I_PS)............................................24

5. Functional Description.....................................................................................................25

5.1.

5.2.

Program Memory – OTP .....................................................................................................25

Boot Up...............................................................................................................................25

5.2.1

Timing charts for reset conditions ....................................................................26

5.3.

5.4.

Data Memory – SRAM ........................................................................................................27

Oscillator and clock.............................................................................................................27

5.4.1. Internal High RC oscillator and Internal Low RC oscillator........................................27

5.4.2. IHRC calibration .......................................................................................................27

5.4.3. IHRC Frequency Calibration and System Clock .......................................................28

5.4.4. External Crystal Oscillator ........................................................................................29

5.4.5. System Clock and LVR levels...................................................................................31

5.4.6. System Clock Switching ...........................................................................................32

5.5

5.6

5.7

16-bit Timer (Timer16) ........................................................................................................33

Watchdog Timer..................................................................................................................35

Interrupt ..............................................................................................................................35

Page 3 of 71

PDK-DS-PMX156-EN_V106 – Dec. 12, 2018

PMC156/PMS156 Series

8bit OTP Type IO Controller

5.8

5.9

Power-Save and Power-Down ............................................................................................38

5.8.1. Power-Save mode (“stopexe”)..................................................................................38

5.8.2. Power-Down mode (“stopsys”) .................................................................................39

5.8.3. Wake-up...................................................................................................................40

IO Pins................................................................................................................................42

5.10 Reset and LVR....................................................................................................................43

5.10.1. Reset......................................................................................................................43

5.10.2. LVR reset ...............................................................................................................43

5.10.3. Notice for LVR reset ...............................................................................................43

5.11 LCD Bias Voltage Generator...............................................................................................45

6. IO Registers.......................................................................................................................46

6.1

6.2

6.3

6.4

6.5

6.6

6.7

6.8

6.9

ACC Status Flag Register (flag), IO address = 0x00 ...........................................................46

Stack Pointer Register (sp), IO address = 0x02...................................................................46

Clock Mode Register (clkmd), IO address = 0x03 ...............................................................46

Interrupt Enable Register (inten), IO address = 0x04...........................................................46

Interrupt Request Register (intrq), IO address = 0x05 .........................................................47

Timer 16 mode Register (t16m), IO address = 0x06............................................................47

External Oscillator setting Register (eoscr, write only), IO address = 0x0a..........................47

IHRC oscillator control Register (ihrcr, write only), IO address = 0x0b ................................48

Interrupt Edge Select Register (integs), IO address = 0x0c.................................................48

6.10 Port A Digital Input Enable Register (padier), IO address = 0x0d........................................49

6.11 Port B Digital Input Enable Register (pbdier), IO address = 0x0e........................................50

6.12 Port A Data Registers (pa), IO address = 0x10 ...................................................................51

6.13 Port A Control Registers (pac), IO address = 0x11..............................................................51

6.14 Port A Pull-High Registers (paph), IO address = 0x12.........................................................51

6.15 Port B Data Registers (pb), IO address = 0x14 ...................................................................51

6.16 Port B Control Registers (pbc), IO address = 0x15..............................................................51

6.17 Port B Pull-High Registers (pbph), IO address = 0x16.........................................................51

6.18 MISC Register (misc), IO address = 0x3b ...........................................................................52

7. Instructions.......................................................................................................................53

7.1

7.2

7.3

7.4

7.5

7.6

7.7

7.8

7.9

Data Transfer Instructions...................................................................................................54

Arithmetic Operation Instructions ........................................................................................56

Shift Operation Instructions.................................................................................................58

Logic Operation Instructions................................................................................................59

Bit Operation Instructions....................................................................................................61

Conditional Operation Instructions ......................................................................................61

System control Instructions .................................................................................................62

Summary of Instructions Execution Cycle ...........................................................................64

Summary of affected flags by Instructions...........................................................................65

7.10 BIT definition.......................................................................................................................65

8. Code Options ....................................................................................................................66

9. Special Notes....................................................................................................................67

9.1. Warning ...................................................................................................................................67

Page 4 of 71

PDK-DS-PMX156-EN_V106 – Dec. 12, 2018

PMC156/PMS156 Series

8bit OTP Type IO Controller

9.2

. Using IC............................................................................................................................67

9.2.1.

9.2.2.

9.2.3.

9.2.4.

9.2.5.

9.2.6.

9.2.7.

9.2.8.

9.2.9.

IO pin usage and setting..................................................................................67

Interrupt ...........................................................................................................68

System clock switching....................................................................................68

Power down mode, wakeup and watchdog ......................................................69

TIMER time out................................................................................................69

LVR .................................................................................................................70

IHRC................................................................................................................70

LCD COM pin application.................................................................................70

Program writing................................................................................................71

9.3. Using ICE ................................................................................................................................71

Page 5 of 71

PDK-DS-PMX156-EN_V106 – Dec. 12, 2018

PMC156/PMS156 Series

8bit OTP Type IO Controller

Revision History:

Revision

0.01

Date

Description

2013/12/10 1^stversion

0.02

2014/02/10 Add section 5.10.3 Notice for LVR reset ,Add chapter 8 Special Notes

2014/12/22 Amend PMS156 operating temperature to -40°C ~ 85°C

0.03

0.04

2015/06/16

Amend PMS156 operating temperature to -20°C ~ 70°C

1. Add section 5.8.3: the description of wake-up

2. Add section 8.3 Warning

0.05

2016/07/07

1. Add company address & Tel No.

2. Amend Section 1.1, 1.2, 1.3

3. Add Section 1.4: Package Information

4. Add Chapter 3 Pin Assignment and Description: PMC156-S08,PMC156-D08,

PMS156-S08, PMS156-D08

5. Amend Section 4.1 DC/AC Characteristics

6. Amend Section 4.3 to 4.14

7. Add 4.16:Typical power down current (I_PD) and power save current (I_PS)

8. Add Section 5.2.1 Timing charts for reset conditions

9. Amend Table2: Three Oscillator Circuits provided by PMC156/PMS156

10. Amend Section 5.4.1, 5.4.3, 5.4.4, 5.4.5

11. Amend Section 5.5 16-bit Timer

1.06

2018/12/12

12. Amend Section 5.7 Interrupt

13. Amend Section 5.8.1, 5.8.2, 5.8.3

14. Amend Section 5.10.2, 5.10.3

15. Amend Section 5.11 LCD Bias Voltage Generator

16. Amend Section 6.6, 6.10, 6.11, 6.18

17. Delete the Symbol “pc0” in Chapter 7

18. Amend Section 7.8 Summary of Instructions Execution Cycle and delete 8.1.7

19. Move Section 8.1.8 BIT definition to Section 7.10

20. Add Chapter 8 Code Options

21. Move Section 8.3 to Section 9.1 and updated the link

22. Amend Section 9.2.1, 9.2.5, 9.2.9

23. Add Section 9.2.7 IHRC

24. Amend Section 9.3 Using ICE

Page 6 of 71

PDK-DS-PMX156-EN_V106 – Dec. 12, 2018

PMC156/PMS156 Series

8bit OTP Type IO Controller

1. Features

1.1. Special Features



PMC156 series:



High EFT series

Operating temperature range: -40°C ~ 85°C



PMS156 series:



General purpose series

Not supposed to use in AC RC step-down powered or high EFT requirement applications.

PADAUK assumes no liability if such kind of applications can not pass the safety regulation tests.

Operating temperature range: -20°C ~ 70°C



1.2. System Features



1KW OTP program memory

64 Bytes data RAM

One hardware 16-bit timer

Support fast wake-up

16 IO pins with 10mA capability and optional pull-high resistor

Every IO pin can be configured to enable wake-up function

Band-gap circuit to provide 1.20V reference voltage

Built-in half VDD bias voltage generator for LCD application

Built-in Internal High RC Oscillator (IHRC)

Operating frequency range:

DC ~ 8MHz@V_DD≧3.3V; DC ~ 4MHz@V_DD≧2.5V; DC ~ 2MHz@V_DD≧2.2V

Operating voltage range: 2.2V ~ 5.5V

Low power consumption



I

_operating~ 1.7mA@1MIPS, V_DD=5.0V

_powerdown~ 1uA@V_DD=5.0V

I_operating~ 8uA@ILRC=21kHz, V_DD=3.3V

I_powerdown~ 0.5uA@V_DD=3.3V

I



Clock sources: External crystal oscillator, internal high RC oscillator and internal low RC oscillator

Eight levels of LVR reset : 4.1V, 3.6V, 3.1V, 2.8V, 2.5V, 2.2V, 2.0V, 1.8V

Two external interrupt pins

1.3. CPU Features



One processing unit operating mode

79 Powerful instructions

Most instructions are 1T execution cycle

Programmable stack pointer and adjustable stack level

Direct and indirect addressing modes for data access. Data memories are available for use as an index pointer

of Indirect addressing mode



IO space and memory space are independent

Page 7 of 71

PDK-DS-PMX156-EN_V106 – Dec. 12, 2018

PMC156/PMS156 Series

8bit OTP Type IO Controller

1.4. Package Information

 PMC156 Series



PMC156-S20: SOP20 (300mil);

PMC156-S18: SOP18 (300mil);

PMC156-D18: DIP18 (300mil);

PMC156-S16: SOP16 (150mil);

PMC156-S14: SOP14 (150mil);

PMC156-S08: SOP8 (150ml);

PMC156-D08: DIP8 (300mil)

 PMS156 Series



PMS156-S20: SOP20 (300mil);

PMS156-S18: SOP18 (300mil);

PMS156-D18: DIP18 (300mil);

PMS156-S16: SOP16 (150mil);

PMS156-S14: SOP14 (150mil);

PMS156-S08: SOP8 (150ml);

PMS156-D08: DIP8 (300mil)

Page 8 of 71

PDK-DS-PMX156-EN_V106 – Dec. 12, 2018

PMC156/PMS156 Series

8bit OTP Type IO Controller

2. General Description and Block Diagram

The PMC156/PMS156 is an IO-Type, OTP-based CMOS 8-bit microcontroller. The PMC156/PMS156 employs

RISC architecture and most the instructions are executed in one cycle except that few instructions are two cycles

that handle indirect memory access. 1KW bits OTP program memory and 64 bytes data SRAM are inside, one

hardware 16-bit timer is also provided in the PMC156/PMS156.

Touch

Controller

Interrupt

Controller

1.5KW

OTP

&

Task

Control

16-bit Timer

IO Ports

CPU

88 bytes

SRAM

Timer2

8-bit Timer

Watchdog

Timer

POR / LVR

Power

management

Page 9 of 71

PDK-DS-PMX156-EN_V106 – Dec. 12, 2018

PMC156/PMS156 Series

8bit OTP Type IO Controller

3. Pin Assignment and Functional Description

PMC156 series

PA2/COM2

PA3/COM3

PA4/COM4

PA5/PRST#

GND

PA2/COM2

PA3/COM3

PA4/COM4

PA5/PRST#

GND

1

2

3

4

5

6

7

8

9

PA1/COM1

PA0/INT0

PA7/X1IN

PA6/XO2 UT

VDD

PA1/COM1

PA0/INT0

PA7/XI1N

PA6/XO2 UT

VDD

1

2

18

17

16

15

14

13

12

11

10

20

19

18

17

16

15

14

13

12

11

3

4

5

PB0/INT1

PB1/COM1A

PB2/COM2A

PB3

GND

6

PB7

VDD

PB0/INT1

PB1/COM1A

PB2/COM2A

PB3

7

PB6/COM4A

PB5/COM3A

PB4

PB7

8

PB6/COM4A

PB5/COM3A

9

PB4

10

PMC156 (SOP18-300mil)

PMC156 (DIP18-300mil)

PMC156 (SOP20-300mil)

PA2/COM2

PA3/COM3

PA4/COM4

PA5/PRST#

GND

1

PA1/COM1

PA0/INT0

PA7/XI1N

PA6/XO2 UT

VDD

PA2/COM2

PA3/COM3

PA4/COM4

PA5/PRST#

GND

1

2

3

4

5

6

7

8

PA1/COM1

PA0/INT0

PA7/XI1N

PA6/XO2 UT

VDD

14

13

12

11

10

9

16

2

3

4

5

6

7

15

14

13

12

11

10

9

PB0/INT1

PB7

PB1/COM1A

PB2/COM2A

8

PB6/COM4A

PB5/COM3A

PMC156 (SOP14-150mil)

PMC156 (SOP16-150mil)

GND

VDD

PA6/X2

1

8

PA5/PRSTB#

PA4/COM4

2

7

6

5

PA7/X1

3

4

PA0/INT0

PA3/COM3

PMC156–S08 (SOP8- 150mil)

PMC156– - 300mil)

D08 (DIP8

Page 10 of 71

PDK-DS-PMX156-EN_V106 – Dec. 12, 2018

PMC156/PMS156 Series

8bit OTP Type IO Controller

PMS156 series

GND

VDD

PA6/X2

8

7

6

5

1

2

PA5/PRST#B

PA4/COM4

PA3/COM3

PA7/X1

3

4

PA0/INT0

PMS156–S08 (SOP8- 150mil)

PMS156– - 300mil)

D08 (DIP8

Page 11 of 71

PDK-DS-PMX156-EN_V106 – Dec. 12, 2018

PMC156/PMS156 Series

8bit OTP Type IO Controller

Pin & Buffer

Type

Pin Name

Description

The functions of this pin can be:

(1) Bit 7 of port A. It can be configured as digital input or two-state output, with

pull-high resistor.

IO

PA7/

X1

ST /

(2) X1 (input) when crystal oscillator is used.

CMOS /

Analog

If this pin is used for crystal oscillator, bit 7 of padier register must be programmed

“0” to avoid leakage current. This pin can be used to wake-up system during sleep

mode; however, wake-up function is also disabled if bit 7 of padier register is “0”.

The functions of this pin can be:

(1) Bit 6 of port A. It can be configured as digital input or two-state output, with

pull-high resistor.

IO

PA6/

X2

ST /

(2) X2 (output) when crystal oscillator is used.

CMOS /

Analog

If this pin is used for crystal oscillator, bit 6 of padier register must be programmed

“0” to avoid leakage current. This pin can be used to wake-up system during sleep

mode; however, wake-up function is also disabled if bit 6 of padier register is “0”.

The functions of this pin can be:

(1) Bit 5 of port A. It can be configured as digital input or open-drain output pin.

Please notice that there is no pull-high resistor in this pin.

(2) Hardware reset.

IO

PA5/

ST /

PRST#

This pin can be used to wake-up system during sleep mode; however, wake-up

function is also disabled if bit 5 of padier register is “0”.

Please put 33Ω resistor in series to have high noise immunity when this pin is in

input mode.

CMOS

The functions of this pin can be:

(1) Bit 4 of port A. It can be configured as digital input or two-state output, with

pull-high resistor.

IO

PA4 /

ST /

(2) COM4 of group 1 for LCD to provide (1/2 VDD) for LCD bias voltage.

(3) Channel 0 input.

COM4

CMOS /

Analog

This pin can be used to wake up system during sleep mode; however, wake-up

function from this pin is also disabled when bit 4 of padier register is “0”

The functions of this pin can be:

IO

(1) Bit 3 of port A. It can be configured as digital input or two-state output, with

pull-high resistor.

PA3 /

ST /

COM3

CMOS /

Analog

(2) COM3 of group 1 for LCD to provide (1/2 VDD) for LCD bias voltage.

This pin can be used to wake up system during sleep mode; however, wake-up

function from this pin is also disabled when bit 3 of padier register is “0”

The functions of this pin can be:

IO

(1) Bit 2 of port A. It can be configured as digital input or two-state output, with

pull-high resistor.

PA2 /

ST /

COM2

CMOS /

Analog

(2) COM2 of group 1 for LCD to provide (1/2 VDD) for LCD bias voltage.

This pin can be used to wake up system during sleep mode; however, wake-up

function from this pin is also disabled when bit 2 of padier register is “0”

Page 12 of 71

PDK-DS-PMX156-EN_V106 – Dec. 12, 2018

PMC156/PMS156 Series

8bit OTP Type IO Controller

Pin Type &

Buffer Type

Pin Name

Description

The functions of this pin can be:

(1) Bit 1 of port A. It can be configured as digital input or two-state output, with

pull-high resistor.

IO

ST /

PA1 /

COM1

(2) COM1 of group 1 for LCD to provide (1/2 VDD) for LCD bias voltage.

This pin can be used to wake up system during sleep mode; however, wake-up

function from this pin is also disabled when bit 1 of padier register is “0”

CMOS / Analog

The functions of this pin can be:

(1) Bit 0 of port A. It can be configured as digital input or two-state output, with

pull-high resistor.

IO

PA0 /

INT0

ST /

(2) External interrupt line 0. Both rising edge and falling edge are accepted to

request interrupt service.

CMOS /

Analog

This pin can be used to wake up system during sleep mode; however, wake-up

function from this pin is also disabled when bit 0 of padier register is “0”.

The functions of this pin can be:

IO

(1) Bit 7 of port B. It can be configured as digital input or two-state output, with

pull-high resistor.

ST /

PB7

CMOS /

Analog

This pin can be used to wake up system during sleep mode; however, wake-up

function from this pin is also disabled when bit 7 of pbdier register is “0”.

The functions of this pin can be:

(1) Bit 6 of port B. It can be configured as digital input or two-state output, with

pull-high resistor.

IO

PB6 /

ST /

COM4A

(2) COM4A of group 2 for LCD to provide (1/2 VDD) for LCD bias voltage.

This pin can be used to wake up system during sleep mode; however, wake-up

function from this pin is also disabled when bit 6 of pbdier register is “0”.

CMOS

The functions of this pin can be:

(1) Bit 5 of port B. It can be configured as digital input or two-state output, with

pull-high resistor.

IO

PB5 /

ST /

COM3A

(2) COM3A of group 2 for LCD to provide (1/2 VDD) for LCD bias voltage.

This pin can be used to wake up system during sleep mode; however, wake-up

function from this pin is also disabled when bit 5 of pbdier register is “0”.

CMOS

The functions of this pin can be:

IO

(1) Bit 4 of port B. It can be configured as digital input or two-state output, with

pull-high resistor.

PB4

PB3

ST /

CMOS

This pin can be used to wake up system during sleep mode; however, wake-up

function from this pin is also disabled when bit 4 of pbdier register is “0”.

The functions of this pin can be bit 4 of port B. It can be configured as digital

input or two-state output, with pull-high resistor. This pin can be used to wake up

system during sleep mode; however, wake-up function from this pin is also

disabled when bit 3 of pbdier register is “0”.

IO

ST /

CMOS

Page 13 of 71

PDK-DS-PMX156-EN_V106 – Dec. 12, 2018

PMC156/PMS156 Series

8bit OTP Type IO Controller

Pin Type &

Buffer Type

Pin Name

Description

The functions of this pin can be:

(1) Bit 2 of port B. It can be configured as digital input or two-state output, with

pull-high resistor.

IO

PB2 /

ST /

COM2A

(2) COM2A of group 2 for LCD to provide (1/2 VDD) for LCD bias voltage.

This pin can be used to wake up system during sleep mode; however, wake-up

function from this pin is also disabled when bit 2 of pbdier register is “0”.

CMOS

The functions of this pin can be:

(1) Bit 1 of port B. It can be configured as digital input or two-state output, with

pull-high resistor.

IO

PB1 /

ST /

COM1A

(2) COM1A of group 2 for LCD to provide (1/2 VDD) for LCD bias voltage..

This pin can be used to wake up system during sleep mode; however, wake-up

function from this pin is also disabled when bit 1 of pbdier register is “0”.

CMOS

The functions of this pin can be:

(1) Bit 0 of port B. It can be configured as digital input or two-state output, with

pull-high resistor.

IO

PB0 /

INT1

ST /

(2) External interrupt line 1. Both rising edge and falling edge are accepted to

request interrupt service.

CMOS

This pin can be used to wake up system during sleep mode; however, wake-up

function from this pin is also disabled when bit 0 of pbdier register is “0”.

VDD

GND

Positive power

Ground

Notes: IO: Input/Output; ST: Schmitt Trigger input; Analog: Analog input pin; CMOS: CMOS voltage level

Page 14 of 71

PDK-DS-PMX156-EN_V106 – Dec. 12, 2018

PMC156/PMS156 Series

8bit OTP Type IO Controller

4. Device Characteristics

4.1. DC/AC Characteristics

All data are acquired under the conditions of V_DD=5.0V, f_SYS=2MHz unless noted.

Symbol

Description

Operating Voltage

Min

Typ

Max

Unit

Conditions

V_DD

2.2

5.0

5.5

V

* Subject to LVR tolerance

Under_20ms_Vdd_ok**= Y/N

System clock* =

IHRC/2

0

8M

4M

2M

V

_DD≧2.5V / V_DD≧3.1V

_DD≧2.2V / V_DD≧2.5V

_DD≧2.2V / V_DD≧2.2V

f_SYS

IHRC/4

Hz

IHRC/8

ILRC

37K

1.7

8

V_DD= 5.0V

mA f_SYS=1MIPS@5.0V

uA f_SYS=ILRC=21kHz@3.3V

uA f_SYS= 0Hz,V_DD=5.0V

uA f_SYS= 0Hz,V_DD=3.3V

V_DD=5.0V;

I_OP

I_PD

Operating Current

Power Down Current

1

0.5

(by stopsys command)

Power Save Current

I_PS

0.4

mA Band-gap, LVR, IHRC, ILRC,

Timer16 modules are ON.

V

(by stopexe command)

V_IL

V_IH

Input low voltage for IO lines

Input high voltage for IO lines

IO lines sink current

0

0.7 V_DD

7

0.3 V_DD

V_DD

13

V

I_OL

10

-7

mA V_DD=5.0V, V_OL=0.5V

mA V_DD=5.0V, V_OH=4.5V

I_OH

IO lines drive current

-5

-9

1

V_DD+0.3≧V_IN≧ -0.3

I_{INJ (PIN)}

Injected current on pin

mA

62

V_DD=5.0V

R_PH

Pull-high Resistance

100

210

KΩ

V

_DD=3.3V

V_DD=2.2V

3.86

3.35

2.84

2.61

2.37

2.04

1.86

1.67

15.84*

4.15

3.60

3.05

2.80

2.55

2.20

2.00

1.80

16*

4.44

3.85

3.26

3.00

2.73

2.35

2.14

1.93

16.16*

V_LVR

V

Low Voltage Reset Voltage *

@25^oC

Frequency of IHRC after

V_DD=2.2V~5.5V,

-40^oC <Ta<85^oC*

-20^oC <Ta<70^oC*

f_IHRC

MHz

calibration *

15.20*

15.28*

16*

16.80*

16.72

Page 15 of 71

PDK-DS-PMX156-EN_V106 – Dec. 12, 2018

PMC156/PMS156 Series

8bit OTP Type IO Controller

Symbol

Description

Min

Typ

37*

21*

Max

Unit

Conditions

V_DD=5.0V, Ta=25^oC

V_DD=5.0V, -40^oC <Ta<85^oC*

V_DD=5.0V, -20^oC <Ta<70^oC*

V_DD=3.3V, Ta=25^oC

31.3*

41.9*

24.0*

25.9*

50.0*

48.1*

f_ILRC

Frequency of ILRC *

KHz

18.3*

24.5*

V_DD=3.3V, -40^oC <Ta<85^oC*

V_DD=3.3V, -20^oC <Ta<70^oC*

V_DD= 5.0V

14.0*

14.7*

29.0*

27.3*

21*

t_INT

Interrupt pulse width

30

ns

V

V_DR

RAM data retention voltage*

1.5

In power-down mode.

2048

4096

misc[1:0]=00 (default)

misc[1:0]=01

ILRC

clock

t_WDT

Watchdog timeout period

period

16384

29

misc[1:0]=10

System boot-up period from

power-on

@V_DD=5V, ILRC~37kHz

@V_DD=3.3V, ILRC~21kHz

t_SBP

ms

48

System wake-up period

Fast wake-up by IO toggle from

STOPEXE suspend

Where T_SYSis the time

period of system clock

128

T_SYS

Fast wake-up by IO toggle from

STOPSYS suspend, IHRC is the

system clock

128 T_SYS

Where T_SIHRCis the stable

time of IHRC from power-on.

t_WUP

+

T_SIHRC

Normal wake-up from

STOPEXE or STOPSYS

suspend

Where T_ILRCis the clock

period of ILRC

1024

T_ILRC

us

t_RST

External reset pulse width

120

@V_DD=5V

*These parameters are for design reference, not tested for every chip.

** Under_20ms_Vdd_Ok is a checking condition for the VDD rising from 0V to the stated voltage within 20ms.

4.2. Absolute Maximum Ratings



Supply Voltage ……………………………......

Input Voltage …………………………………..

Operating Temperature ………………………

2.2V ~ 5.5V

-0.3V ~ V_DD+ 0.3V

PMC156 series:-40°C ~ 85°C ;

PMS156 series:-20°C ~ 70°C

-50°C ~ 125°C



Storage Temperature …………………………

Junction Temperature ………………………

150°C

Page 16 of 71

PDK-DS-PMX156-EN_V106 – Dec. 12, 2018

PMC156/PMS156 Series

8bit OTP Type IO Controller

4.3. Typical IHRC Frequency vs. VDD (calibrated to 16MHz)

4.4. Typical ILRC Frequency vs. VDD

Page 17 of 71

PDK-DS-PMX156-EN_V106 – Dec. 12, 2018

PMC156/PMS156 Series

8bit OTP Type IO Controller

4.5. Typical IHRC Frequency vs. Temperature (calibrated to 16MHz)

* PMS156 series:-20°C ~ 70°C

4.6. Typical ILRC Frequency vs. Temperature

* PMS156 series:-20°C ~ 70°C

Page 18 of 71

PDK-DS-PMX156-EN_V106 – Dec. 12, 2018

PMC156/PMS156 Series

8bit OTP Type IO Controller

4.7. Typical Operating Current vs. VDD and CLK=IHRC/n



Conditions:

ON: Band-gap, LVR, IHRC, T16 modules; OFF: ILRC, EOSC modules;

IO: PA0:0.5Hz output toggle and no loading, others: input and no floating

4.8. Typical Operating Current vs. VDD and CLK=ILRC/n



Conditions:

ON: Band-gap, LVR, ILRC, T16 modules; OFF: IHRC, EOSC modules;

IO: PA0:0.5Hz output toggle and no loading, others: input and no floating

Page 19 of 71

PDK-DS-PMX156-EN_V106 – Dec. 12, 2018

PMC156/PMS156 Series

8bit OTP Type IO Controller

4.9. Typical Lowest Operating Current vs. VDD and CLK=ILRC/n



Conditions:

ON: ILRC, T16 module; OFF: IHRC, EOSC, Band-gap, LVR modules;

IO: PA0:0.5Hz output toggle and no loading, others: input and no floating

4.10.Typical operating current vs. VDD @ system clock = 4MHz EOSC / n



Conditions:

ON: EOSC, MISC.6 = 1;

OFF: Band-gap, LVR, IHRC, ILRC, T16 modules;

IO: PA0:0.5Hz output toggle and no loading, others: input and no floating

Page 20 of 71

PDK-DS-PMX156-EN_V106 – Dec. 12, 2018

PMC156/PMS156 Series

8bit OTP Type IO Controller

4.11.Typical operating current vs. VDD @ system clock = 32kHz EOSC / n



Conditions:

ON: EOSC;

OFF: Band-gap, LVR, IHRC, ILRC, T16 modules;

IO: PA0:0.5Hz output toggle and no loading, others: input and no floating

4.12.Typical IO pull high resistance



Conditions:

ON: EOSC, MISC.6 = 1;

OFF: Band-gap, LVR, IHRC, ILRC, T16 modules;

IO: PA0:0.5Hz output toggle and no loading, others: input and no floating

Page 21 of 71

PDK-DS-PMX156-EN_V106 – Dec. 12, 2018

PMC156/PMS156 Series

8bit OTP Type IO Controller

4.13.Typical IO driving current (I_OH) and sink current (I_OL)



Conditions:

ON: EOSC, MISC.6 = 1;

OFF: Band-gap, LVR, IHRC, ILRC, T16 modules;

IO: PA0:0.5Hz output toggle and no loading, others: input and no floating

4.14.Typical IO input high / low threshold voltage (V_IH/V_IL)

Page 22 of 71

PDK-DS-PMX156-EN_V106 – Dec. 12, 2018

PMC156/PMS156 Series

8bit OTP Type IO Controller

4.15.Typical VDD/2 Bias output voltage

VDD/2 bias Voltage vs. VDD

3

2.5

2

1.5

1

0.5

0

2

2.5

3

3.5

4

4.5

5

5.5

VDD (V)

Page 23 of 71

PDK-DS-PMX156-EN_V106 – Dec. 12, 2018

PMC156/PMS156 Series

8bit OTP Type IO Controller

4.16.Typical power down current (I_PD) and power save current (I_PS)

Page 24 of 71

PDK-DS-PMX156-EN_V106 – Dec. 12, 2018

PMC156/PMS156 Series

8bit OTP Type IO Controller

5. Functional Description

5.1. Program Memory – OTP

The OTP (One Time Programmable) program memory is used to store the program instructions to be executed.

The OTP program memory may contains the data, tables and interrupt entry. After reset, the initial address for

CPU is 0x000. The interrupt entry is 0x010 if used, the last eight addresses are reserved for system using, like

checksum, serial number, etc. The OTP program memory for PMC156/PMS156 is a 1KW that is partitioned as

Table 1. The OTP memory from address 0x3F8 to 0x3FF is for system using, address space from 0x001 to

0x00F and from 0x011 to 0x3F7 are user program spaces.

Address

0x000

0x001

•

Function

Reset – goto instruction

User program

•

0x00F

0x010

0x011

•

User program

Interrupt entry address

User program

•

0x3F7

0x3F8

•

User program

System Using

•

0x3FF

System Using

Table 1: Program Memory Organization of PMC156/PMS156

5.2. Boot Up

POR (Power-On-Reset) is used to reset PMC156/PMS156 when power up, however, the supply voltage may

be not stable. To ensure the stability of supply voltage after power up, it will wait 1024 ILRC clock cycles before

first instruction being executed, which is t_SBPand shown in the Fig. 1.

VDD

t

SBP

POR

Program

Execution

Boot up from Power-On Reset

Fig. 1: Power Up Sequence

Page 25 of 71

PDK-DS-PMX156-EN_V106 – Dec. 12, 2018

PMC156/PMS156 Series

8bit OTP Type IO Controller

5.2.1Timing charts for reset conditions

LVR level

VDD

LVR

SBP

t

Program

Execution

Boot up from LVR detection

VDD

t

SBP

WD

Time Out

Program

Execution

Boot up from Watch Dog Time Out

VDD

Reset#

t

SBP

Program

Execution

Boot up from Reset Pad reset

Page 26 of 71

PDK-DS-PMX156-EN_V106 – Dec. 12, 2018

PMC156/PMS156 Series

8bit OTP Type IO Controller

5.3. Data Memory – SRAM

The access of data memory can be byte or bit operation. Besides data storage, the SRAM data memory is also

served as data pointer of indirect access method and the stack memory.

The stack memory is defined in the data memory. The stack pointer is defined in the stack pointer register; the

depth of stack memory of each processing unit is defined by the user. The arrangement of stack memory fully

flexible and can be dynamically adjusted by the user.

For indirect memory access mechanism, the data memory is used as the data pointer to address the data byte.

All the data memory could be the data pointer; it’s quite flexible and useful to do the indirect memory access. All

the 64 bytes data memory of PMC156/PMS156 can be accessed by indirect access mechanism.

5.4. Oscillator and clock

There are three oscillator circuits provided by PMC156/PMS156: external crystal oscillator (EOSC), internal

high RC oscillator (IHRC) and internal low RC oscillator (ILRC), and these three oscillators are enabled or

disabled by registers eoscr.7, clkmd.4 and clkmd.2 independently. User can choose one of these three

oscillators as system clock source and use clkmd register to target the desired frequency as system clock to

meet different applications.

Oscillator Module

EOSC

Enable/Disable

eoscr.7

IHRC

clkmd.4

ILRC

clkmd.2

Table2: Three Oscillator Circuits provided by PMC156/PMS156

5.4.1. Internal High RC oscillator and Internal Low RC oscillator

After boot-up, the IHRC and ILRC oscillators are enabled. The frequency of IHRC can be calibrated to

eliminate process variation by ihrcr register; normally it is calibrated to 16MHz. The frequency deviation can be

within 2% normally after calibration and it still drifts slightly with supply voltage and operating temperature.

Please refer to the measurement chart for IHRC frequency verse VDD and IHRC frequency verse temperature.

The frequency of ILRC will vary by process, supply voltage and temperature, please refer to DC specification

and do not use for accurate timing application.

5.4.2. IHRC calibration

The IHRC frequency may be different chip by chip due to manufacturing variation, PMC156/PMS156 provide

the IHRC frequency calibration to eliminate this variation, and this function can be selected when compiling

user’s program and the command will be inserted into user’s program automatically. The calibration command

is shown as below:

.ADJUST_IC SYSCLK=IHRC/(p1), IHRC=(p2)MHz, V_DD=(p3)V

Where,

p1=2, 4, 8, 16, 32; In order to provide different system clock.

p2=16 ~ 18; In order to calibrate the chip to different frequency, 16MHz is the usually one.

p3=2.2 ~ 5.5; In order to calibrate the chip under different supply voltage.

Page 27 of 71

PDK-DS-PMX156-EN_V106 – Dec. 12, 2018

PMC156/PMS156 Series

8bit OTP Type IO Controller

5.4.3. IHRC Frequency Calibration and System Clock

During compiling the user program, the options for IHRC calibration and system clock are shown as Table 3:

SYSCLK

○ Set IHRC / 2

○ Set IHRC / 4

○ Set IHRC / 8

○ Set IHRC / 16

○ Set IHRC / 32

○ Set ILRC

CLKMD

IHRCR

Calibrated

Description

= 34h (IHRC / 2)

= 14h (IHRC / 4)

= 3Ch (IHRC / 8)

IHRC calibrated to 16MHz, CLK=8MHz (IHRC/2)

IHRC calibrated to 16MHz, CLK=4MHz (IHRC/4)

IHRC calibrated to 16MHz, CLK=2MHz (IHRC/8)

IHRC calibrated to 16MHz, CLK=1MHz (IHRC/16)

IHRC calibrated to 16MHz, CLK=0.5MHz (IHRC/32)

IHRC calibrated to 16MHz, CLK=ILRC

= 1Ch (IHRC / 16) Calibrated

= 7Ch (IHRC / 32) Calibrated

= E4h (ILRC / 1)

No change

Calibrated

○ Disable

No Change

IHRC not calibrated, CLK not changed

Table 3: Options for IHRC Frequency Calibration

Usually, .ADJUST_IC will be the first command after boot up, in order to set the target operating frequency

whenever stating the system. The program code for IHRC frequency calibration is executed only one time that

occurs in writing the codes into OTP memory; after then, it will not be executed again. If the different option for

IHRC calibration is chosen, the system status is also different after boot. The following shows the status of

PMC156 for different option:

(1) .ADJUST_IC SYSCLK=IHRC/2, IHRC=16MHz, V_DD=5V

After boot up, CLKMD = 0x34：



IHRC frequency is calibrated to 16MHz@V_DD=5V and IHRC module is enabled

System CLK = IHRC/2 = 8MHz

Watchdog timer is disabled, ILRC is enabled, PA5 is in input mode

(2) .ADJUST_IC SYSCLK=IHRC/4, IHRC=16MHz, V_DD=3.3V

After boot, CLKMD = 0x14：



IHRC frequency is calibrated to 16MHz@V_DD=3.3V and IHRC module is enabled

System CLK = IHRC/4 = 4MHz

Watchdog timer is disabled, ILRC is enabled, PA5 is in input mode

(3) .ADJUST_IC SYSCLK=IHRC/8, IHRC=16MHz, V_DD=2.5V

After boot, CLKMD = 0x3C：



IHRC frequency is calibrated to 16MHz@V_DD=2.5V and IHRC module is enabled

System CLK = IHRC/8 = 2MHz

Watchdog timer is disabled, ILRC is enabled, PA5 is in input mode

(4) .ADJUST_IC SYSCLK=IHRC/16, IHRC=16MHz, V_DD=2.2V

After boot, CLKMD = 0x1C：



IHRC frequency is calibrated to 16MHz@V_DD=2.2V and IHRC module is enabled

System CLK = IHRC/16 = 1MHz

Watchdog timer is disabled, ILRC is enabled, PA5 is in input mode

Page 28 of 71

PDK-DS-PMX156-EN_V106 – Dec. 12, 2018

PMC156/PMS156 Series

8bit OTP Type IO Controller

(5) .ADJUST_IC SYSCLK=IHRC/32, IHRC=16MHz, V_DD=5V

After boot, CLKMD = 0x7C：



IHRC frequency is calibrated to 16MHz@V_DD=5V and IHRC module is enabled

System CLK = IHRC/32 = 500kHz

Watchdog timer is disabled, ILRC is enabled, PA5 is in input mode

(6) .ADJUST_IC SYSCLK=ILRC, IHRC=16MHz, V_DD=5V

After boot, CLKMD = 0XE4：



IHRC frequency is calibrated to 16MHz@V_DD=5V and IHRC module is disabled

System CLK = ILRC

Watchdog timer is enabled, ILRC is disabled, PA5 is input mode

(7) .ADJUST_IC DISABLE

After boot, CLKMD is not changed (Do nothing)：



IHRC is not calibrated and IHRC module is disabled. Band-gap is not calibrated.

System CLK = ILRC

Watchdog timer is enabled, ILRC is enabled, PA5 is in input mode

5.4.4. External Crystal Oscillator

If crystal oscillator is used, a crystal or resonator is required between X1 and X2. Fig. 2 shows the hardware

connection under this application; the range of operating frequency of crystal oscillator can be from 32 kHz to

4MHz, depending on the crystal placed on; higher frequency oscillator than 4MHz is NOT supported.

(Select driving current for oscillator)

Eoscr[6:5]

(Enable crystal oscillator)

Eoscr.7

C1

PA7/X1

System clock = EOSC

PA6/X2

C2

The values of C1 and C2 should depend on

the specification of crystal.

Fig. 2: Connection of crystal oscillator

Page 29 of 71

PDK-DS-PMX156-EN_V106 – Dec. 12, 2018

PMC156/PMS156 Series

8bit OTP Type IO Controller

Besides crystal, external capacitor and options of PMC156 should be fine tuned in eoscr (0x0a) register to

have good sinusoidal waveform. The eoscr.7 is used to enable crystal oscillator module, eoscr.6 and eoscr.5

are used to set the different driving current to meet the requirement of different frequency of crystal oscillator:

 eoscr.[6:5]=01 : Low driving capability, for lower frequency, ex: 32kHz crystal oscillator

 eoscr.[6:5]=10 : Middle driving capability, for middle frequency, ex: 1MHz crystal oscillator

 eoscr.[6:5]=11 : High driving capability, for higher frequency, ex: 4MHz crystal oscillator

Table 4 shows the recommended values of C1 and C2 for different crystal oscillator; the measured start-up

time under its corresponding conditions is also shown. Since the crystal or resonator had its own characteristic,

the capacitors and start-up time may be slightly different for different type of crystal or resonator, please refer

to its specification for proper values of C1 and C2.

Measured

Frequency

C1

C2

Conditions

Start-up time

6ms

4MHz

1MHz

32kHz

4.7pF

10pF

22pF

4.7pF

10pF

22pF

(eoscr[6:5]=11, misc.6=0)

(eoscr[6:5]=10, misc.6=0)

(eoscr[6:5]=01, misc.6=0)

11ms

450ms

Table 4: Recommend values of C1 and C2 for crystal and resonator oscillators

When using the crystal oscillator, user must pay attention to the stable time of oscillator after enabling it, the

stable time of oscillator will depend on frequency ` crystal type ` external capacitor and supply voltage. Before

switching the system to the crystal oscillator, user must make sure the oscillator is stable; the reference

program is shown as below:

void

{

FPPA0 (void)

. ADJUST_IC SYSCLK=IHRC/16, IHRC=16MHz, VDD=5V

$

EOSCR Enable, 4Mhz;

T16M EOSC, /1, BIT13;

// EOSCR = 0b110_00000;

// T16 receive 2^14=16384 clocks of crystal EOSC,

// Intrq.T16 =>1, crystal EOSC Is stable

WORD

count

=

0;

stt16count;

Intrq.T16 =

0;

wait1

Intrq.T16;

0xB4;

// count from 0x0000 to 0x2000, then setINTRQ.T16

// switch system clock to EOSC;

//disable IHRC

clkmd

=

Clkmd.4 = 0;

...

Please notice that the crystal oscillator should be fully turned off before entering the power-down mode, in

order to avoid unexpected wakeup event. If the 32kHz crystal oscillator is used and extremely low operating

current is required, misc.6 can be set to reduce current after crystal oscillator is running normally.

Page 30 of 71

PDK-DS-PMX156-EN_V106 – Dec. 12, 2018

PMC156/PMS156 Series

8bit OTP Type IO Controller

5.4.5. System Clock and LVR levels

The clock source of system clock comes from EOSC, IHRC and ILRC, the hardware diagram of system clock

in the PMC156 is shown as Fig. 3.

clkmd[7:5]

÷2, ÷4, ÷8,

÷16, ÷32, ÷64

IHRC

clock

System

clock

CLK

M

U

X

EOSC

clock

÷1, ÷2, ÷4, ÷8

ILRC

clock

÷1 (default), ÷4

Fig. 3: Options of System Clock

User can choose different operating system clock depends on its requirement; the selected operating system

clock should be combined with supply voltage and LVR level to make system stable. The LVR level will be

selected during compilation and the lowest LVR levels can be chosen for different operating frequencies.

Please refer to Section 4.1.

Page 31 of 71

PDK-DS-PMX156-EN_V106 – Dec. 12, 2018

PMC156/PMS156 Series

8bit OTP Type IO Controller

5.4.6. System Clock Switching

After IHRC calibration, user may want to switch system clock to a new frequency or may switch system clock at

any time to optimize the system performance and power consumption. Basically, the system clock of PMC156

can be switched among IHRC, ILRC and EOSC by setting the clkmd register at any time; system clock will be

the new one after writing to clkmd register immediately. Please notice that the original clock module can NOT

be turned off at the same time as writing command to clkmd register. The examples are shown as below and

more information about clock switching, please refer to the “Help -> Application Note -> “IC introduction” ->

“ Register introduction” -> “CLKMD”.

Case 1: Switching system clock from ILRC to IHRC/2

…

//

system clock is ILRC

CLKMD

CLKMD.2

…

=

0x34；

0；

switch to IHRC/2，ILRC CAN NOT be disabled here

ILRC CAN be disabled at this time

Case 2: Switching system clock from ILRC to EOSC

…

//

system clock is ILRC

CLKMD

CLKMD.2

…

=

0xA6； //

switch to IHRC，ILRC CAN NOT be disabled here

ILRC CAN be disabled at this time

0；

//

Case 3: Switching system clock from IHRC/2 to ILRC

…

//

system clock is IHRC/2

CLKMD

CLKMD.4

…

=

0xF4；

0；

switch to ILRC，IHRC CAN NOT be disabled here

IHRC CAN be disabled at this time

Case 4: Switching system clock from IHRC/2 to EOSC

…

//

system clock is IHRC/2

CLKMD

CLKMD.4

…

=

0XB0； //

switch to EOSC，IHRC CAN NOT be disabled here

IHRC CAN be disabled at this time

0；

//

Case 5: Switching system clock from IHRC/2 to IHRC/4

…

//

system clock is IHRC/2, ILRC is enabled here

switch to IHRC/4

CLKMD

…

=

0X14； //

Case 6: System may hang if it is to switch clock and turn off original oscillator at the same time

…

//

system clock is ILRC

CLKMD

=

0x30；

CAN NOT switch clock from ILRC to IHRC/2 and

turn off ILRC oscillator at the same time

Page 32 of 71

PDK-DS-PMX156-EN_V106 – Dec. 12, 2018

PMC156/PMS156 Series

8bit OTP Type IO Controller

5.5 16-bit Timer (Timer16)

A 16-bit hardware timer (Timer16) is implemented in the PMC156/PMS156, the clock sources of Timer16 may

come from system clock (CLK), clock of external crystal oscillator (EOSC), internal high RC oscillator (IHRC),

internal low RC oscillator (ILRC) and PA0, a multiplex is used to select clock output for the clock source. Before

sending clock to the counter16, a pre-scaling logic with divided-by-1, 4, 16, and 64 is used for wide range

counting. The 16-bit counter performs up-counting operation only, the counter initial values can be stored from

memory by stt16 instruction and the counting values can be loaded to memory by ldt16 instruction. A selector is

used to select the interrupt condition of Timer16, whenever overflow occurs, the Timer16 interrupt can be

triggered. The hardware diagram of Timer16 is shown as Fig. 4. The interrupt source of Timer16 comes from

one of bit 8 to 15 of 16-bit counter, and the interrupt type can be rising edge trigger or falling edge trigger which

is specified in the bit 4 of integs register (IO address 0x0C).

stt16 command

DATA Memory

t16m[7:5]

t16m[4:3]

ldt16 command

CLK

M

U

X

Pre-

scalar

÷

1, 4,

16, 64

16-bit

up

counter

Bit[15:0]

IHRC

EOSC

ILRC

Data Bus

PA0↓

Bit[15:8]

M

U

X

To set

interrupt

request flag

or

t16m[2:0]

integs.4

Fig. 4: Hardware diagram of Timer16

When using the Timer16, the syntax for Timer16 has been defined in the .INC file. There are three parameters

to define the Timer16 using; 1^stparameter is used to define the clock source of Timer16, 2^ndparameter is used

to define the pre-scalar and the 3^rdone is to define the interrupt source.

T16M

$ 7~5:

IO_RW

0x06

STOP, SYSCLK, X , PA4_F, IHRC, EOSC, ILRC, PA0_F

/1, /4, /16, /64

// 1^stpar.

// 2^ndpar.

// 3^rdpar.

$ 4~3:

$ 2~0:

BIT8, BIT9, BIT10, BIT11, BIT12, BIT13, BIT14, BIT15

Page 33 of 71

PDK-DS-PMX156-EN_V106 – Dec. 12, 2018

PMC156/PMS156 Series

8bit OTP Type IO Controller

User can choose the proper parameters of T16M to meet system requirement, examples as below (For more

examples, please refer to IDE software "Application Note  Introduction of IC  Introduction of Register 

T16M"):

$

T16M

SYSCLK, /64, BIT15;

// choose (SYSCLK/64) as clock source, every 2^16 clock to set INTRQ.2=1

// if using System Clock = IHRC / 2 = 8 MHz

// SYSCLK/64 = 8 MHz/64 = 125kHz, about every 512 mS to generate INTRQ.2=1

$

T16M

EOSC, /1, BIT13;

// choose (EOSC/1) as clock source, every 2^14 clocks to generate INTRQ.2=1

// if EOSC=32768 Hz, 32768 Hz/(2^14) = 2Hz, every 0.5S to generate INTRQ.2=1

T16M

PA0_F, /1, BIT8;

// choose PA0 as clock source, every 2^9 to generate INTRQ.2=1

// receiving every 512 times PA0 to generate INTRQ.2=1

T16M

STOP;

// stop Timer16 counting

If Timer16 is operated at free running, the frequency of interrupt can be described as below:

F_{INTRQ_T16M}= F_{clock source}÷ P ÷ 2ⁿ⁺¹

Where,

F is the frequency of selected clock source to Timer16;

P is the selection of t16m [4:3]; (1, 4, 16, 64)

N is the n^thbit selected to request interrupt service, for example: n=10 if bit 10 is selected.

Page 34 of 71

PDK-DS-PMX156-EN_V106 – Dec. 12, 2018

PMC156/PMS156 Series

8bit OTP Type IO Controller

5.6 Watchdog Timer

The watchdog timer (WDT) is a counter with clock coming from ILRC. There are three different timeout periods

of watchdog timer can be chosen by setting the misc register, they are:



16384 ILRC clock period when misc[1:0]=10

4096 ILRC clock period when misc[1:0]=01

2048 ILRC clock period when misc[1:0]=00 (default)

The frequency of ILRC may drift a lot due to the variation of manufacture, supply voltage and temperature; user

should reserve guard band for safe operation. WDT can be cleared by power-on-reset or by command wdreset

at any time. When WDT is timeout, PMC156 will be reset to restart the program execution. The relative timing

diagram of watchdog timer is shown as Fig. 5.

VDD

t

SBP

WD

Time Out

Program

Execution

Watch Dog Time Out Sequence

Fig. 5: Sequence of Watch Dog Time Out

5.7 Interrupt

There are three interrupt lines for PMC156:



External interrupt PA0

External interrupt PB0

Timer16 interrupt

Every interrupt request line has its own corresponding interrupt control bit to enable or disable it; the hardware

diagram of interrupt function is shown as Fig. 6. All the interrupt request flags are set by hardware and cleared

by writing intrq register. When the request flags are set, it can be rising edge, falling edge or both, depending on

the setting of register integs. All the interrupt request lines are also controlled by engint instruction (enable

global interrupt) to enable interrupt operation and disgint instruction (disable global interrupt) to disable it. The

stack memory for interrupt is shared with data memory and its address is specified by stack register sp. Since

the program counter is 16 bits width, the bit 0 of stack register sp should be kept 0. Moreover, user can use

pushaf / popaf instructions to store or restore the values of ACC and flag register to / from stack memory.

Page 35 of 71

PDK-DS-PMX156-EN_V106 – Dec. 12, 2018

PMC156/PMS156 Series

8bit OTP Type IO Controller

Since the stack memory is shared with data memory, the stack position and level are arranged by the compiler

in Mini-C project. When defining the stack level in ASM project, users should arrange their locations carefully to

prevent address conflicts.

Inten.2

T16 output

Integs.4

PB0

Intrq.2

Select Edge

& Set Flag

Interrupt

to FPP0

Inten.1

Intrq.1

Select Edge

& Set Flag

Integs[3:2]

PA0

engint & disgint

Inten.0

Intrq.0

Select Edge

& Set Flag

Integs[1:0]

Fig. 6: Hardware diagram of Interrupt controller

Once the interrupt occurs, its operation will be:

 The program counter will be stored automatically to the stack memory specified by register sp.

 New sp will be updated to sp+2.

 Global interrupt will be disabled automatically.

 The next instruction will be fetched from address 0x010.

During the interrupt service routine, the interrupt source can be determined by reading the intrq register.

Note: Even if INTEN=0, INTRQ will be still triggered by the interrupt source.

After finishing the interrupt service routine and issuing the reti instruction to return back, its operation will be:

 The program counter will be restored automatically from the stack memory specified by register sp.

 New sp will be updated to sp-2.

 Global interrupt will be enabled automatically.

 The next instruction will be the original one before interrupt.

User must reserve enough stack memory for interrupt, two bytes stack memory for one level interrupt and four

bytes for two levels interrupt. For interrupt operation, the following sample program shows how to handle the

interrupt, noticing that it needs four bytes stack memory to handle interrupt and pushaf.

void

{

FPPA0

(void)

...

$

INTEN PA0;

//

INTEN =1; interrupt request when PA0 level changed

clear INTRQ

INTRQ

ENGINT

...

=

0;

global interrupt enable

DISGINT

...

//

global interrupt disable

}

Page 36 of 71

PDK-DS-PMX156-EN_V106 – Dec. 12, 2018

PMC156/PMS156 Series

8bit OTP Type IO Controller

void Interrupt (void)

// interrupt service routine

{

PUSHAF

// store ALU and FLAG register

// If INTEN.PA0 will be opened and closed dynamically,

// user can judge whether INTEN.PA0 =1 or not.

// Example: If (INTEN.PA0 && INTRQ.PA0) {…}

// If INTEN.PA0 is always enable,

// user can omit the INTEN.PA0 judgement to speed up interrupt service routine.

If (INTRQ.PA0)

{

// Here for PA0 interrupt service routine

INTRQ.PA0 = 0;

...

// Delete corresponding bit (take PA0 for example)

}

...

// X : INTRQ = 0;

// It is not recommended to use INTRQ = 0 to clear all at the end of

// the interrupt service routine.

// It may accidentally clear out the interrupts that have just occurred

// and are not yet processed.

POPAF

// restore ALU and FLAG register

}

Page 37 of 71

PDK-DS-PMX156-EN_V106 – Dec. 12, 2018

PMC156/PMS156 Series

8bit OTP Type IO Controller

5.8 Power-Save and Power-Down

There are three operational modes defined by hardware: ON mode, Power-Save mode and Power-Down

modes. ON mode is the state of normal operation with all functions ON, Power-save mode (“stopexe”) is the

state to reduce operating current and CPU keeps ready to continue, Power-Down mode (“stopsys”) is used to

save power deeply. Therefore, Power-save mode is used in the system which needs low operating power with

wake-up occasionally and Power-Down mode is used in the system which needs power down deeply with

seldom wake-up. Fig. 7 shows the differences in oscillator modules between Power-Save mode (“stopexe”) and

Power-Down mode (“stopsys”).

Differences in oscillator modules between STOPSYS and STOPEXE

IHRC

Stop

ILRC

Stop

EOSC

Stop

STOPSYS

STOPEXE

No Change

Fig. 7: Differences in oscillator modules between STOPSYS and STOPEXE

5.8.1. Power-Save mode (“stopexe”)

Using “stopexe” instruction to enter the Power-Save mode, only system clock is disabled, remaining all the

oscillator modules active. For CPU, it stops executing; however, for Timer16, counter keep counting if its clock

source is not the system clock. The wake-up sources for “stopexe” can be IO-toggle or Timer16 counts to the

set values when clock sources of Timer16 come from IHRC, ILRC or EOSC modules. Wake-up from input pins

can be considered as a continuation of normal execution, nop command is recommended to follow the

stopexe command, the detail information for Power-Save mode shows below:

 IHRC and EOSC oscillator modules: No change, keep active if it was enabled

 ILRC oscillator modules: must remain enabled, need to start with ILRC when be wakening up.

 System clock: Disable, therefore, CPU stops execution

 OTP memory is turned off

 Timer16: Stop counting if system clock is selected or the corresponding oscillator module is disabled;

otherwise, it keeps counting.

 Wake-up sources: IO toggle in digital mode (PxDIER bit is 1) or Timer16.

The watchdog timer must be disabled before issuing the “stopexe” command, the example is shown as below:

CLKMD.En_WatchDog

=

0;

1;

// disable watchdog timer

stopexe;

nop;

….

// power saving

Wdreset;

CLKMD.En_WatchDog

// enable watchdog timer

Page 38 of 71

PDK-DS-PMX156-EN_V106 – Dec. 12, 2018

PMC156/PMS156 Series

8bit OTP Type IO Controller

Another example shows how to use Timer16 to wake-up from “stopexe”:

$ T16M IHRC, /1, BIT8

…

// Timer16 setting

WORD

STT16

stopexe;

nop;

count

=

0;

count;

…

The initial counting value of Timer16 is zero and the system will be waken up after the Timer16 counts 256 IHRC

clocks.

5.8.2. Power-Down mode (“stopsys”)

Power-Down mode is the state of deeply power-saving with turning off all the oscillator modules. By using the

“stopsys” instruction, this chip will be put on Power-Down mode directly. The internal low frequency RC

oscillator must be enabled before entering the Power-Down mode, means that bit 2 of register clkmd (0x03)

must be set to high before issuing “stopsys” command in order to resume the system when wakeup. The

following shows the internal status of PMC156 in detail when “stopsys” command is issued:

 All the oscillator modules are turned off

 Enable internal low RC oscillator (set bit 2 of register clkmd)

 OTP memory is turned off

 The contents of SRAM and registers remain unchanged

 Wake-up sources: IO toggle in digital mode (PxDIER bit is 1)

Wake-up from input pins can be considered as a continuation of normal execution. To minimize power

consumption, all the I/O pins should be carefully manipulated before entering power-down mode. The

reference sample program for power down is shown as below:

CMKMD

CLKMD.4

…

=

0xF4;

0;

//

change clock from IHRC to ILRC, disable watchdog timer

disable IHRC

while (1)

{

STOPSYS;

//

enter power-down

if (…) break;

if wakeup happen and check OK, then return to high speed,

else stay in power-down mode again.

}

CLKMD=

0x34;

//

change clock from ILRC to IHRC/2

Page 39 of 71

PDK-DS-PMX156-EN_V106 – Dec. 12, 2018

PMC156/PMS156 Series

8bit OTP Type IO Controller

5.8.3. Wake-up

After entering the Power-Down or Power-Save modes, the PMC156 can be resumed to normal operation by

toggling IO pins, Timer16 interrupt is available for Power-Save mode ONLY. Fig. 8 shows the differences in

wake-up sources between STOPSYS and STOPEXE.

Differences in wake-up sources between STOPSYS and STOPEXE

IO Toggle

Yes

T16 Interrupt

STOPSYS

STOPEXE

No

Yes

Fig. 8: Differences in wake-up sources between Power-Save mode and Power-Down mode

When using the IO pins to wake-up the PMC156/PMS156, registers padier and pbdier should be properly set

to enable the wake-up function for every corresponding pin. The wake-up time for normal wake-up is about

1024 ILRC clocks counting from wake-up event; fast wake-up can be selected to reduce the wake-up time by

misc register. For fast wake-up mechanism, the wake-up time is 128 system clocks from IO toggling if

STOPEXE was issued, and 128 system clocks plus oscillator (IHRC or ILRC) stable time from IO toggling if

STOPSYS was issued. The oscillator stable time is the time for IHRC or ILRC oscillator from power-on,

depending on which oscillator is used as system clock source. Please notice that there is no fast wake-up

mode whenever EOSC is enabled.

system clock

Suspend mode

wake-up mode

wake-up time (t_WUP) from IO toggle

source

128 * T_SYS,

STOPEXE suspend

fast wake-up

IHRC or ILRC

Where T_SYSis the time period of system clock

128 T_{SYS +}T_SIHRC

;

STOPSYS suspend

fast wake-up

IHRC

ILRC

Where T_SIHRCis the stable time of IHRC from

power-on.

128 T_{SYS +}T_SILRC

;

Where T_SILRCis the stable time of ILRC from

power-on.

STOPSYS or

STOPEXE

suspend

1024 * T_ILRC

,

EOSC

Where T_ILRCis the clock period of ILRC

1024 * T_ILRC

Where T_ILRCis the clock period of ILRC

1024 * T_ILRC

Where T_ILRCis the clock period of ILRC

,

STOPEXE suspend normal wake-up

STOPSYS suspend normal wake-up

Any one

,

Please notice that the clock source of watch-dog will be switched to system clock (for example: 4MHz) when

fast wakeup is enabled. Therefore, for fast wake-up, recommending turning off the watchdog timer when

enabling the fast wakeup. When wake-up, turning on the watchdog timer after disabling the fast wakeup.

Page 40 of 71

PDK-DS-PMX156-EN_V106 – Dec. 12, 2018

PMC156/PMS156 Series

8bit OTP Type IO Controller

To avoid unable wake-up problem happening from drifted process, please switch the system operating

frequency to ILRC/1 before executing STOPSYS/STOPEXE instruction, and then switch to the original

system operating frequency after waking-up, the example is shown as below:

….

$ CLKMD

stopsys;

$ CLKMD

ILRC/1,En_IHRC,En_ILRC

IHRC/n,En_IHRC,En_ILRC

//SYSCLK switch to ILRC

//Use stopsys or stopexe

//Switch to SYSCLK after waking-up

Page 41 of 71

PDK-DS-PMX156-EN_V106 – Dec. 12, 2018

PMC156/PMS156 Series

8bit OTP Type IO Controller

5.9 IO Pins

Other than PA5, all the pins can be independently set into two states output or input by configuring the data

registers (pa, pb), control registers (pac, pbc) and pull-high registers (paph, pbph). All these pins have

Schmitt-trigger input buffer and output driver with CMOS level. When it is set to output low, the pull-high resistor

is turned off automatically. If user wants to read the pin state, please notice that it should be set to input mode

before reading the data port; if user reads the data port when it is set to output mode, the reading data comes

from data register, NOT from IO pad. As an example, Table 5 shows the configuration table of bit 0 of port A.

The hardware diagram of IO buffer is also shown as Fig. 9.

pa.0 pac.0 paph.0

Description

Input without pull-high resistor

X

0

1

0

1

0

1

X

0

1

Input with pull-high resistor

Output low without pull-high resistor

Output high without pull-high resistor

Output high with pull-high resistor

Table 5: PA0 Configuration Table

RD pull -high latch

WR pull -high latch

D

Q

(weak P -MOS)

pull-high

latch

D

Q

Data

latch

Q1

PAD

WR data latch

RD control latch

Q

WR control latch

Control

M

U

latch

X

RD Port

Data Bus

padier .x or pbdier.x

Wakeup module

Interrupt module

(PA0,PB0 only)

Analog Module

Fig. 9: Hardware diagram of IO buffer

Other than PA5, all the IO pins have the same structure; PA5 can be open-drain ONLY when setting to output

mode (without Q1). When PMC156 is put in power-down or power-save mode, every pin can be used to

wake-up system by toggling its state. Therefore, those pins needed to wake-up system must be set to input

mode and set the corresponding bits of registers padier or pbdier to high. The same reason, padier.0 should

be set high when PA0 is used as external interrupt pin and pbdier.0 for PB0.

Page 42 of 71

PDK-DS-PMX156-EN_V106 – Dec. 12, 2018

PMC156/PMS156 Series

8bit OTP Type IO Controller

5.10 Reset and LVR

5.10.1. Reset

There are many causes to reset the PMC156/PMS156, once reset is asserted, all the registers in PMC156

will be set to default values, system should be restarted once abnormal cases happen, or by jumping program

counter to address ’h0. The data memory is in uncertain state when reset comes from power-up and LVR;

however, the content will be kept when reset comes from PRST# pin or WDT timeout.

5.10.2. LVR reset

By code option, there are many different levels of LVR for reset . Usually, user selects LVR reset level to be in

conjunction with operating frequency and supply voltage.

5.10.3. Notice for LVR reset

In some applications, the power VDD may change rapidly because of quick switching the power source

manually or strong power noise. In case, when the power VDD drops to the level that is lower than the LVR

level but higher than 1.0V, if at this time the power VDD is pulled up again to be over LVR level (just see the

diagram below), there may be some chances that cause the MCU malfunction or hanged.

VDD

|

- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -

LVR

|

1.0V

|

- - - - - - - - - - - - - - - - - -

|

- - - - - - - - - - - - - - - - - - - - - - - - - - - - -

Output

vvvvvvvvvv

LVR reset state

Reset succeed，IO signal output

Reset fail，IO signal output stop

Page 43 of 71

PDK-DS-PMX156-EN_V106 – Dec. 12, 2018

PMC156/PMS156 Series

8bit OTP Type IO Controller

To avoid the above problem, please follow the below steps in your program:

Step 1. Insert the below two instructions just after the .ADJUST_IC instruction

SET1 inten.7

Notice: IDE 0.57 or above version will insert this instruction automatically.

Intrq

=

0;

Notice: IDE 0.59 or above version will insert this instruction automatically.

Step 2. Never clear the inten.7 through out the whole program. Please pay special attention in accidental

clear inten.7 by writing operation to the whole inten register. Please consider using set1/set0 instruction

to change other interrupt enable flags.

Notice: IDE 0.57 or above version will block the reset operation of inten.7 automatically.

Step 3. When wdreset instruction is being used:

Please modify the wdreset instruction inside the main loop of the program:

C language:

If (inten.7==0) reset; else {wdreset;}

Assembly language: t1sn inten.7;

reset

wdreset

or use as below :

.wdreset

（for IDE 0.57 or above version only）

Step 4. When clkmd is being used:

When clkmd instruction is set inside the main loop of the program and clkmd.1 = 0, please insert below

instructions afterward.

C language:

If (inten.7==0) reset;

Assembly language:

t1sn

inten.7;

reset

or use as below to set clkmd:

.clkmd = 0x hh;

( “ hh” is a hexadecimal value. For IDE 0.59 or above version only)

Page 44 of 71

PDK-DS-PMX156-EN_V106 – Dec. 12, 2018

PMC156/PMS156 Series

8bit OTP Type IO Controller

5.11 LCD Bias Voltage Generator

This function can be enabled by misc.4 and code option LCD2. There are two sets of pins can be selected as

the LCD COM ports, four pins in each set. By selecting PA_1234 for LCD2, PA1, PA2, PA3 and PA4 are

defined to output VDD/2 voltage during input mode, and be used as COM function for LCD applications. By

selecting PB_1256 of LCD2, PB1, PB2, PB5 and PB6 are defined as COM ports.

If user wants to output VDD, VDD/2, GND three levels voltage, enabling VDD/2 bias voltage (by set misc.4=1),

then set to output-high for VDD, with input mode for VDD/2, and output-low for GND correspondingly, Fig.10

shows how to use this function.

VDD

VDD/2

GND

Pin set to output high

Pin set to input

Pin set to output low

Fig. 10: Using VDD/2 bias voltage generator

Page 45 of 71

PDK-DS-PMX156-EN_V106 – Dec. 12, 2018

PMC156/PMS156 Series

8bit OTP Type IO Controller

6. IO Registers

6.1ACC Status Flag Register (flag), IO address = 0x00

Bit Reset R/W

Description

Reserved. These four bits are “1” when read.

7 – 4

3

-

R/W OV (Overflow). This bit is set whenever the sign operation is overflow.

AC (Auxiliary Carry). There are two conditions to set this bit, the first one is carry out of low

R/W nibble in addition operation, and the other one is borrow from the high nibble into low nibble

in subtraction operation.

2

-

C (Carry). There are two conditions to set this bit, the first one is carry out in addition

R/W operation, and the other one is borrow in subtraction operation. Carry is also affected by

shift with carry instruction.

1

0

-

Z (Zero). This bit will be set when the result of arithmetic or logic operation is zero;

R/W

Otherwise, it is cleared.

6.2 Stack Pointer Register (sp), IO address = 0x02

Bit Reset R/W

Description

Stack Pointer Register. Read out the current stack pointer, or write to change the stack

pointer. Please notice that bit 0 should be kept 0 due to program counter is 16 bits.

7 – 0 R/W

-

6.3 Clock Mode Register (clkmd), IO address = 0x03

Bit Reset R/W

Description

System clock selection:

Type 0, clkmd[3]=0

Type 1, clkmd[3]=1

000: IHRC/4

001: IHRC/2

010: reserved

011: EOSC/4

100: EOSC/2

101: EOSC

000: IHRC/16

001: IHRC/8

010: reserved

011: IHRC/32

100: IHRC/64

101: EOSC/8

11X: reserved

7 – 5

111 R/W

110: ILRC/4

111: ILRC (default)

4

3

1

0

R/W IHRC oscillator Enable. 0 / 1: disable / enable

Clock Type Select. This bit is used to select the clock type in bit [7:5].

0 / 1: Type 0 / Type 1

RW

ILRC Enable. 0 / 1: disable / enable

2

1

R/W

If ILRC is disabled, watchdog timer is also disabled.

1

0

1

0

R/W Watch Dog Enable. 0 / 1: disable / enable

R/W Pin PA5/PRST# function. 0 / 1: PA5 / PRST#.

6.4 Interrupt Enable Register (inten), IO address = 0x04

Bit Reset R/W

Description

7 – 3

-

R/W Reserved.

2

1

0

R/W Enable interrupt from Timer16 overflow. 0 / 1: disable / enable.

R/W Enable interrupt from PB0. 0 / 1: disable / enable.

R/W Enable interrupt from PA0. 0 / 1: disable / enable.

Page 46 of 71

PDK-DS-PMX156-EN_V106 – Dec. 12, 2018

PMC156/PMS156 Series

8bit OTP Type IO Controller

6.5 Interrupt Request Register (intrq), IO address = 0x05

Bit Reset R/W

Description

7 – 3

-

R/W Reserved.

Interrupt Request from Timer16, this bit is set by hardware and cleared by software.

0 / 1: No request / Request

2

-

R/W

Interrupt Request from pin PB0, this bit is set by hardware and cleared by software.

0 / 1: No request / Request

1

0

-

Interrupt Request from pin PA0, this bit is set by hardware and cleared by software.

0 / 1: No request / Request

6.6 Timer 16 mode Register (t16m), IO address = 0x06

Bit Reset R/W

Description

Timer Clock source selection

000: Timer 16 is disabled

001: CLK (system clock)

010: reserved

7 – 5

4 – 3

2 – 0

000 R/W 011: PA4 falling edge (from external pin)

100: IHRC

101: EOSC

110: ILRC

111: PA0 falling edge (from external pin)

Internal clock divider.

00: /1

00

R/W 01: /4

10: /16

11: /64

Interrupt source selection. Interrupt event happens when selected bit is changed.

0 : bit 8 of Timer16

1 : bit 9 of Timer16

2 : bit 10 of Timer16

000 R/W 3 : bit 11 of Timer16

4 : bit 12 of Timer16

5 : bit 13 of Timer16

6 : bit 14 of Timer16

7 : bit 15 of Timer16

6.7 External Oscillator setting Register (eoscr, write only), IO address = 0x0a

Bit

Reset R/W

Description

7

0

WO Enable external crystal oscillator. 0 / 1 : Disable / Enable

External crystal oscillator selection.

00 : reserved

6 – 5

00

WO 01 : Low driving capability, for lower frequency, ex: 32kHz crystal oscillator

10 : Middle driving capability, for middle frequency, ex: 1MHz crystal oscillator

11 : High driving capability, for higher frequency, ex: 4MHz crystal oscillator

4 – 1

0

-

Reserved. Please keep 0 for future compatibility.

0

WO Power-down the Band-gap and LVR hardware modules. 0 / 1: normal / power-down.

Page 47 of 71

PDK-DS-PMX156-EN_V106 – Dec. 12, 2018

PMC156/PMS156 Series

8bit OTP Type IO Controller

6.8 IHRC oscillator control Register (ihrcr, write only), IO address = 0x0b

Bit

Reset R/W

Description

Bit [7:0] of internal high RC oscillator for frequency calibration.

For system using only, please user do NOT write this register.

7 – 0

-

WO

6.9 Interrupt Edge Select Register (integs), IO address = 0x0c

Bit

Reset R/W

Description

7 – 5

-

Reserved. Please keep 0.

Timer16 edge selection.

4

0

WO 0 : rising edge to trigger interrupt

1 : falling edge to trigger interrupt

PB0 edge selection.

00 : both rising edge and falling edge to trigger interrupt

WO 01 : rising edge to trigger interrupt

10 : falling edge to trigger interrupt

11 : reserved.

3 – 2

00

PA0 edge selection.

00 : both rising edge and falling edge to trigger interrupt

WO 01 : rising edge to trigger interrupt

10 : falling edge to trigger interrupt

11 : reserved.

1 – 0

Page 48 of 71

PDK-DS-PMX156-EN_V106 – Dec. 12, 2018

PMC156/PMS156 Series

8bit OTP Type IO Controller

6.10 Port A Digital Input Enable Register (padier), IO address = 0x0d

Bit

Reset

R/W

Description

Enable PA7 digital input and wake-up event. 1 / 0 : enable / disable.

This bit should be set to low to prevent leakage current when external crystal oscillator

is used. If this bit is set to low, PA7 can NOT be used to wake-up the system.

Note: For ICE emulation, the function is disabled when this bit is “1” and “0” is enabled.

Enable PA6 digital input and wake-up event. 1 / 0 : enable / disable.

This bit should be set to low to prevent leakage current when external crystal oscillator

is used. If this bit is set to low, PA6 can NOT be used to wake-up the system.

Note: For ICE emulation, the function is disabled when this bit is “1” and “0” is enabled.

Enable PA5 wake-up event. 1 / 0 : enable / disable.

7

1

WO

6

1

WO

5

4

3

2

1

WO This bit can be set to low to disable wake-up from PA5 toggling.

Note: For ICE emulation, wakeup is disabled when this bit is “1” and “0” is enabled.

Enable PA4 digital input and wake-up event. 1 / 0 : enable / disable.

WO If this bit is set to low, PA4 can NOT be used to wake-up the system.

Note: For ICE emulation, the function is disabled when this bit is “1” and “0” is enabled.

Enable PA3 digital input and wake-up event. 1 / 0 : enable / disable.

WO If this bit is set to low, PA3 can NOT be used to wake-up the system.

Note: For ICE emulation, the function is disabled when this bit is “1” and “0” is enabled.

Enable PA2 wake-up event. 1 / 0 : enable / disable.

WO This bit can be set to low to disable wake-up from PA2 toggling.

Note: For ICE emulation, wakeup is disabled when this bit is “1” and “0” is enabled.

Enable PA1 wake-up event. 1 / 0 : enable / disable.

WO This bit can be set to low to disable wake-up from PA1 toggling.

Note: For ICE emulation, wakeup is disabled when this bit is “1” and “0” is enabled.

Enable PA0 wake-up event and interrupt request. 1 / 0 : enable / disable.

This bit can be set to low to disable wake-up from PA0 toggling and interrupt request

0

1

WO

from this pin.

Note: For ICE emulation, the function is disabled when this bit is “1” and “0” is enabled.

Page 49 of 71

PDK-DS-PMX156-EN_V106 – Dec. 12, 2018

PMC156/PMS156 Series

8bit OTP Type IO Controller

6.11 Port B Digital Input Enable Register (pbdier), IO address = 0x0e

Bit

Reset

R/W

Description

Enable PB7 digital input and wake-up event. 1 / 0 : enable / disable.

7

1

WO If this bit is set to low, PB7 can NOT be used to wake-up the system.

Note: For ICE emulation, the function is disabled when this bit is “1” and “0” is enabled.

Enable PB6 wake-up event. 1 / 0 : enable / disable.

6

5

4

3

2

1

WO This bit can be set to low to disable wake-up from PB6 toggling.

Note: For ICE emulation, wakeup is disabled when this bit is “1” and “0” is enabled.

Enable PB5 wake-up event. 1 / 0 : enable / disable.

WO This bit can be set to low to disable wake-up from PB5 toggling.

Note: For ICE emulation, wakeup is disabled when this bit is “1” and “0” is enabled.

Enable PB4 wake-up event. 1 / 0 : enable / disable.

WO This bit can be set to low to disable wake-up from PB4 toggling.

Note: For ICE emulation, wakeup is disabled when this bit is “1” and “0” is enabled.

Enable PB3 digital input and wake-up event. 1 / 0 : enable / disable.

WO If this bit is set to low, PB3 can NOT be used to wake-up the system.

Note: For ICE emulation, the function is disabled when this bit is “1” and “0” is enabled.

Enable PB2 digital input and wake-up event. 1 / 0 : enable / disable.

WO If this bit is set to low, PB2 can NOT be used to wake-up the system.

Note: For ICE emulation, the function is disabled when this bit is “1” and “0” is enabled.

Enable PB1 digital input and wake-up event. 1 / 0 : enable / disable.

WO If this bit is set to low, PB1 can NOT be used to wake-up the system.

Note: For ICE emulation, the function is disabled when this bit is “1” and “0” is enabled.

Enable PB0 digital input, wake-up event and interrupt request. 1 / 0 : enable / disable.

If this bit is set to low, PB0 can NOT be used to wake-up the system and interrupt

0

1

WO

request from this pin.

Note: For ICE emulation, the function is disabled when this bit is “1” and “0” is enabled.

Page 50 of 71

PDK-DS-PMX156-EN_V106 – Dec. 12, 2018

PMC156/PMS156 Series

8bit OTP Type IO Controller

6.12 Port A Data Registers (pa), IO address = 0x10

Bit

Reset R/W

Description

7 – 0 0x00 R/W Data registers for Port A.

6.13Port A Control Registers (pac), IO address = 0x11

Bit

Reset R/W

Description

Port A control registers. This register is used to define input mode or output mode for each

7 – 0 0x00 R/W corresponding pin of port A.

0 / 1: input / output.

6.14 Port A Pull-High Registers (paph), IO address = 0x12

Bit

Reset R/W

Description

Port A pull-high registers. This register is used to enable the internal pull-high device on

each corresponding pin of port A.

7 – 0 0x00 R/W

0 / 1 : disable / enable

Please note that the PA5 does not have pull-high resistor.

6.15 Port B Data Registers (pb), IO address = 0x14

Bit

Reset R/W

Description

7 – 0 0x00 R/W Data registers for Port B.

6.16 Port B Control Registers (pbc), IO address = 0x15

Bit

Reset R/W

Description

Port B control registers. This register is used to define input mode or output mode for each

7 – 0 0x00 R/W corresponding pin of port B.

0 / 1: input / output

6.17 Port B Pull-High Registers (pbph), IO address = 0x16

Bit

Reset R/W

Description

Port B pull-high registers. This register is used to enable the internal pull-high device on

7 – 0 0x00 R/W each corresponding pin of port B.

0 / 1 : disable / enable

Page 51 of 71

PDK-DS-PMX156-EN_V106 – Dec. 12, 2018

PMC156/PMS156 Series

8bit OTP Type IO Controller

6.18 MISC Register (misc), IO address = 0x3b

Bit

Reset R/W

Description

7

-

Reserved

Enable extremely low current for 32kHz crystal oscillator AFTER oscillation.

WO 0: Normal.

1: Low driving current for 32kHz crystal oscillator.

6

0

Enable fast Wake-up. Fast wake-up is NOT supported when EOSC is enabled.

0: Normal wake-up.

The wake-up time is 1024 ILRC clocks

1: Fast wake-up.

The wake-up time is 128 CLKs (system clock) + oscillator stable time.

If wake-up from STOPEXE suspend, there is no oscillator stable time;

If wake-up from STOPSYS suspend, it will be IHRC or ILRC stable time from

power-on.

5

0

WO

Please notice that the clock source will be switched to system clock

(for example: 4MHz) when fast wakeup is enabled, therefore,

it is recommended to turn off the watchdog timer before enabling the fast wakeup

and turn on the watchdog timer after disabling the fast wakeup.

Enable VDD/2 LCD bias voltage generator.

0 / 1 : Disable / Enable (ICE cannot be dynamically switched)

If Code Option selects LCD output, but MISC.4 does not set to 1, then the VDD/2 bias

cannot be output on the IC. However, the emulator is always OK. Two above phenomena

are different.

4

-

Recover time from LVR reset.

3

2

0

WO 0: Normal. The system will take about 1024 ILRC clocks to boot up from LVR reset.

1: Fast. The system will take about 64 ILRC clocks to boot up from LVR reset.

Disable LVR function.

WO

0 / 1 : Enable / Disable

Watch dog time out period

00: 2048 ILRC clock period

WO 01: 4096 ILRC clock period

10: 16384 ILRC clock period

11: Reserved

1 – 0

00

Page 52 of 71

PDK-DS-PMX156-EN_V106 – Dec. 12, 2018

PMC156/PMS156 Series

8bit OTP Type IO Controller

7. Instructions

Symbol

Description

ACC

a

Accumulator ( Abbreviation of accumulator )

Accumulator ( Symbol of accumulator in program )

sp

flag

I

Stack pointer

ACC status flag register

Immediate data

&

Logical AND

|

Logical OR

←

^

Movement

Exclusive logic OR

+

Add

－

〜

〒

OV

Z

Subtraction

NOT (logical complement, 1’s complement)

NEG (2’s complement)

Overflow (The operational result is out of range in signed 2’s complement number system)

Zero (If the result of ALU operation is zero, this bit is set to 1)

Carry (The operational result is to have carry out for addition or to borrow carry for

subtraction in unsigned number system)

C

Auxiliary Carry (If there is a carry out from low nibble after the result of ALU operation, this

bit is set to 1)

AC

word

M.n

Only addressed in 0~0x1F (0~31) is allowed

Only addressed in 0~0xF (0~15) is allowed

Page 53 of 71

PDK-DS-PMX156-EN_V106 – Dec. 12, 2018

PMC156/PMS156 Series

8bit OTP Type IO Controller

7.1 Data Transfer Instructions

mov

a, I

Move immediate data into ACC.

Example: mov a, 0x0f;

Result: a ← 0fh;

Affected flags: 『N』Z 『N』C 『N』AC 『N』OV

M, a

a, M

Move data from ACC into memory

Example: mov

MEM, a;

Result: MEM ← a

Affected flags: 『N』Z 『N』C 『N』AC 『N』OV

Move data from memory into ACC

Example: mov

a, MEM ;

Result: a ← MEM; Flag Z is set when MEM is zero.

Affected flags: 『Y』Z 『N』C 『N』AC 『N』OV

a, IO

Move data from IO into ACC

Example: mov

a, pa ;

Result: a ← pa; Flag Z is set when pa is zero.

Affected flags: 『Y』Z 『N』C 『N』AC 『N』OV

IO, a

Move data from ACC into IO

Example: mov

Result: pb ← a

pb, a;

Affected flags: 『N』Z 『N』C 『N』AC 『N』OV

Move 16-bit counting values in Timer16 to memory in word.

Example: ldt16 word;

ldt16 word

Result:

word ← 16-bit timer

Affected flags: 『N』Z 『N』C 『N』AC 『N』OV

Application Example:

------------------------------------------------------------------------------------------------------------------------

word

…

T16val ;

// declare a RAM word

clear

stt16

…

lb@ T16val ;

hb@ T16val ;

T16val ;

// clear T16val (LSB)

// clear T16val (MSB)

// initial T16 with 0

set1

…

t16m.5 ;

// enable Timer16

set0

ldt16

….

t16m.5 ;

T16val ;

// disable Timer 16

// save the T16 counting value to T16val

------------------------------------------------------------------------------------------------------------------------

Page 54 of 71

PDK-DS-PMX156-EN_V106 – Dec. 12, 2018

PMC156/PMS156 Series

8bit OTP Type IO Controller

stt16 word

Store 16-bit data from memory in word to Timer16.

Example: stt16 word;

Result:

16-bit timer ←word

Affected flags: 『N』Z 『N』C 『N』AC 『N』OV

Application Example:

------------------------------------------------------------------------------------------------------------------------

word

…

T16val ;

// declare a RAM word

mov

stt16

…

a, 0x34 ;

lb@ T16val , a ; // move 0x34 to T16val (LSB)

a, 0x12 ;

hb@ T16val , a ; // move 0x12 to T16val (MSB)

T16val ;

// initial T16 with 0x1234

----------------------------------------------------------------------------------------------------------------------

idxm a, index Move data from specified memory to ACC by indirect method. It needs 2T to execute this

instruction.

Example: idxm a, index;

Result:

a ← [index], where index is declared by word.

Affected flags: 『N』Z 『N』C 『N』AC 『N』OV

Application Example:

-----------------------------------------------------------------------------------------------------------------------

word

…

RAMIndex ;

// declare a RAM pointer

mov

…

a, 0x5B ;

// assign pointer to an address (LSB)

// save pointer to RAM (LSB)

lb@RAMIndex, a ;

a, 0x00 ;

// assign 0x00 to an address (MSB), should be 0

hb@RAMIndex, a ; // save pointer to RAM (MSB)

idxm

a, RAMIndex ; // mov memory data in address 0x5B to ACC

------------------------------------------------------------------------------------------------------------------------

Idxm index, a Move data from ACC to specified memory by indirect method. It needs 2T to execute this

instruction.

Example: idxm index, a;

Result:

[index] ← a; where index is declared by word.

Affected flags: 『N』Z 『N』C 『N』AC 『N』OV

Page 55 of 71

PDK-DS-PMX156-EN_V106 – Dec. 12, 2018

PMC156/PMS156 Series

8bit OTP Type IO Controller

Application Example:

------------------------------------------------------------------------------------------------------------------------

word

…

RAMIndex ;

// declare a RAM pointer

mov

…

a, 0x5B ;

// assign pointer to an address (LSB)

// save pointer to RAM (LSB)

lb@RAMIndex, a ;

a, 0x00 ;

// assign 0x00 to an address (MSB), should be 0

hb@RAMIndex, a ; // save pointer to RAM (MSB)

mov

idxm

a, 0xA5 ;

RAMIndex, a ;

// mov 0xA5 to memory in address 0x5B

------------------------------------------------------------------------------------------------------------------------

Exchange data between ACC and memory

xch

M

Example: xch MEM ;

Result:

MEM ← a , a ← MEM

Affected flags: 『N』Z 『N』C 『N』AC 『N』OV

Move the ACC and flag register to memory that address specified in the stack pointer.

Example: pushaf;

pushaf

Result:

[sp] ← {flag, ACC};

sp ← sp + 2 ;

Affected flags: 『N』Z 『N』C 『N』AC 『N』OV

Application Example:

------------------------------------------------------------------------------------------------------------------------

.romadr 0x10 ;

// ISR entry address

pushaf ;

…

// put ACC and flag into stack memory

// ISR program

…

// ISR program

popaf ;

reti ;

// restore ACC and flag from stack memory

------------------------------------------------------------------------------------------------------------------------

Restore ACC and flag from the memory which address is specified in the stack pointer.

Example: popaf;

popaf

Result:

sp ← sp - 2

{Flag, ACC} ← [sp] ;

Affected flags: 『Y』Z 『Y』C 『Y』AC 『Y』OV

;

7.2 Arithmetic Operation Instructions

add

a, I

Add immediate data with ACC, then put result into ACC

Example: add a, 0x0f ;

Result: a ← a + 0fh

Affected flags: 『Y』Z 『Y』C 『Y』AC 『Y』OV

add

a, M

Add data in memory with ACC, then put result into ACC

Example: add

Result: a ← a + MEM

Affected flags: 『Y』Z 『Y』C 『Y』AC 『Y』OV

a, MEM ;

Page 56 of 71

PDK-DS-PMX156-EN_V106 – Dec. 12, 2018

PMC156/PMS156 Series

8bit OTP Type IO Controller

add

M, a

Add data in memory with ACC, then put result into memory

Example: add MEM, a;

Result: MEM ← a + MEM

Affected flags: 『Y』Z 『Y』C 『Y』AC 『Y』OV

addc a, M

addc M, a

Add data in memory with ACC and carry bit, then put result into ACC

Example: addc

a, MEM ;

Result: a ← a + MEM + C

Affected flags: 『Y』Z 『Y』C 『Y』AC 『Y』OV

Add data in memory with ACC and carry bit, then put result into memory

Example: addc

MEM, a ;

Result: MEM ← a + MEM + C

Affected flags: 『Y』Z 『Y』C 『Y』AC 『Y』OV

addc

sub

a

Add carry with ACC, then put result into ACC

Example: addc

a ;

Result: a ← a + C

Affected flags: 『Y』Z 『Y』C 『Y』AC 『Y』OV

M

Add carry with memory, then put result into memory

Example: addc

MEM ;

Result: MEM ← MEM + C

Affected flags: 『Y』Z 『Y』C 『Y』AC 『Y』OV

a, I

a, M

M, a

Subtraction immediate data from ACC, then put result into ACC.

Example: sub

a, 0x0f;

Result: a ← a - 0fh ( a + [2’s complement of 0fh] )

Affected flags: 『Y』Z 『Y』C 『Y』AC 『Y』OV

sub

Subtraction data in memory from ACC, then put result into ACC

Example: sub

a, MEM ;

Result: a ← a - MEM ( a + [2’s complement of M] )

Affected flags: 『Y』Z 『Y』C 『Y』AC 『Y』OV

sub

Subtraction data in ACC from memory, then put result into memory

Example: sub

MEM, a;

Result: MEM ← MEM - a ( MEM + [2’s complement of a] )

Affected flags: 『Y』Z 『Y』C 『Y』AC 『Y』OV

subc a, M

subc M, a

Subtraction data in memory and carry from ACC, then put result into ACC

Example: subc

a, MEM;

Result: a ← a – MEM - C

Affected flags: 『Y』Z 『Y』C 『Y』AC 『Y』OV

Subtraction ACC and carry bit from memory, then put result into memory

Example: subc

MEM, a ;

Result: MEM ← MEM – a - C

Affected flags: 『Y』Z 『Y』C 『Y』AC 『Y』OV

subc

a

Subtraction carry from ACC, then put result into ACC

Example: subc

a;

Result: a ← a - C

Affected flags: 『Y』Z 『Y』C 『Y』AC 『Y』OV

M

Subtraction carry from the content of memory, then put result into memory

Example: subc

Result: MEM ← MEM - C

Affected flags: 『Y』Z 『Y』C 『Y』AC 『Y』OV

MEM;

Page 57 of 71

PDK-DS-PMX156-EN_V106 – Dec. 12, 2018

PMC156/PMS156 Series

8bit OTP Type IO Controller

inc

M

Increment the content of memory

Example: inc MEM ;

Result: MEM ← MEM + 1

Affected flags: 『Y』Z 『Y』C 『Y』AC 『Y』OV

dec

clear

M

Decrement the content of memory

Example: dec

MEM;

Result: MEM ← MEM - 1

Affected flags: 『Y』Z 『Y』C 『Y』AC 『Y』OV

M

Clear the content of memory

Example: clear

Result: MEM ← 0

Affected flags: 『N』Z 『N』C 『N』AC 『N』OV

MEM ;

7.3 Shift Operation Instructions

sr

a

Shift right of ACC, shift 0 to bit 7

Example: sr a ;

Result: a (0,b7,b6,b5,b4,b3,b2,b1) ← a (b7,b6,b5,b4,b3,b2,b1,b0), C ← a(b0)

Affected flags: 『N』Z 『Y』C 『N』AC 『N』OV

Shift right of ACC with carry bit 7 to flag

src

sr

a

Example: src a ;

Result: a (c,b7,b6,b5,b4,b3,b2,b1) ← a (b7,b6,b5,b4,b3,b2,b1,b0), C ← a(b0)

Affected flags: 『N』Z 『Y』C 『N』AC 『N』OV

Shift right the content of memory, shift 0 to bit 7

Example: sr MEM ;

M

Result: MEM(0,b7,b6,b5,b4,b3,b2,b1) ← MEM(b7,b6,b5,b4,b3,b2,b1,b0), C ← MEM(b0)

Affected flags: 『N』Z 『Y』C 『N』AC 『N』OV

Shift right of memory with carry bit 7 to flag

src

sl

M

Example: src MEM ;

Result: MEM(c,b7,b6,b5,b4,b3,b2,b1) ← MEM (b7,b6,b5,b4,b3,b2,b1,b0), C ← MEM(b0)

Affected flags: 『N』Z 『Y』C 『N』AC 『N』OV

Shift left of ACC shift 0 to bit 0

a

Example: sl a ;

Result: a (b6,b5,b4,b3,b2,b1,b0,0) ← a (b7,b6,b5,b4,b3,b2,b1,b0), C ← a (b7)

Affected flags: 『N』Z 『Y』C 『N』AC 『N』OV

Shift left of ACC with carry bit 0 to flag

slc

sl

a

Example: slc a ;

Result: a (b6,b5,b4,b3,b2,b1,b0,c) ← a (b7,b6,b5,b4,b3,b2,b1,b0), C ← a(b7)

Affected flags: 『N』Z 『Y』C 『N』AC 『N』OV

Shift left of memory, shift 0 to bit 0

M

Example: sl MEM ;

Result: MEM (b6,b5,b4,b3,b2,b1,b0,0) ← MEM (b7,b6,b5,b4,b3,b2,b1,b0), C ← MEM(b7)

Affected flags: 『N』Z 『Y』C 『N』AC 『N』OV

Shift left of memory with carry bit 0 to flag

slc

M

Example: slc MEM ;

Result: MEM (b6,b5,b4,b3,b2,b1,b0,C) ← MEM (b7,b6,b5,b4,b3,b2,b1,b0), C ← MEM (b7)

Affected flags: 『N』Z 『Y』C 『N』AC 『N』OV

Page 58 of 71

PDK-DS-PMX156-EN_V106 – Dec. 12, 2018

PMC156/PMS156 Series

8bit OTP Type IO Controller

swap

a

Swap the high nibble and low nibble of ACC

Example: swap a ;

Result: a (b3,b2,b1,b0,b7,b6,b5,b4) ← a (b7,b6,b5,b4,b3,b2,b1,b0)

Affected flags: 『N』Z 『N』C 『N』AC 『N』OV

7.4 Logic Operation Instructions

and

or

a, I

a, M

M, a

a, I

Perform logic AND on ACC and immediate data, then put result into ACC

Example: and a, 0x0f ;

Result: a ← a & 0fh

Affected flags: 『Y』Z 『N』C 『N』AC 『N』OV

Perform logic AND on ACC and memory, then put result into ACC

Example: and

a, RAM10 ;

Result: a ← a & RAM10

Affected flags: 『Y』Z 『N』C 『N』AC 『N』OV

Perform logic AND on ACC and memory, then put result into memory

Example: and

MEM, a ;

Result: MEM ← a & MEM

Affected flags: 『Y』Z 『N』C 『N』AC 『N』OV

Perform logic OR on ACC and immediate data, then put result into ACC

Example: or

a, 0x0f ;

Result: a ← a | 0fh

Affected flags: 『Y』Z 『N』C 『N』AC 『N』OV

or

a, M

Perform logic OR on ACC and memory, then put result into ACC

Example: or

a, MEM ;

Result: a ← a | MEM

Affected flags: 『Y』Z 『N』C 『N』AC 『N』OV

or

M, a

a, I

Perform logic OR on ACC and memory, then put result into memory

Example: or

MEM, a ;

Result: MEM ← a | MEM

Affected flags: 『Y』Z 『N』C 『N』AC 『N』OV

xor

Perform logic XOR on ACC and immediate data, then put result into ACC

Example: xor

a, 0x0f ;

Result: a ← a ^ 0fh

Affected flags: 『Y』Z 『N』C 『N』AC 『N』OV

IO, a

Perform logic XOR on ACC and IO register, then put result into IO register

Example: xor

pa, a ;

Result: pa ← a ^ pa ; // pa is the data register of port A

Affected flags: 『N』Z 『N』C 『N』AC 『N』OV

xor

a, M

M, a

Perform logic XOR on ACC and memory, then put result into ACC

Example: xor

a, MEM ;

Result: a ← a ^ RAM10

Affected flags: 『Y』Z 『N』C 『N』AC 『N』OV

Perform logic XOR on ACC and memory, then put result into memory

Example:

xor

MEM, a ;

Result:

MEM ← a ^ MEM

Affected flags: 『Y』Z 『N』C 『N』AC 『N』OV

Page 59 of 71

PDK-DS-PMX156-EN_V106 – Dec. 12, 2018

PMC156/PMS156 Series

8bit OTP Type IO Controller

not

a

Perform 1’s complement (logical complement) of ACC

Example: not a ;

Result: a ← 〜a

Affected flags: 『Y』Z 『N』C 『N』AC 『N』OV

Application Example:

------------------------------------------------------------------------------------------------------------------------

mov

not

a, 0x38 ;

a ;

// ACC=0X38

// ACC=0XC7

------------------------------------------------------------------------------------------------------------------------

Perform 1’s complement (logical complement) of memory

not

M

Example: not

MEM ;

Result: MEM ← 〜MEM

Affected flags: 『Y』Z 『N』C 『N』AC 『N』OV

Application Example:

------------------------------------------------------------------------------------------------------------------------

mov

not

a, 0x38 ;

mem, a ;

mem ;

// mem = 0x38

// mem = 0xC7

------------------------------------------------------------------------------------------------------------------------

Perform 2’s complement of ACC

neg

a

Example: neg

a;

Result: a ← 〒a

Affected flags: 『Y』Z 『N』C 『N』AC 『N』OV

Application Example:

------------------------------------------------------------------------------------------------------------------------

mov

neg

a, 0x38 ;

a ;

// ACC=0X38

// ACC=0XC8

------------------------------------------------------------------------------------------------------------------------

Perform 2’s complement of memory

neg

M

Example: neg

MEM;

Result: MEM ← 〒MEM

Affected flags: 『Y』Z 『N』C 『N』AC 『N』OV

Application Example:

------------------------------------------------------------------------------------------------------------------------

mov

not

a, 0x38 ;

mem, a ;

mem ;

// mem = 0x38

// mem = 0xC8

------------------------------------------------------------------------------------------------------------------------

Page 60 of 71

PDK-DS-PMX156-EN_V106 – Dec. 12, 2018

PMC156/PMS156 Series

8bit OTP Type IO Controller

7.5 Bit Operation Instructions

set0 IO.n

set1 IO.n

set0 M.n

set1 M.n

Set bit n of IO port to low

Example: set0 pa.5 ;

Result: set bit 5 of port A to low

Affected flags: 『N』Z 『N』C 『N』AC 『N』OV

Set bit n of IO port to high

Example: set1 pb.5 ;

Result: set bit 5 of port B to high

Affected flags: 『N』Z 『N』C 『N』AC 『N』OV

Set bit n of memory to low

Example: set0 MEM.5 ;

Result: set bit 5 of MEM to low

Affected flags: 『N』Z 『N』C 『N』AC 『N』OV

Set bit n of memory to high

Example: set1 MEM.5 ;

Result: set bit 5 of MEM to high

Affected flags: 『N』Z 『N』C 『N』AC 『N』OV

7.6 Conditional Operation Instructions

ceqsn a, I

Compare ACC with immediate data and skip next instruction if both are equal.

Flag will be changed like as (a ← a - I)

Example: ceqsn

a, 0x55 ;

MEM ;

error ;

inc

goto

Result: If a=0x55, then “goto error”; otherwise, “inc MEM”.

Affected flags: 『Y』Z 『Y』C 『Y』AC 『Y』OV

Compare ACC with memory and skip next instruction if both are equal.

Flag will be changed like as (a ← a - M)

ceqsn a, M

Example: ceqsn

a, MEM;

Result: If a=MEM, skip next instruction

Affected flags: 『Y』Z 『Y』C 『Y』AC 『Y』OV

t0sn IO.n

t1sn IO.n

Check IO bit and skip next instruction if it’s low

Example: t0sn

pa.5;

Result: If bit 5 of port A is low, skip next instruction

Affected flags: 『N』Z 『N』C 『N』AC 『N』OV

Check IO bit and skip next instruction if it’s high

Example: t1sn

pa.5 ;

Result: If bit 5 of port A is high, skip next instruction

Affected flags: 『N』Z 『N』C 『N』AC 『N』OV

Page 61 of 71

PDK-DS-PMX156-EN_V106 – Dec. 12, 2018

PMC156/PMS156 Series

8bit OTP Type IO Controller

t0sn M.n

t1sn M.n

Check memory bit and skip next instruction if it’s low

Example: t0sn MEM.5 ;

Result: If bit 5 of MEM is low, then skip next instruction

Affected flags: 『N』Z 『N』C 『N』AC 『N』OV

Check memory bit and skip next instruction if it’s high

EX: t1sn MEM.5 ;

Result: If bit 5 of MEM is high, then skip next instruction

Affected flags: 『N』Z 『N』C 『N』AC 『N』OV

Increment ACC and skip next instruction if ACC is zero

izsn

dzsn

izsn

dzsn

a

Example: izsn

Result:

a;

a

←

a + 1,skip next instruction if a = 0

Affected flags: 『Y』Z 『Y』C 『Y』AC 『Y』OV

a

Decrement ACC and skip next instruction if ACC is zero

Example: dzsn

Result:

a;

A

←

A - 1,skip next instruction if a = 0

Affected flags: 『Y』Z 『Y』C 『Y』AC 『Y』OV

M

Increment memory and skip next instruction if memory is zero

Example: izsn

Result: MEM

MEM;

MEM + 1, skip next instruction if MEM= 0

←

Affected flags: 『Y』Z 『Y』C 『Y』AC 『Y』OV

M

Decrement memory and skip next instruction if memory is zero

Example: dzsn

Result: MEM

Affected flags: 『Y』Z 『Y』C 『Y』AC 『Y』OV

MEM;

←

MEM - 1, skip next instruction if MEM = 0

7.7 System control Instructions

call

label

Function call, address can be full range address space

Example: call

function1;

pc + 1

Result: [sp]

←

pc

sp

←

function1

sp + 2

Affected flags: 『N』Z 『N』C 『N』AC 『N』OV

goto label

Go to specific address which can be full range address space

Example: goto

error;

Result: Go to error and execute program.

Affected flags: 『N』Z 『N』C 『N』AC 『N』OV

Place immediate data to ACC, then return

Example: ret 0x55;

ret

I

Result:

A ← 55h

ret ;

Affected flags: 『N』Z 『N』C 『N』AC 『N』OV

Return to program which had function call

Example: ret;

Result:

sp ← sp - 2

pc ← [sp]

Affected flags: 『N』Z 『N』C 『N』AC 『N』OV

Page 62 of 71

PDK-DS-PMX156-EN_V106 – Dec. 12, 2018

PMC156/PMS156 Series

8bit OTP Type IO Controller

reti

Return to program that is interrupt service routine. After this command is executed, global

interrupt is enabled automatically.

Example: reti;

Affected flags: 『N』Z 『N』C 『N』AC 『N』OV

nop

No operation

Example: nop;

Result: nothing changed

Affected flags: 『N』Z 『N』C 『N』AC 『N』OV

pcadd

a

Next program counter is current program counter plus ACC.

Example: pcadd a;

Result: pc ← pc + a

Affected flags: 『N』Z 『N』C 『N』AC 『N』OV

Application Example:

------------------------------------------------------------------------------------------------------------------------

…

mov

pcadd

goto

…

a, 0x02 ;

a ;

// PC <- PC+2

// jump here

err1 ;

correct ;

err2 ;

err3 ;

correct:

// jump here

…

------------------------------------------------------------------------------------------------------------------------

Enable global interrupt enable

engint

Example: engint;

Result: Interrupt request can be sent to CPU

Affected flags: 『N』Z 『N』C 『N』AC 『N』OV

Disable global interrupt enable

disgint

stopsys

stopexe

Example: disgint ;

Result: Interrupt request is blocked from CPU

Affected flags: 『N』Z 『N』C 『N』AC 『N』OV

System halt.

Example: stopsys;

Result: Stop the system clocks and halt the system

Affected flags: 『N』Z 『N』C 『N』AC 『N』OV

CPU halt. The oscillator module is still active to output clock, however, system clock is disabled

to save power.

Example: stopexe;

Result: Stop the system clocks and keep oscillator modules active.

Affected flags: 『N』Z 『N』C 『N』AC 『N』OV

Reset the whole chip, its operation will be same as hardware reset.

Example: reset;

reset

Result: Reset the whole chip.

Affected flags: 『N』Z 『N』C 『N』AC 『N』OV

Page 63 of 71

PDK-DS-PMX156-EN_V106 – Dec. 12, 2018

PMC156/PMS156 Series

8bit OTP Type IO Controller

wdreset

Reset Watchdog timer.

Example: wdreset ;

Result: Reset Watchdog timer.

Affected flags: 『N』Z 『N』C 『N』AC 『N』OV

7.8 Summary of Instructions Execution Cycle

goto, call, idxm, pcadd, ret, reti

2T

1T

Condition is fulfilled

ceqsn, cneqsn,t0sn, t1sn, dzsn, izsn

Condition is not fulfilled

Others

Page 64 of 71

PDK-DS-PMX156-EN_V106 – Dec. 12, 2018

PMC156/PMS156 Series

8bit OTP Type IO Controller

7.9 Summary of affected flags by Instructions

Instruction

mov a, I

Z

-

C

-

AC OV Instruction

Z

-

C

-

AC OV Instruction

Z

Y

-

C

-

AC OV

-

mov M, a

mov IO, a

idxm a, index

pushaf

-

mov a, M

ldt16 word

idxm index, a

popaf

-

mov a, IO

stt16 word

Y

-

xch

M

-

Y

-

Y

-

Y

-

Y

-

add a, I

Y

-

Y

-

Y

-

Y

-

add a, M

addc M, a

sub a, I

Y

-

Y

-

Y

-

Y

-

add M, a

addc a, M

addc

a

addc

M

sub a, M

sub M, a

subc a, M

subc M, a

subc

dec

src

a

subc

clear

M

inc

sr a

src

sl

M

a

sr

M

-

Y

-

sl

a

-

slc

a

-

M

-

slc

and

M

-

swap

and

a

-

and

a, I

Y

-

a, M

Y

-

M, a

Y

-

or a, I

-

or a, M

-

or M, a

-

xor

neg

a, I

-

xor

not

neg

IO, a

-

xor

not

a, M

-

M, a

a

-

a

Y

-

M

-

M

-

set0 IO.n

set1 M.n

t0sn IO.n

t1sn M.n

-

set1 IO.n

ceqsn a, I

t1sn IO.n

-

set0 M.n

ceqsn a, M

t0sn M.n

-

Y

-

Y

-

Y

-

Y

-

Y

-

Y

-

Y

-

Y

-

izsn

dzsn

ret

a

Y

-

Y

-

Y

-

Y

-

dzsn

call

a

Y

-

Y

-

Y

-

Y

-

izsn

M

Y

-

Y

-

Y

-

Y

-

M

label

goto label

reti

I

ret

-

nop

-

pcadd

a

-

engint

-

disgint

reset

-

stopsys

wdreset

-

stopexe

-

7.10 BIT definition

(1) Bit defined: Only addressed at 0x00 ~ 0x0F

(2) WORD defined : Only addressed at 0x00 ~ 0x1E

Page 65 of 71

PDK-DS-PMX156-EN_V106 – Dec. 12, 2018

PMC156/PMS156 Series

8bit OTP Type IO Controller

8. Code Options

Option

Selection Description

Enable

Disable

4.0V

3.5V

3.0V

2.75V

2.5V

2.2V

2.0V

1.8V

Yes

Security Enable

Security

Security Disable

Select LVR = 4.0V

Select LVR = 3.5V

Select LVR = 3.0V

Select LVR = 2.75V

LVR

Select LVR = 2.5V

Select LVR = 2.2V

Select LVR = 2.0V

Select LVR = 1.8V

reach normal operating voltage quickly within 20 mS

can’t reach normal operating voltage quickly within 20 mS

Under_20mS_VDD_OK

No

VDD/2 LCD bias voltage generator enabled, PB[1,2,5,6]

are VDD/2 if input mode

PB_1256

PA_1234

LCD

(please refer to MISC.4)

VDD/2 LCD bias voltage generator enabled, PA[1,2,3,4]

are VDD/2 if input mode

Page 66 of 71

PDK-DS-PMX156-EN_V106 – Dec. 12, 2018

PMC156/PMS156 Series

8bit OTP Type IO Controller

9. Special Notes

This chapter is to remind user who use PMC153/PMS153 series IC in order to avoid frequent errors upon

operation.

9.1. Warning

User must read all application notes of the IC by detail before using it. Please download the related application

notes from the following link: http://www.padauk.com.tw/tw/technical/index.aspx

9.2. Using IC

9.2.1. IO pin usage and setting

(1) IO pin as digital input



When IO is set as digital input, the level of Vih and Vil would changes with the voltage and

temperature. Please follow the minimum value of Vih and the maximum value of Vil.

The value of internal pull high resistor would also changes with the voltage, temperature and pin

voltage. It is not the fixed value.

(2) If IO pin is set to be digital input and enable wake-up function



Configure IO pin as input

Set corresponding bit to “1” in PADIER

(3) PA5 is set to be output pin



PA5 can be set to be Open-Drain output pin only, output high requires adding pull-high resistor.

(4) PA5 is set to be PRST# input pin



No internal pull-high resistor for PA5

Configure PA5 as input

Set CLKMD.0=1 to enable PA5 as PRST# input pin

(5) PA5 is set to be input pin and to connect with a push button or a switch by a long wire



Needs to put a >10Ω resistor in between PA5 and the long wire

Avoid using PA5 as input in such application.

(5) PA7 and PA6 as external crystal oscillator



Configure PA7 and PA6 as input

Disable PA7 and PA6 internal pull-high resistor

Configure PADIER register to set PA6 and PA7 as analog input

EOSCR register bit [6:5] selects corresponding crystal oscillator frequency :



01 : for lower frequency, ex : 32kHz

10 : for middle frequency, ex : 455kHz、1MHz

11 : for higher frequency, ex : 4MHz



Program EOSCR.7 =1 to enable crystal oscillator

Ensure EOSC working well before switching from IHRC or ILRC to EOSC

Page 67 of 71

PDK-DS-PMX156-EN_V106 – Dec. 12, 2018

PMC156/PMS156 Series

8bit OTP Type IO Controller

Note: Please read the PMC-APN013 carefully. According to PMC-APN013, the crystal oscillator should be used

reasonably. If the following situations happen to cause IC start-up slowly or non-startup, PADAUK Technology is

not responsible for this: the quality of the user's crystal oscillator is not good, the usage conditions are

unreasonable, the PCB cleaner leakage current, or the PCB layouts are unreasonable.

9.2.2. Interrupt

(1) When using the interrupt function, the procedure should be:

Step1: Set INTEN register, enable the interrupt control bit

Step2: Clear INTRQ register

Step3: In the main program, using ENGINT to enable CPU interrupt function

Step4: Wait for interrupt. When interrupt occurs, enter to Interrupt Service Routine

Step5: After the Interrupt Service Routine being executed, return to the main program

* Use DISGINT in the main program to disable all interrupts

* When interrupt service routine starts, use PUSHAF instruction to save ALU and FLAG

register. POPAF instruction is to restore ALU and FLAG register before RETI as below:

void Interrupt (void)

// Once the interrupt occurs, jump to interrupt service routine

// enter DISGINT status automatically, no more interrupt is

{

accepted

PUSHAF;

…

POPAF;

}

// RETI will be added automatically. After RETI being executed, ENGINT status

will be restored

(2) INTEN and INTRQ have no initial values. Please set required value before enabling interrupt function

9.2.3. System clock switching

(1) System clock can be switched by CLKMD register. Please notice that, NEVER switch the system clock and

turn off the original clock source at the same time. For example: When switching from clock A to clock B,

please switch to clock B first; and after that turn off the clock A oscillator through CLKMD.



Case 1 : Switch system clock from ILRC to IHRC/2

CLKMD

=

0x36;

0;

// switch to IHRC, ILRC can not be disabled here

CLKMD.2 =

// ILRC can be disabled at this time



Case 2 : Switch system clock from ILRC to EOSC

CLKMD

=

0xA6;

0;

// switch to EOSC, ILRC can not be disabled here

CLKMD.2 =

// ILRC can be disabled at this time



ERROR. Switch ILRC to IHRC and turn off ILRC simultaneously

CLKMD 0x50; // MCU will hang

=

(2) Please ensure the EOSC oscillation has established before switching from ILRC or IHRC to EOSC. MCU

will not check its status. Please wait for a while after enabling EOSC. System clock can be switched to

EOSC afterwards. Otherwise, MCU will hang. The example for switching system clock from ILRC to 4MHz

EOSC after boot up is as below:

Page 68 of 71

PDK-DS-PMX156-EN_V106 – Dec. 12, 2018

PMC156/PMS156 Series

8bit OTP Type IO Controller

.ADJUST_IC

DISABLE

0;

Enable, 4MHz;

CLKMD.1 =

// turn off WDT for executing delay instruction.

$

EOSCR

// 4MHz EOSC start to oscillate 荡。

// Delay for EOSC establishment

$ T16M EOSC,/1,BIT10

Word Count = 0;

Stt16 Count;

Intrq.T16 = 0;

wait1

Intrq.T16;

CLKMD

=

0xA4;

0;

// ILRC -> EOSC;

CLKMD.2 =

// turn off ILRC but not necessarily routine

The delay duration should be adjusted in accordance with the characteristic of the crystal and PCB.To

measure the oscillator signal by the oscilloscope, please select (x10) on the probe and measure through

PA6(X2) pin to avoid the interference on the oscillator.

9.2.4. Power down mode, wakeup and watchdog

(1) Watchdog will be inactive once ILRC is disabled

(2) Please turn off watchdog before executing STOPSYS or STOPEXE instruction, otherwise IC will be reset

due to watchdog timeout. It is the same as in ICE emulation.

(3) The clock source of Watchdog is ILRC if the fast wakeup is disabled; otherwise, the clock source of

Watchdog will be the system clock and the reset time from watchdog becomes much shorter. It is

recommended to disable Watchdog and enable fast wakeup before entering STOPSYS mode. When the

system is waken up from power down mode, please firstly disable fast wakeup function, and then enable

Watchdog. It is to avoid system to be reset after being waken up.

(4) If enable Watchdog during programming and also wants the fast wakeup, the example as below:

CLKMD.En_WatchDog

=

0;

// disable watchdog timer

$ MISC

stopexe;

nop;

Fast_Wake_Up;

$ MISC

Wdreset;

WT_xx;

// Reset Watchdog time to normal wake-up

// enable watchdog timer

CLKMD.En_WatchDog

=

1;

9.2.5. TIMER time out

When select $ INTEGS BIT_R (default value) and T16M counter BIT8 to generate interrupt, if T16M counts

from 0, the first interrupt will occur when the counter reaches to 0x100 (BIT8 from 0 to 1) and the second

interrupt will occur when the counter reaches 0x300 (BIT8 from 0 to 1). Therefore, selecting BIT8 as 1 to

generate interrupt means that the interrupt occurs every 512 counts. Please notice that if T16M counter is

restarted, the next interrupt will occur once Bit8 turns from 0 to 1.

If select $ INTEGS BIT_F(BIT triggers from 1 to 0) and T16M counter BIT8 to generate interrupt, the T16M

counter changes to an interrupt every 0x200/0x400/0x600/. Please pay attention to two differences with

setting INTEGS methods.

Page 69 of 71

PDK-DS-PMX156-EN_V106 – Dec. 12, 2018

PMC156/PMS156 Series

8bit OTP Type IO Controller

9.2.6. LVR

(1) VDD must reach or above 2.0V for successful power-on process; otherwise IC will be inactive.

(2) The setting of LVR (1.8V, 2.0V, 2.2V etc) will be valid just after successful power-on process.

(3) User can set EOSCR.0 as “1” to disable LVR. However, VDD must be kept as exceeding the lowest

working voltage of chip; Otherwise IC may work abnormally.

9.2.7. IHRC

(1) The IHRC frequency calibration is performed when IC is programmed by the writer.

(2) Because the characteristic of the Epoxy Molding Compound (EMC) would some degrees affects the IHRC

frequency (either for package or COB), if the calibration is done before molding process, the actual IHRC

frequency after molding may be deviated or becomes out of spec. Normally , the frequency is getting slower

a bit.

(3) It usually happens in COB package or Quick Turnover Programming (QTP). And PADAUK would not take

any responsibility for this situation.

(4) Users can make some compensatory adjustments according to their own experiences. For example, users

can set IHRC frequency to be 0.5% ~ 1% higher and aim to get better re-targeting after molding.

9.2.8. LCD COM pin application

(1) There are two groups of LCD COM IO selectable for PMC156/PMS156, they are

PA_1234(PA1/COM1,PA2/COM2,PA3/COM3,PA4/COM4) and

PB_1256(PB1/COM0A,PB2/COM1A,PB5/COM2A,PB6/COM3A).

(2) In the practical application, only one group is actually used. User can select one of the groups in Code

Option where the LVR value is also selectable before program compiling. The code option is shown as

below. Please notice that once the code option is confirmed, any change will be unacceptable in the next

programming.

Page 70 of 71

PDK-DS-PMX156-EN_V106 – Dec. 12, 2018

PMC156/PMS156 Series

8bit OTP Type IO Controller

9.2.9. Program writing

There are 6 pins for using the writer to program: PA3, PA4, PA5, PA6, VDD and GND.

Please use PDK3S-P-002 for program real chip and just use the CN40 jumper (at the back for the writer) with

putting the PMC156/PMS156- SOP14/16/20 & SOP18/DIP18 IC in the top of the Textool . Other packages

could be programmed by connecting the signals correspondingly. All the signals of the left side of the jumpers

are the same and as the descriptions at the left bottom corner. They are VDD, PA0(not used), PA3, PA4, PA5,

PA6, PA7(not used), and GND).

If user use PDK5S-P-003 or above to program, please follow the instructions for connecting jumpers.

 Special notes about voltage and current while Multi-Chip-Package(MCP) or On-Board Programming

(1)

(2)

(3)

PA5 (V_PP) may be higher than 11V.

_DDmay be higher than 6.5V, and its maximum current may reach about 20mA.

All other signal pins level (except GND) are the same as V_DD.

V

User should confirm when using this product in MCP or On-Board Programming, the peripheral circuit or

components will not be destroyed or limit the above voltages.

9.3. Using ICE

Please use PDK5S-I-S01/2(B) ICE to emulate PMC156/PMS156. Please note in the simulation:

 PDK5S-I-S01/2(B) doesn’t support the instruction NMOV/SWAP/NADD/COMP with RAM

 PDK5S-I-S01/2(B) doesn’t support the dynamic setting of function misc.4 (Only fix to 0 or 1)

 Fast Wakeup time is different from PDK5S-I-S01/2(B): 128 SYSCLK, PMC156/PMS156: refer to 5.8.3

 Watch dog time out period is different from PDK5S-I-S01/2(B):

WDT period

misc[1:0]=00

misc[1:0]=01

misc[1:0]=10

misc[1:0]=11

PDK5S-I-S01/2(B)

2048 * T_ILRC

PMC156/PMS156

8K * T_ILRC

4096 * T_ILRC

16K * T_ILRC

16384 * T_ILRC

256 * T_ILRC

64K * T_ILRC

256K * T_ILRC

Page 71 of 71

PDK-DS-PMX156-EN_V106 – Dec. 12, 2018


型号：	PMC156-S16
厂家：	PADAUK Technology
描述：	8bit OTP Type IO Controller
文件：	总71页 (文件大小：1289K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

PMC156-S16 [PADAUK]

相关型号：

SI9130DB

SI9135LG-T1

SI9135LG-T1-E3

SI9135_11

SI9136_11

SI9130CG-T1-E3

SI9130LG-T1-E3

SI9130_11

SI9137

SI9137DB