PMS15B-D08 [PADAUK]
8bit OTP Type IO Controller;型号: | PMS15B-D08 |
厂家: | PADAUK Technology |
描述: | 8bit OTP Type IO Controller |
文件: | 总68页 (文件大小:1519K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
PMS15B/PMS150G Family
8bit OTP Type IO Controller
Data Sheet
Version 0.03 – July 24, 2020
Copyright 2020 by PADAUK Technology Co., Ltd., all rights reserved
6F-6, No.1, Sec. 3, Gongdao 5th Rd., Hsinchu City 30069, Taiwan, R.O.C.
TEL: 886-3-572-8688 www.padauk.com.tw
PMS15B/PMS150G Family
8 bit OTP Type IO Controller
IMPORTANT NOTICE
PADAUK Technology reserves the right to make changes to its products or to terminate
production of its products at any time without notice. Customers are strongly
recommended to contact PADAUK Technology for the latest information and verify
whether the information is correct and complete before placing orders.
PADAUK Technology products are not warranted to be suitable for use in life-support
applications or other critical applications. PADAUK Technology assumes no liability for
such applications. Critical applications include, but are not limited to, those that may
involve potential risks of death, personal injury, fire or severe property damage.
PADAUK Technology assumes no responsibility for any issue caused by a customer’s
product design. Customers should design and verify their products within the ranges
guaranteed by PADAUK Technology. In order to minimize the risks in customers’ products,
customers should design a product with adequate operating safeguards.
©Copyright 2020, PADAUK Technology Co. Ltd
Page 2 of 68
PDK-DS-PMS15B/PMS150G-EN-V003–Jul. 24, 2020
PMS15B/PMS150G Family
8 bit OTP Type IO Controller
Table of Contents
1. Features...............................................................................................................................7
1.1.
1.2.
1.3.
1.4.
Special features ....................................................................................................................7
System Features...................................................................................................................7
CPU Features .......................................................................................................................7
Package Information .............................................................................................................7
2. General Description and Block Diagram ..........................................................................8
3. Pin Functional Description ................................................................................................9
4. Device Characteristics .....................................................................................................11
4.1.
4.2.
4.3.
4.4.
4.5.
4.6.
4.7.
4.8.
4.9.
DC/AC Characteristics ........................................................................................................11
Absolute Maximum Ratings.................................................................................................12
Typical IHRC Frequency vs. VDD (calibrated to 16MHz).....................................................13
Typical ILRC Frequency vs. VDD........................................................................................13
Typical IHRC Frequency vs. Temperature (calibrated to 16MHz)........................................14
Typical ILRC Frequency vs. Temperature...........................................................................14
Typical Operating Current vs. VDD and CLK=IHRC/n.........................................................15
Typical Operating Current vs. VDD and CLK=ILRC/n..........................................................15
Typical IO pull high resistance.............................................................................................16
4.10. Typical IO pull high resistance vs. Temperature, VDD=5V ..................................................16
4.11. Typical IO pull Low resistance.............................................................................................17
4.12. Typical IO pull low resistance vs. Temperature, VDD=5V....................................................17
4.13. Typical IO driving current (IOH) and sink current (IOL) ...........................................................18
4.14. Typical IO input high/low threshold voltage (VIH/VIL) ............................................................18
4.15. Typical power down current (IPD) and power save current (IPS)............................................19
5. Functional Description.....................................................................................................20
5.1.
5.2.
Program Memory – OTP .....................................................................................................20
Boot Procedure...................................................................................................................20
5.2.1. Timing charts for reset conditions ...........................................................................21
5.3.
5.4.
Data Memory – SRAM ........................................................................................................22
Oscillator and clock.............................................................................................................22
5.4.1. Internal High RC oscillator and Internal Low RC oscillator......................................22
5.4.2. IHRC calibration .....................................................................................................22
©Copyright 2020, PADAUK Technology Co. Ltd
Page 3 of 68
PDK-DS-PMS15B/PMS150G-EN-V003–Jul. 24, 2020
PMS15B/PMS150G Family
8 bit OTP Type IO Controller
5.4.3. IHRC Frequency Calibration and System Clock......................................................23
5.4.4. System Clock and LVR levels.................................................................................24
5.4.5. System Clock Switching .........................................................................................25
5.5.
Comparator.........................................................................................................................26
5.5.1. Internal reference voltage (Vinternal R)........................................................................27
5.5.2. Using the comparator .............................................................................................29
5.5.3. Using the comparator and band-gap 1.20V ............................................................29
5.6.
5.7.
16-bit Timer (Timer16) ........................................................................................................31
8-bit timer (Timer2) with PWM generation...........................................................................32
5.7.1. Using the Timer2 to generate periodical waveform.................................................33
5.7.2. Using the Timer2 to generate 8-bit PWM waveform................................................34
5.7.3. Using the Timer2 to generate 6-bit PWM waveform................................................36
5.8.
5.9.
Watchdog Timer..................................................................................................................37
Interrupt ..............................................................................................................................38
5.10. Power-Save and Power-Down ............................................................................................40
5.10.1. Power-Save mode (“stopexe”)................................................................................41
5.10.2. Power-Down mode (“stopsys”) ...............................................................................42
5.10.3. Wake-up.................................................................................................................42
5.11. IO Pins................................................................................................................................43
5.12. Reset ..................................................................................................................................44
6. IO Registers.......................................................................................................................45
6.1.
6.2.
6.3.
6.4.
6.5.
6.6.
6.7.
6.8.
6.9.
ACC Status Flag Register (flag), IO address = 0x00 ...........................................................45
Stack Pointer Register (sp), IO address = 0x02...................................................................45
Clock Mode Register (clkmd), IO address = 0x03 ...............................................................45
Interrupt Enable Register (inten), IO address = 0x04...........................................................45
Interrupt Request Register (intrq), IO address = 0x05 .........................................................46
Timer 16 mode Register (t16m), IO address = 0x06............................................................46
External Oscillator setting Register (eoscr, write only), IO address = 0x0a..........................46
Interrupt Edge Select Register (integs), IO address = 0x0c.................................................47
Port A Digital Input Enable Register (padier), IO address = 0x0d........................................47
6.10. Port A Data Registers (pa), IO address = 0x10 ...................................................................47
6.11. Port A Control Registers (pac), IO address = 0x11..............................................................47
6.12. Port A Pull-High Registers (paph), IO address = 0x12.........................................................47
6.13. Port A Pull-Low Registers (papl), IO address = 0x13...........................................................47
6.14. MISC Register (misc), IO address = 0x1b ...........................................................................48
6.15. Comparator Control Register (gpcc), IO address = 0x1A.....................................................48
6.16. Comparator Selection Register (gpcs), IO address = 0x1E .................................................49
©Copyright 2020, PADAUK Technology Co. Ltd
Page 4 of 68
PDK-DS-PMS15B/PMS150G-EN-V003–Jul. 24, 2020
PMS15B/PMS150G Family
8 bit OTP Type IO Controller
6.17. Timer2 Control Register (tm2c), IO address = 0x1C............................................................49
6.18. Timer2 Counter Register (tm2ct), IO address = 0x1D..........................................................49
6.19. Timer2 Bound Register (tm2b), IO address = 0x09 .............................................................50
6.20. Timer2 Scalar Register (tm2s), IO address = 0x17..............................................................50
7. Instructions.......................................................................................................................51
7.1.
7.2.
7.3.
7.4.
7.5.
7.6.
7.7.
7.8.
7.9.
Data Transfer Instructions...................................................................................................52
Arithmetic Operation Instructions ........................................................................................55
Shift Operation Instructions.................................................................................................56
Logic Operation Instructions................................................................................................57
Bit Operation Instructions....................................................................................................59
Conditional Operation Instructions ......................................................................................59
System control Instructions .................................................................................................60
Summary of Instructions Execution Cycle ...........................................................................62
Summary of affected flags by Instructions...........................................................................63
7.10. BIT definition.......................................................................................................................63
8. Code Options ....................................................................................................................64
9. Special Notes....................................................................................................................65
9.1.
9.2.
Warning...............................................................................................................................65
Using IC..............................................................................................................................65
9.2.1. IO pin usage and setting.........................................................................................65
9.2.2. Interrupt..................................................................................................................65
9.2.3. System clock switching...........................................................................................66
9.2.4. Power down mode, wakeup and watchdog.............................................................66
9.2.5. TIMER time out.......................................................................................................66
9.2.6. IHRC ......................................................................................................................66
9.2.7. LVR ........................................................................................................................67
9.2.8. Program writing ......................................................................................................67
9.3.
Using ICE............................................................................................................................68
©Copyright 2020, PADAUK Technology Co. Ltd
Page 5 of 68
PDK-DS-PMS15B/PMS150G-EN-V003–Jul. 24, 2020
PMS15B/PMS150G Family
8 bit OTP Type IO Controller
Revision History:
Revision
Date
2019/11/14 Preliminary version
1. Amend Chapter 3 SOP8 and DIP8
Description
0.00
2. Add Major Differences Table between PMS150G and PMS150C
3. Amend Section 1.2 System Features
4. Amend Section 4.1: fIHRC
0.01
2019/11/28
5. Amend Section 4.5, 4.6, 4.8, 4.9, 4.10, 4.12, 4.14
6. Amend Section 5.2, 5.7.1, 5.7.2, 5.7.3
7. Amend Section 6.13
8. Amend Chapter 8 PA5 Open-Drain
1. Amend Major Differences Table between PMS150G and PMS15A/PMS150C
0.02
0.03
2020/04/14 2. Amend Section 1.2, 5.10.3, 5.11, 6.9, 6.14, 9.2.7, 9.2.8, 9.3
3. Delete the super boot-up / wake-up function
1. Add IC chip of PMS15B
2020/07/24 2. Add Section 5.4.5 System Clock Switching
3. Amend Section 1.2, 5.1, 5.5.2, 6.9, 6.16
Major Differences Table between
PMS15B/PMS150G and PMS15A/PMS150C
Item
Function
Operating Voltage
Range
PMS15B/PMS150G
PMS15A/PMS150C
1
1.8 ~ 5.5V
2.0 ~ 5.5V
2
3
4
Max Fsysclk
2MHz
8MHz
Input Option
PA5 Mode
Pull-High / Pull-Low
Normal IO / Open-Drain
Pull-High ONLY
Open-Drain
Programming
Writer
PDK-3S-P002 /
PDK-5S-P003
Normal / Low
5
6
PDK-5S-P003
Normal
IO Drive Option
©Copyright 2020, PADAUK Technology Co. Ltd
Page 6 of 68
PDK-DS-PMS15B/PMS150G-EN-V003–Jul. 24, 2020
PMS15B/PMS150G Family
8 bit OTP Type IO Controller
1. Features
1.1. Special features
General purpose series
Not supposed to use in AC RC step-down powered or high EFT requirement applications.
PADAUK assumes no liability if such kind of applications can not pass the safety regulation tests.
Operating temperature range: -20°C ~ 70°C
1.2. System Features
Series
PMS150G
PMS15B
Program memory
1KW
Data memory (byte)
Maximum IO quantity
64
64
6
6
0.5KW
One hardware 16-bit timer
One hardware 8-bit timer with PWM generation
One general purpose comparator
Support fast/normal wake-up
Every IO pin can be configured to enable wake-up function
6 IO pins with pull-high/pull-low resistor
Clock sources: internal high RC oscillator and internal low RC oscillator
Eight levels of LVR: 4.0V, 3.5V, 3.0V, 2.75V, 2.5V, 2.2V, 2.0V, 1.8V
One external interrupt pin
1.3. CPU Features
One processing unit operating mode
79 Powerful instructions
Most instructions are 1T execution cycle
Programmable stack pointer and adjustable stack level
Direct and indirect addressing modes for data access. Data memories are available for use as an index
pointer of Indirect addressing mode
IO space and memory space are independent
1.4. Package Information
PMS150GSeries
PMS150G- U06: SOT23-6 (60mil);
PMS150G- S08: SOP8 (150mil);
PMS150G- D08: DIP8 (300mil)
PMS15B Series
PMS15B- U06: SOT23-6 (60mil);
PMS15B- S08: SOP8 (150mil);
PMS15B- D08: DIP8 (300mil)
©Copyright 2020, PADAUK Technology Co. Ltd
Page 7 of 68
PDK-DS-PMS15B/PMS150G-EN-V003–Jul. 24, 2020
PMS15B/PMS150G Family
8 bit OTP Type IO Controller
2. General Description and Block Diagram
The PMS15B/PMS150G is an IO-Type, fully static, OTP-based CMOS 8-bit microcontroller; it employs RISC
architecture and most the instructions are executed in one cycle except that few instructions are two cycles that
handle indirect memory access.
1KW bits OTP program memory and 64 bytes data SRAM are inside. Besides, one hardware 16-bit timer, one
hardware 8-bit timer with PWM generation and one general purpose comparator are also provided in the
PMS15B/PMS150G.
©Copyright 2020, PADAUK Technology Co. Ltd
Page 8 of 68
PDK-DS-PMS15B/PMS150G-EN-V003–Jul. 24, 2020
PMS15B/PMS150G Family
8 bit OTP Type IO Controller
3. Pin Functional Description
Pin & Buffer
Pin Name
Type
Description
This pin can be used as:
(1) Bit 7 of port A. It can be configured as digital input or two-state output, with
pull-high or pull-low resistor.
IO
ST /
PA7 /
(2) Minus input source of comparator.
CIN-
CMOS /
Analog
When this pin is configured as analog input, please use bit 7 of register padier to
disable the digital input to prevent current leakage. This pin can be used to
wake-up system during sleep mode; however, wake-up function is also disabled if
bit 7 of padier register is “0”.
This pin can be used as:
(1) Bit 6 of port A. It can be configured as digital input or two-state output, with
pull-high or pull-low resistor.
IO
PA6 /
ST /
(2) Minus input source of comparator.
CIN-
CMOS /
Analog
When this pin is configured as analog input, please use bit 6 of register padier to
disable the digital input to prevent current leakage. This pin can be used to
wake-up system during sleep mode; however, wake-up function is also disabled if
bit 6 of padier register is “0”.
©Copyright 2020, PADAUK Technology Co. Ltd
Page 9 of 68
PDK-DS-PMS15B/PMS150G-EN-V003–Jul. 24, 2020
PMS15B/PMS150G Family
8 bit OTP Type IO Controller
Pin & Buffer
Type
Pin Name
Description
The functions of this pin can be:
(1) Bit 5 of port A. It can be configured as digital input or two-state output, with
pull-high or pull-low resistor.
IO
(2) Hardware reset.
PA5 /
ST /
This pin can be used to wake-up system during sleep mode; however, wake-up
function is also disabled if bit 5 of padier register is “0”.
Please put 33Ω resistor in series to have high noise immunity when this pin is in
input mode.
PRSTB
CMOS
This pin can be used as:
(1) Bit 4 of port A. It can be configured as digital input or two-state output, with
pull-high or pull-low resistor.
IO
PA4 /
CIN+ /
(2) Plus input source of comparator.
ST /
(3) Minus input source of comparator.
CIN- /
CMOS /
Analog
(4) Output of 8-bit Timer2 (TM2)
TM2PWM
When this pin is configured as analog input, please use bit 4 of register padier to
disable the digital input to prevent current leakage. This pin can be used to
wake-up system during sleep mode; however, wake-up function is also disabled if
bit 4 of padier register is “0”.
This pin can be used as:
(1) Bit 3 of port A. It can be configured as digital input or two-state output, with
pull-high or pull-low resistor.
IO
PA3 /
CIN- /
(2) Minus input source of comparator.
ST /
(3) Output of 8-bit Timer2 (TM2)
CMOS /
Analog
TM2PWM
When this pin is configured as analog input, please use bit 3 of register padier to
disable the digital input to prevent current leakage. This pin can be used to
wake-up system during sleep mode; however, wake-up function is also disabled if
bit 3 of padier register is “0”.
The functions of this pin can be:
(1) Bit 0 of port A. It can be configured as digital input or output with pull-up or
pull-low resistor.
PA0 /
INT0 /
CO
IO
(2) External interrupt line 0. Both rising edge and falling edge are accepted to
request interrupt service.
ST /
CMOS
(3) Output of comparator
This pin can be used to wake up system during sleep mode; however, wake-up
function from this pin is also disabled when bit 0 of padier register is “0”.
VDD
GND
Positive power
Ground
Notes: IO: Input/Output; ST: Schmitt Trigger input; Analog: Analog input pin; CMOS: CMOS voltage level
©Copyright 2020, PADAUK Technology Co. Ltd
Page 10 of 68
PDK-DS-PMS15B/PMS150G-EN-V003–Jul. 24, 2020
PMS15B/PMS150G Family
8 bit OTP Type IO Controller
4. Device Characteristics
4.1. DC/AC Characteristics
All data are acquired under the conditions of VDD=5.0V, fSYS=2MHz unless noted.
Symbol
VDD
Description
Operating Voltage
Min
1.8*
-5
Typ
Max
5.5
5
Unit
V
Conditions
* Subject to LVR tolerance
Low Voltage Reset tolerance
System clock (CLK)* =
IHRC/8
%
LVR%
0
2M
1.9
Hz
VDD ≧ 1.8V
fSYS
ILRC
57KHz
1.8
VDD =5.0V
VPOR Power On Reset Voltage
1.7
V
fSYS=IHRC/16=1MIPS@3.3V
fSYS=ILRC=59KHz@3.3V
0.3
mA
uA
IOP
IPD
Operating Current
22
Power Down Current
1
uA
fSYS= 0Hz, VDD =3.3V
(by stopsys command)
VDD =3.3V;
Power Save Current
IPS
3
uA
Band-gap, LVR, IHRC are
OFF, ILRC module is ON.
(by stopexe command)
VIL
VIH
IOL
IOH
VIN
Input low voltage for IO lines
Input high voltage for IO lines
IO lines sink current
0
0.7 VDD
19
0.1 VDD
VDD
V
V
21
24
mA
mA
V
VDD=5.0V, VOL=0.5V
VDD=5.0V, VOH=4.5V
IO lines drive current
Input voltage
-11
-13
-16
-0.3
VDD+0.3
1
VDD +0.3≧VIN≧ -0.3
IINJ (PIN) Injected current on pin
mA
KΩ
KΩ
RPH
RPL
Pull-high Resistance
Pull-low Resistance
76
66
84
77
96
86
@25oC, VDD =2.0V~5.5V,
15.66*
16*
16.34*
Frequency of IHRC after
fIHRC
MHz
VDD =2.0V~5.5V,
calibration*
15.10*
16*
57*
16.90*
-20oC<Ta<70oC*
VDD =5.0V, -20oC <Ta<70oC*
VDD =5.0V
fILRC
tINT
Frequency of ILRC*
KHz
ns
Interrupt pulse width
30
In power-down mode.
misc[1:0]=00 (default)
misc[1:0]=01
VDR
RAM data retention voltage*
1.5
V
8k
16k
64k
256k
ILRC
clock
tWDT
Watchdog timeout period
misc[1:0]=10
period
misc[1:0]=11
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Page 11 of 68
PDK-DS-PMS15B/PMS150G-EN-V003–Jul. 24, 2020
PMS15B/PMS150G Family
8 bit OTP Type IO Controller
Symbol
Description
System boot-up period from
power-on (Fast boot up)
System boot-up period from
power-on (Slow boot up)
Wake-up time for fast wake-up
(misc.5=1)
Min
Typ
850
850
51
Max
Unit
Conditions
@ VDD =5V
us
@ VDD =2.5V
tSBP
@ VDD =5V
ms
51
@ VDD =2.5V
Where TILRC is the clock
period of ILRC
Where TILRC is the clock
period of ILRC
@ VDD =5V
32
TILRC
TILRC
tWUP
Wake-up time for normal wake-up
(misc.5=0)
2048
tRST
External reset pulse width
120
0
us
mV
V
CPos Comparator offset*
±10
±20
VDD+1.5
500
CPcm Comparator input common mode*
CPspt Comparator response time*
100
2.5
20
ns
Both Rising and Falling
VDD = 3.3V
Stable time to change comparator
CPmc
mode
7.5
us
CPcs Comparator current consumption
uA
*These parameters are for design reference, not tested for every chip.
4.2. Absolute Maximum Ratings
Supply Voltage ……………………………......
1.8V ~ 5.5V (Maximum Rating: 5.5V)
*If VDD over maximum rating, it may lead to a permanent damage of IC.
Input Voltage …………………………………..
Operating Temperature ………………………
Storage Temperature …………………………
Junction Temperature ………………………..
-0.3V ~ VDD + 0.3V
-20°C ~ 70°C
-50°C ~ 125°C
150°C
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Page 12 of 68
PDK-DS-PMS15B/PMS150G-EN-V003–Jul. 24, 2020
PMS15B/PMS150G Family
8 bit OTP Type IO Controller
4.3. Typical IHRC Frequency vs. VDD (calibrated to 16MHz)
4.4. Typical ILRC Frequency vs. VDD
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Page 13 of 68
PDK-DS-PMS15B/PMS150G-EN-V003–Jul. 24, 2020
PMS15B/PMS150G Family
8 bit OTP Type IO Controller
4.5. Typical IHRC Frequency vs. Temperature (calibrated to 16MHz)
4.6. Typical ILRC Frequency vs. Temperature
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Page 14 of 68
PDK-DS-PMS15B/PMS150G-EN-V003–Jul. 24, 2020
PMS15B/PMS150G Family
8 bit OTP Type IO Controller
4.7. Typical Operating Current vs. VDD and CLK=IHRC/n
Conditions: ON: Band-gap, LVR, IHRC, T16 modules; OFF: ILRC modules;
IO: PA0:0.5Hz output toggle and no loading, others: input and no floating
4.8. Typical Operating Current vs. VDD and CLK=ILRC/n
Conditions: ON: T16 modules; OFF: Band-gap, LVR, ILRC, IHRC modules;
IO: PA0:0.5Hz output toggle and no loading, others: input and no floating
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Page 15 of 68
PDK-DS-PMS15B/PMS150G-EN-V003–Jul. 24, 2020
PMS15B/PMS150G Family
8 bit OTP Type IO Controller
4.9. Typical IO pull high resistance
4.10.Typical IO pull high resistance vs. Temperature, VDD=5V
©Copyright 2020, PADAUK Technology Co. Ltd
Page 16 of 68
PDK-DS-PMS15B/PMS150G-EN-V003–Jul. 24, 2020
PMS15B/PMS150G Family
8 bit OTP Type IO Controller
4.11.Typical IO pull Low resistance
4.12.Typical IO pull low resistance vs. Temperature, VDD=5V
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Page 17 of 68
PDK-DS-PMS15B/PMS150G-EN-V003–Jul. 24, 2020
PMS15B/PMS150G Family
8 bit OTP Type IO Controller
4.13.Typical IO driving current (IOH) and sink current (IOL)
( VOH=0.9*VDD, VOL=0.1*VDD )
4.14.Typical IO input high/low threshold voltage (VIH/VIL)
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Page 18 of 68
PDK-DS-PMS15B/PMS150G-EN-V003–Jul. 24, 2020
PMS15B/PMS150G Family
8 bit OTP Type IO Controller
4.15.Typical power down current (IPD) and power save current (IPS)
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Page 19 of 68
PDK-DS-PMS15B/PMS150G-EN-V003–Jul. 24, 2020
PMS15B/PMS150G Family
8 bit OTP Type IO Controller
5. Functional Description
5.1. Program Memory – OTP
The OTP (One Time Programmable) program memory is used to store the program instructions to be executed.
The OTP program memory may contains the data, tables and interrupt entry. After reset, the initial address for
FPP0 is 0x000. The interrupt entry is 0x010 if used, the last 16 addresses are reserved for system using, like
checksum, serial number, etc. The OTP program memory for PMS15B/PMS150Gis 0.5KW/1KW that is
partitioned as Table 1. The OTP memory from address 0x3F0 to 0x3FF is for system using, address space
from 0x001 to 0x00F and from 0x011 to 0x3EF is user program space.
Address
0x000
0x001
•
Function
FPP0 reset – goto instruction
User program
•
•
•
0x00F
0x010
0x011
•
User program
Interrupt entry address
User program
•
0x1FF
0x200
•
User program
User program
•(Not for PMS15B)
User program
System Using
•
0x3EF
0x3F0
•
0x3FF
System Using
Table 1: Program Memory Organization
5.2. Boot Procedure
POR (Power-On-Reset) is used to reset PMS15B/PMS150G when power up, the boot up options can be
selected as fast or slow, time for fast boot-up is about 32 ILRC clock cycles and 2048 ILRC clock cycles for
slow boot-up. Customer must ensure the stability of supply voltage after power up no matter which option is
chosen, the power up sequence is shown in the Fig. 1 and tSBP is the boot-up time.
Please noted, during Power-On-Reset, the VDD must go higher than VPOR to boot-up the MCU.
Fig. 1: Power Up Sequence
Page 20 of 68 PDK-DS-PMS15B/PMS150G-EN-V003–Jul. 24, 2020
©Copyright 2020, PADAUK Technology Co. Ltd
PMS15B/PMS150G Family
8 bit OTP Type IO Controller
5.2.1. Timing charts for reset conditions
LVR level
VDD
LVR
SBP
t
Program
Execution
Boot up from LVR detection
VDD
t
SBP
WD
Time Out
Program
Execution
Boot up from Watch Dog Time Out
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Page 21 of 68
PDK-DS-PMS15B/PMS150G-EN-V003–Jul. 24, 2020
PMS15B/PMS150G Family
8 bit OTP Type IO Controller
5.3. Data Memory – SRAM
The access of data memory can be byte or bit operation. Besides data storage, the SRAM data memory is also
served as data pointer of indirect access method and the stack memory.
The stack memory is defined in the data memory. The stack pointer is defined in the stack pointer register; the
depth of stack memory of each processing unit is defined by the user. The arrangement of stack memory fully
flexible and can be dynamically adjusted by the user.
For indirect memory access mechanism, the data memory is used as the data pointer to address the data byte.
All the data memory could be the data pointer; it’s quite flexible and useful to do the indirect memory access.
All the 64 bytes data memory of PMS15B/PMS150G can be accessed by indirect access mechanism.
5.4. Oscillator and clock
There are two oscillator circuits provided by PMS15B/PMS150G: internal high RC oscillator (IHRC) and
internal low RC oscillator (ILRC), and these two oscillators are enabled or disabled by registers clkmd.4 and
clkmd.2 independently. User can choose one of these two oscillators as system clock source and use clkmd
register to target the desired frequency as system clock to meet different application.
Oscillator Module
Enable/Disable
clkmd.4
IHRC
ILRC
clkmd.2
5.4.1. Internal High RC oscillator and Internal Low RC oscillator
After boot-up, the IHRC and ILRC oscillators are enabled. The frequency of IHRC can be calibrated to
eliminate process variation by ihrcr register; normally it is calibrated to 16MHz. The frequency deviation can
be within 2% normally after calibration and it still drifts slightly with supply voltage and operating temperature.
Please refer to the measurement chart for IHRC frequency verse VDD and IHRC frequency verse
temperature.
The frequency of ILRC will vary by process, supply voltage and temperature, please refer to DC specification
and do not use for accurate timing application.
5.4.2. IHRC calibration
The IHRC frequency may be different chip by chip due to manufacturing variation, PMS15B/PMS150G
provide the IHRC frequency calibration to eliminate this variation, and this function can be selected when
compiling user’s program and the command will be inserted into user’s program automatically. The calibration
command is shown as below:
.ADJUST_IC
SYSCLK=IHRC/(p1), IHRC=(p2)MHz, VDD=(p3)V
Where,
p1=8, 16, 32; In order to provide different system clock.
p2=14 ~ 18; In order to calibrate the chip to different frequency, 16MHz is the usually one.
p3=2.2 ~ 5.5; In order to calibrate the chip under different supply voltage.
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Page 22 of 68
PDK-DS-PMS15B/PMS150G-EN-V003–Jul. 24, 2020
PMS15B/PMS150G Family
8 bit OTP Type IO Controller
5.4.3. IHRC Frequency Calibration and System Clock
During compiling the user program, the options for IHRC calibration and system clock are shown as Table 2:
SYSCLK
○ Set IHRC / 8
○ Set IHRC / 16
○ Set IHRC / 32
○ Set ILRC
CLKMD
IHRCR
Description
= 3Ch (IHRC / 8)
= 1Ch (IHRC / 16)
= 7Ch (IHRC / 32)
= E4h (ILRC / 1)
No change
Calibrated
Calibrated
Calibrated
Calibrated
No Change
IHRC calibrated to 16MHz, CLK=2MHz (IHRC/8)
IHRC calibrated to 16MHz, CLK=1MHz (IHRC/16)
IHRC calibrated to 16MHz, CLK=0.5MHz (IHRC/32)
IHRC calibrated to 16MHz, CLK=ILRC
○ Disable
IHRC not calibrated, CLK not changed
Table 2: Options for IHRC Frequency Calibration
Usually, .ADJUST_IC will be the first command after boot up, in order to set the target operating frequency
whenever stating the system. The program code for IHRC frequency calibration is executed only one time
that occurs in writing the codes into OTP memory; after then, it will not be executed again. If the different
option for IHRC calibration is chosen, the system status is also different after boot. The following shows the
status of PMS15B/PMS150G for different option:
(1) .ADJUST_IC
SYSCLK=IHRC/8, IHRC=16MHz, VDD=2.5V
After boot, CLKMD = 0x3C:
IHRC frequency is calibrated to 16MHz@VDD=2.5V and IHRC module is enabled
System CLK = IHRC/8 = 2MHz
Watchdog timer is disabled, ILRC is enabled, PA5 is in input mode
(2) .ADJUST_IC
SYSCLK=IHRC/16, IHRC=16MHz, VDD=2.2V
After boot, CLKMD = 0x1C:
IHRC frequency is calibrated to 16MHz@VDD=2.2V and IHRC module is enabled
System CLK = IHRC/16 = 1MHz
Watchdog timer is disabled, ILRC is enabled, PA5 is in input mode
(3) .ADJUST_IC
SYSCLK=IHRC/32, IHRC=16MHz, VDD=5V
After boot, CLKMD = 0x7C:
IHRC frequency is calibrated to 16MHz@VDD=5V and IHRC module is enabled
System CLK = IHRC/32 = 500KHz
Watchdog timer is disabled, ILRC is enabled, PA5 is in input mode
(4) .ADJUST_IC
SYSCLK=ILRC, IHRC=16MHz, VDD=5V
After boot, CLKMD = 0XE4:
IHRC frequency is calibrated to 16MHz@VDD=5V and IHRC module is disabled
System CLK = ILRC
Watchdog timer is disabled, ILRC is enabled, PA5 is input mode
(5) .ADJUST_IC DISABLE
After boot, CLKMD is not changed (Do nothing):
IHRC is not calibrated.
System CLK = ILRC or IHRC/64 (by Boot-up_Time)
Watchdog timer is enabled, ILRC is enabled, PA5 is in input mode
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Page 23 of 68
PDK-DS-PMS15B/PMS150G-EN-V003–Jul. 24, 2020
PMS15B/PMS150G Family
8 bit OTP Type IO Controller
5.4.4. System Clock and LVR levels
The clock source of system clock comes from IHRC or ILRC, the hardware diagram of system clock in the
PMS15B/PMS150G is shown as Fig. 2.
Fig. 2: Options of System Clock
User can choose different operating system clock depends on its requirement; the selected operating system
clock should be combined with supply voltage and LVR level to make system stable. The LVR level will be
selected during compilation. Please refer to Section 4.1.
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Page 24 of 68
PDK-DS-PMS15B/PMS150G-EN-V003–Jul. 24, 2020
PMS15B/PMS150G Family
8 bit OTP Type IO Controller
5.4.5. System Clock Switching
After IHRC calibration, user may want to switch system clock to a new frequency or may switch system clock
at any time to optimize the system performance and power consumption. Basically, the system clock of
PMS15B/PMS150G can be switched among IHRC and ILRC by setting the clkmd register at any time;
system clock will be the new one after writing to clkmd register immediately. Please notice that the original
clock module can NOT be turned off at the same time as writing command to clkmd register. The examples
are shown as below and more information about clock switching, please refer to the “Help” -> “Application
Note” -> “IC Introduction” -> “Register Introduction” -> CLKMD”.
Case 1: Switching system clock from ILRC to IHRC/16
…
//
//
//
//
system clock is ILRC
CLKMD.4
CLKMD
// CLKMD.2
…
=
1;
turn on IHRC first to improve anti-interference ability
switch to IHRC/16, ILRC CAN NOT be disabled here
if need, ILRC CAN be disabled at this time
=
0x14;
0;
=
Case 2: Switching system clock from IHRC/16 to ILRC
…
//
//
//
system clock is IHRC/16
CLKMD
CLKMD.4
…
=
=
0xF4;
0;
switch to ILRC,IHRC CAN NOT be disabled here
IHRC CAN be disabled at this time
Case 3: Switching system clock from IHRC/8 to IHRC/16
…
//
//
system clock is IHRC/8, ILRC is enabled here
switch to IHRC/16
CLKMD
…
=
0X14;
Case 4: System may hang if it is to switch clock and turn off original oscillator at the same time
…
//
system clock is ILRC
CLKMD
=
0x30;
//
CAN NOT switch clock from ILRC to IHRC/16 and
turn off ILRC oscillator at the same time
©Copyright 2020, PADAUK Technology Co. Ltd
Page 25 of 68
PDK-DS-PMS15B/PMS150G-EN-V003–Jul. 24, 2020
PMS15B/PMS150G Family
8 bit OTP Type IO Controller
5.5. Comparator
One hardware comparator is built inside the PMS15B/PMS150G ; Fig. 3 shows its hardware diagram. It can
compare signals between two pins or with either internal reference voltage Vinternal R or internal band-gap
reference voltage. The two signals to be compared, one is the plus input and the other one is the minus input.
For the minus input of comparator can be PA3, PA4, Internal band-gap 1.20V, PA6, PA7 or Vinternal R selected
by bit [3:1] of gpcc register, and the plus input of comparator can be PA4 or Vinternal R selected by bit 0 of gpcc
register.
The comparator result can be selected through gpcs.7 to forcibly output to PA0 whatever it is input or output
state. It can be a direct output , or sampled by Timer2 clock (TM2_CLK) which comes from Timer2 module
through gpcc.5. The output polarity can be also inverted by setting gpcc.4register, the comparator output can
be used to request interrupt service or read through gpcc.6.
16 stages
VDD
8R
8R
8R
gpcs.5=1
gpcs.5=0
gpcs.4=0
gpcs.4=1
R
R
R
R
gpcs[3:0]
MUX
Vinternal R
gpcc[3:1]
PA3/CIN-
PA4/CIN-
Band-gap
000
001 M
gpcc.4
To request interrupt
gpcc.6
010 U
011 X
100
X
O
R
-
PA6/CIN-
PA7/CIN-
M
U
X
101
+
D
F
F
To
PA0
0
Timer 2
clock
MUX
1
PA4/CIN+
gpcc.0
TM2_CLK
gpcc.5
gpcs.7
Fig. 3: Hardware diagram of comparator
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Page 26 of 68
PDK-DS-PMS15B/PMS150G-EN-V003–Jul. 24, 2020
PMS15B/PMS150G Family
8 bit OTP Type IO Controller
5.5.1. Internal reference voltage (Vinternal R
)
The internal reference voltage Vinternal R is built by series resistance to provide different level of reference
voltage, bit 4 and bit 5 of gpcs register are used to select the maximum and minimum values of Vinternal R and
bit [3:0] of gpcs register are used to select one of the voltage level which is deivided-by-16 from the defined
maximum level to minimum level. Fig. 4 to Fig. 7 shows four conditions to have different reference voltage
Vinternal R. By setting the gpcs register, the internal reference voltage Vinternal R can be ranged from (1/32)*VDD to
(3/4)*VDD.
Case 1 : gpcs.5=0 & gpcs.4=0
16 stages
VDD
8R
8R
8R
gpcs.4=0
gpcs.4=1
gpcs.5=1
R
R
R
R
gpcs.5=0
MUX
gpcs[3:0]
V
internal R = (3/4) VDD ~ (1/4) VDD + (1/32) VDD
@ gpcs[3:0] = 1111 ~ gpcs[3:0] = 0000
1
4
(n+1)
32
V internal R
=
*
VDD +
*
VDD, n = gpcs[3:0] in decimal
Fig. 4: Vinternal R hardware connection if gpcs.5=0 and gpcs.4=0
Case 2 : gpcs.5=0 & gpcs.4= 1
16 stages
VDD
8R
8R
8R
gpcs.4=0
gpcs.4=1
gpcs.5=1
R
R
R
R
gpcs.5=0
MUX
gpcs[3:0]
V internal R = (2/3) VDD ~ (1/24) VDD
@ gpcs[3:0] = 1111 ~ gpcs[3:0] = 0000
(n+1)
V internal R
=
*
VDD, n = gpcs[3:0] in decimal
24
Fig. 5: Vinternal R hardware connection if gpcs.5=0 and gpcs.4=1
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Page 27 of 68
PDK-DS-PMS15B/PMS150G-EN-V003–Jul. 24, 2020
PMS15B/PMS150G Family
8 bit OTP Type IO Controller
Case 3 : gpcs.5=1 & gpcs.4= 0
16 stages
VDD
8R
8R
8R
gpcs.5=1
gpcs.4=0
gpcs.4=1
R
R
R
R
gpcs.5=0
MUX
gpcs[3:0]
V internal R = (3/5) VDD ~ (1/5) VDD + (1/40) VDD
@ gpcs[3:0] = 1111 ~ gpcs[3:0] = 0000
1
5
(n+1)
40
V internal R
=
*
VDD +
*
VDD, n = gpcs[3:0] in decimal
Fig.6: Vinternal R hardware connection if gpcs.5=1 and gpcs.4=0
Case 4 : gpcs.5=1 & gpcs.4=1
16 stages
VDD
8R
8R
8R
gpcs.4=0
gpcs.4=1
gpcs.5=1
R
R
R
R
gpcs.5=0
MUX
gpcs[3:0]
V
internal R = (1/2) VDD ~ (1/32) VDD
@ gpcs[3:0] = 1111 ~ gpcs[3:0] = 0000
(n+1)
V internal R
=
*
VDD, n = gpcs[3:0] in decimal
32
Fig.7: Vinternal R hardware connection if gpcs.5=1 and gpcs.4=1
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Page 28 of 68
PDK-DS-PMS15B/PMS150G-EN-V003–Jul. 24, 2020
PMS15B/PMS150G Family
8 bit OTP Type IO Controller
5.5.2. Using the comparator
Case A:
Choosing PA3 as minus input and Vinternal R with (18/32)*VDD voltage level as plus input. Vinternal R is configured
as the above Figure “gpcs[5:4] = 2b’00” and gpcs [3:0] = 4b’1001 (n=9) to have Vinternal R = (1/4)*VDD
[(9+1)/32]*VDD = [(9+9)/32]*VDD = (18/32)*VDD.
+
gpcs
gpcc
padier
= 0b0_0_00_1001;
= 0b1_0_0_0_000_0;
= 0bxxxx_0_xxx;
// Vinternal R = VDD*(18/32)
// enable comp, - input: PA3, + input: Vinternal R
// disable PA3 digital input to prevent leakage current
or
$ GPCS
VDD*18/32;
$ GPCC Enable, N_PA3, P_R;
PADIER = 0bxxxx_0_xxx;
// - input: N_xx,+ input: P_R(Vinternal R)
Case B:
Choosing Vinternal R as minus input with (22/40)*VDD voltage level and PA4 as plus input, the comparator result
will be inversed and then output to PA0. Vinternal R is configured as the above Figure “gpcs[5:4] = 2b’10” and
gpcs [3:0] = 4b’1101 (n=13) to have Vinternal R = (1/5)*VDD + [(13+1)/40]*VDD = [(13+9)/40]*VDD = (22/40)*VDD.
gpcs
gpcc
padier
= 0b1_0_10_1101;
= 0b1_0_0_1_011_1;
= 0bxxx_0_xxxx;
// output to PA0, Vinternal R = VDD*(22/40)
// Inverse output, - input: Vinternal R, + input: PA4
// disable PA4 digital input to prevent leakage current
or
$ GPCS
$ GPCC
Output, VDD*22/40;
Enable, Inverse, N_R, P_PA4; // - input: N_R(Vinternal R),+ input: P_xx
PADIER = 0bxxx_0_xxxx;
Note: When selecting output to PA0 output, GPCS will affect the PA3 output function in ICE. Though the IC is
fine, be careful to avoid this error during emulation.
5.5.3. Using the comparator and band-gap 1.20V
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Page 29 of 68
PDK-DS-PMS15B/PMS150G-EN-V003–Jul. 24, 2020
PMS15B/PMS150G Family
8 bit OTP Type IO Controller
The internal band-gap module provides a stable 1.20V output, and it can be used to measure the external
supply voltage level. The band-gap 1.20V is selected as minus input of comparator and Vinternal R is selected
as plus input, the supply voltage of Vinternal R is VDD, the VDD voltage level can be detected by adjusting the
voltage level of Vinternal R to compare with band-gap. If N (gpcs[3:0] in decimal) is the number to let Vinternal R
closest to band-gap 1.20 volt, the supply voltage VDD can be calculated by using the following equations:
For using Case 1: VDD = [ 32 / (N+9) ] * 1.20 volt ;
For using Case 2: VDD = [ 24 / (N+1) ] * 1.20 volt ;
For using Case 3: VDD = [ 40 / (N+9) ] * 1.20 volt ;
For using Case 4: VDD = [ 32 / (N+1) ] * 1.20 volt ;
Case 1:
$ GPCS
VDD*12/40;
// 4.0V * 12/40 = 1.2V
$ GPCC Enable, BANDGAP, P_R; // - input: BANDGAP, + input: P_R(Vinternal R
)
….
if (GPC_Out)
// or GPCC.6
{
// when VDD﹥4V
}
else
{
}
// when VDD﹤4V
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Page 30 of 68
PDK-DS-PMS15B/PMS150G-EN-V003–Jul. 24, 2020
PMS15B/PMS150G Family
8 bit OTP Type IO Controller
5.6. 16-bit Timer (Timer16)
PMS15B/PMS150G provide a 16-bit hardware timer (Timer16) and its clock source may come from system
clock (CLK), internal high RC oscillator (IHRC), internal low RC oscillator (ILRC), PA0 or PA4. Before
sending clock to the 16-bit counter, a pre-scaling logic with divided-by-1, 4, 16 or 64 is selectable for wide
range counting. The 16-bit counter performs up-counting operation only, the counter initial values can be
stored from data memory by issuing the stt16 instruction and the counting values can be loaded to data
memory by issuing the ldt16 instruction. The interrupt request from Timer16 will be triggered by the selected
bit which comes from bit[15:8] of this 16-bit counter, rising edge or falling edge can be optional chosen by
register integs.4. The hardware diagram of Timer16 is shown as Fig. 8.
stt16 command
DATA Memory
t16m[7:5]
t16m[4:3]
ldt16 command
CLK
IHRC
ILRC
PA0
M
U
X
Pre-
scalar
÷
1, 4,
16, 64
16-bit
up
counter
Bit[15:0]
Data Bus
PA4
Bit[15:8]
M
U
X
To set
interrupt
request flag
or
t16m[2:0]
integs.4
Fig. 8: Hardware diagram of Timer16
When using the Timer16, the syntax for Timer16 has been defined in the .INC file. There are three parameters
to define the Timer16 using; 1st parameter is used to define the clock source of Timer16, 2nd parameter is used
to define the pre-scalar and the 3rd one is to define the interrupt source.
T16M
$ 7~5:
IO_RW
0x06
STOP, SYSCLK, X, PA4_F, IHRC, X, ILRC, PA0_F
/1, /4, /16, /64
// 1st par.
// 2nd par.
// 3rd par.
$ 4~3:
$ 2~0:
BIT8, BIT9, BIT10, BIT11, BIT12, BIT13, BIT14, BIT15
User can choose the proper parameters of T16M to meet system requirement, examples as below:
$
T16M
SYSCLK, /64, BIT15;
// choose (SYSCLK/64) as clock source, every 2^16 clock to set INTRQ.2=1
// if system clock SYSCLK = IHRC / 2 = 8 MHz
// SYSCLK/64 = 8 MHz/64 = 8 uS, about every 524 mS to generate INTRQ.2=1
$
$
T16M
PA0, /1, BIT8;
// choose PA0 as clock source, every 2^9 to generate INTRQ.2=1
// receiving every 512 times PA0 to generate INTRQ.2=1
T16M
STOP;
// stop Timer16 counting
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Page 31 of 68
PDK-DS-PMS15B/PMS150G-EN-V003–Jul. 24, 2020
PMS15B/PMS150G Family
8 bit OTP Type IO Controller
5.7. 8-bit timer (Timer2) with PWM generation
One 8-bit hardware timer (Timer2/TM2) with PWM generation is implemented in the PMS15B/PMS150G.
Please refer to Fig. 9 shown its hardware diagram, the clock sources of Timer2 may come from system clock,
internal high RC oscillator (IHRC) or, internal low RC oscillator (ILRC), PA0 or PA4. Bit[7:4] of register tm2c are
used to select the clock source of Timer2. Please notice that if IHRC is selected for Timer2 clock source, the
clock sent to Timer2 will keep running when using ICE in halt state. The output of Timer2 can be selected
through tm2c[3:2] to output to PA3 or PA4. It will be a forcibly output whatever the PX.x is in input or output
state. A clock pre-scaling module is provided with divided-by-1, 4, 16, and 64 options, controlled by bit [6:5] of
tm2s register; one scaling module with divided-by-1~31 is also provided and controlled by bit [4:0] of tm2s
register. In conjunction of pre-scaling function and scaling function, the frequency of Timer2 clock (TM2_CLK)
can be wide range and flexible.
The Timer2 counter performs 8-bit up-counting operation only; the counter values can be set or read back by
tm2ct register. The 8-bit counter will be clear to zero automatically when its values reach for upper bound
register, the upper bound register is used to define the period of timer or duty of PWM. There are two operating
modes for Timer2: period mode and PWM mode; period mode is used to generate periodical output waveform
or interrupt event; PWM mode is used to generate PWM output waveform with optional 6-bit or 8-bit PWM
resolution, Fig. 10 shows the timing diagram of Timer2 for both period mode and PWM mode.
TM2_CLK
tm2s.7
tm2c.1
tm2c[7:4]
tm2s[6:5] tm2s[4:0]
Pre-
edge to
interrupt
8-bit
up
counter
CLK,
IHRC,
ILRC,
Cmp,
PA0,
~PA0,
PA4,
~PA4
tm2ct[7:0]
PA4
scalar
÷
Scalar
÷
M
U
X
1, 4,
16, 64
1 ~ 31
X
O
R
D
E
M
U
X
PA3
upper
bound
register
tm2c.0
tm2b[7:0]
tm2c[3:2]
Fig. 9: Timer2 hardware diagram
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Page 32 of 68
PDK-DS-PMS15B/PMS150G-EN-V003–Jul. 24, 2020
PMS15B/PMS150G Family
8 bit OTP Type IO Controller
Time out and
Time out and
Time out and
Interrupt request
Interrupt request
Interrupt request
Counter
0xFF
bound
Counter
0xFF
Counter
0x3F
bound
bound
Time
Time
Time
Time
Time
Event Trigger
Event Trigger
Event Trigger
Output-pin
Output-pin
Output-pin
Time
Mode 0 – Period Mode
Mode 1 – 8-bit PWM Mode
Mode 1 – 6-bit PWM Mode
Fig. 10: Timing diagram of Timer2 in period mode and PWM mode (tm2c.1=1)
5.7.1. Using the Timer2 to generate periodical waveform
If periodical mode is selected, the duty cycle of output is always 50%; its frequency can be summarized as
below:
Frequency of Output = Y ÷ [2 × (K+1) × S1 × (S2+1) ]
Where,
Y = tm2c[7:4] : frequency of selected clock source
K = tm2b[7:0] : bound register in decimal
S1 = tm2s[6:5] : pre-scalar (S1=1, 4, 16, 64)
S2 = tm2s[4:0] : scalar register in decimal (S2=0 ~ 31)
Example 1:
tm2c = 0b0001_1000, Y=2MHz
tm2b = 0b0111_1111, K=127
tm2s = 0b0_00_00000, S1=1, S2=0
frequency of output = 2MHz ÷ [ 2 × (127+1) × 1 × (0+1) ] = 7.8kHz
Example 2:
Example 3:
tm2c = 0b0001_1000, Y=2MHz
tm2b = 0b0111_1111, K=127
tm2s[7:0] = 0b0_10_11111, S1=16 , S2 = 31
frequency = 2MHz ÷ ( 2 × (127+1) × 16× (31+1) ) =15.25Hz
tm2c = 0b0001_1000, Y=2MHz
tm2b = 0b0000_1111, K=15
tm2s = 0b0_00_00000, S1=1, S2=0
frequency = 2MHz ÷ ( 2 × (15+1) × 1 × (0+1) ) = 62.5kHz
Example 4:
tm2c = 0b0001_1000, Y=2MHz
tm2b = 0b0000_0001, K=1
tm2s = 0b0_00_00000, S1=1, S2=0
frequency = 2MHz ÷ ( 2 × (1+1) × 1 × (0+1) ) =500KHz
©Copyright 2020, PADAUK Technology Co. Ltd
Page 33 of 68
PDK-DS-PMS15B/PMS150G-EN-V003–Jul. 24, 2020
PMS15B/PMS150G Family
8 bit OTP Type IO Controller
The sample program for using the Timer2 to generate periodical waveform to PA3 is shown as below:
void FPPA0 (void)
{
. ADJUST_IC
…
SYSCLK=IHRC/8, IHRC=16MHz, VDD=5V
tm2ct = 0x00;
tm2b = 0x7f;
tm2s = 0b0_00_00001;
tm2c = 0b0001_10_0_0;
//
//
8-bit PWM, pre-scalar = 1, scalar = 2
system clock, output=PA3, period mode
while(1)
{
nop;
}
}
5.7.2. Using the Timer2 to generate 8-bit PWM waveform
If 8-bit PWM mode is selected, it should set tm2c[1]=1 and tm2s[7]=0, the frequency and duty cycle of output
waveform can be summarized as below:
Frequency of Output = Y ÷ [256 × S1 × (S2+1) ]
Duty of Output = [( K+1 ) ÷ 256]×100%
Where, Y = tm2c[7:4] : frequency of selected clock source
K = tm2b[7:0] : bound register in decimal
S1= tm2s[6:5] : pre-scalar (S1=1, 4, 16, 64)
S2 = tm2s[4:0] : scalar register in decimal (S2=0 ~ 31)
Example 1:
tm2c = 0b0001_1010, Y=2MHz
tm2b = 0b0111_1111, K=127
tm2s = 0b0_00_00000, S1=1, S2=0
frequency of output = 2MHz ÷ ( 256 × 1 × (0+1) ) = 7.8kHz
duty of output = [(127+1) ÷ 256] × 100% = 50%
Example 2:
tm2c = 0b0001_1010, Y=2MHz
tm2b = 0b0111_1111, K=127
tm2s = 0b0_10_11111, S1=16, S2=31
frequency of output = 2MHz ÷ ( 256 × 16× (31+1) ) = 15.25Hz
duty of output = [(127+1) ÷ 256] × 100% = 50%
Example 3:
tm2c = 0b0001_1010, Y=2MHz
tm2b = 0b1111_1111, K=255
tm2s = 0b0_00_00000, S1=1, S2=0
frequency of output = 2MHz ÷ ( 256 × 1 × (0+1) ) = 7.8kHz
duty of output = [(255+1) ÷ 256] × 100% = 100%
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PDK-DS-PMS15B/PMS150G-EN-V003–Jul. 24, 2020
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8 bit OTP Type IO Controller
Example 4:
tm2c = 0b0001_1010, Y=2MHz
tm2b = 0b0000_1001, K = 9
tm2s = 0b0_00_00000, S1=1, S2=0
frequency of output = 2MHz ÷ ( 256 × 1 × (0+1) ) = 7.8kHz
duty of output = [(9+1) ÷ 256] × 100% = 3.9%
The sample program for using the Timer2 to generate PWM waveform from PA3 is shown as below:
void
{
FPPA0 (void)
.ADJUST_IC SYSCLK=IHRC/8, IHRC=16MHz, VDD=5V
wdreset;
tm2ct = 0x00;
tm2b = 0x7f;
tm2s = 0b0_00_00001;
//
//
8-bit PWM, pre-scalar = 1, scalar = 2
system clock, output=PA3, PWM mode
tm2c = 0b0001_10_1_0;
while(1)
{
nop;
}
}
©Copyright 2020, PADAUK Technology Co. Ltd
Page 35 of 68
PDK-DS-PMS15B/PMS150G-EN-V003–Jul. 24, 2020
PMS15B/PMS150G Family
8 bit OTP Type IO Controller
5.7.3. Using the Timer2 to generate 6-bit PWM waveform
If 6-bit PWM mode is selected, it should set tm2c[1]=1 and tm2s[7]=1, the frequency and duty cycle of output
waveform can be summarized as below:
Frequency of Output = Y ÷ [64 × S1 × (S2+1) ]
Duty of Output = [( K+1 ) ÷ 64] × 100%
Where, tm2c[7:4] = Y : frequency of selected clock source
tm2b[7:0] = K : bound register in decimal
tm2s[6:5] = S1 : pre-scalar (S1=1, 4, 16, 64)
tm2s[4:0] = S2 : scalar register in decimal (S2=0 ~ 31)
Example 1:
tm2c = 0b0001_1010, Y=2MHz
tm2b = 0b0001_1111, K=31
tm2s = 0b1_00_00000, S1=1, S2=0
frequency of output = 2MHz ÷ ( 64 × 1 × (0+1) ) = 31.25kHz
duty = [(31+1) ÷ 64] × 100% = 50%
Example 2:
tm2c = 0b0001_1010, Y=2MHz
tm2b = 0b0001_1111, K=31
tm2s = 0b1_11_11111, S1=64, S2=31
frequency of output = 2MHz ÷ ( 64 × 64 × (31+1) ) = 15.25Hz
duty of output = [(31+1) ÷ 64] × 100% = 50%
Example 3:
tm2c = 0b0001_1010, Y=2MHz
tm2b = 0b0011_1111, K=63
tm2s = 0b1_00_00000, S1=1, S2=0
frequency of output = 2MHz ÷ ( 64 × 1 × (0+1) ) = 31.25kHz
duty of output = [(63+1) ÷ 64] × 100% = 100%
Example 4:
tm2c = 0b0001_1010, Y=2MHz
tm2b = 0b0000_0000, K=0
tm2s = 0b1_00_00000, S1=1, S2=0
frequency = 2MHz ÷ ( 64 × 1 × (0+1) ) = 31.25kHz
duty = [(0+1) ÷ 64] × 100% =1.5%
©Copyright 2020, PADAUK Technology Co. Ltd
Page 36 of 68
PDK-DS-PMS15B/PMS150G-EN-V003–Jul. 24, 2020
PMS15B/PMS150G Family
8 bit OTP Type IO Controller
5.8. Watchdog Timer
The watchdog timer (WDT) is a counter with clock coming from ILRC and its frequency is about 62KHz@5V.
There are 4 different timeout periods of watchdog timer can be chosen by setting the misc register, it is:
256k ILRC clock period when misc[1:0]=11
64k ILRC clock period when misc[1:0]=10
16k ILRC clock period when misc[1:0]=01
8k ILRC clock period when misc[1:0]=00 (default)
The frequency of ILRC may drift a lot due to the variation of manufacture, supply voltage and temperature; user
should reserve guard band for safe operation. WDT can be cleared by power-on-reset or by command
wdreset at any time. When WDT is timeout, PMS15B/PMS150G will be reset to restart the program execution.
The relative timing diagram of watchdog timer is shown as Fig. 11.
VDD
t
SBP
WD
Time Out
Program
Execution
Watch Dog Time Out Sequence
Fig. 11: Sequence of Watch Dog Time Out
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Page 37 of 68
PDK-DS-PMS15B/PMS150G-EN-V003–Jul. 24, 2020
PMS15B/PMS150G Family
8 bit OTP Type IO Controller
5.9. Interrupt
There are four interrupt lines for PMS15B/PMS150G:
External interrupt PA0
GPC interrupt
Timer16 interrupt
Timer2 interrupt
Every interrupt request line has its own corresponding interrupt control bit to enable or disable it; the hardware
diagram of interrupt function is shown as Fig. 12. All the interrupt request flags are set by hardware and cleared
by writing intrq register. When the request flags are set, it can be rising edge, falling edge or both, depending
on the setting of register integs. All the interrupt request lines are also controlled by engint instruction (enable
global interrupt) to enable interrupt operation and disgint instruction (disable global interrupt) to disable it. The
stack memory for interrupt is shared with data memory and its address is specified by stack register sp. Since
the program counter is 16 bits width, the bit 0 of stack register sp should be kept 0. Moreover, user can use
pushaf / popaf instructions to store or restore the values of ACC and flag register to / from stack memory.
Since the stack memory is shared with data memory, the stack position and level are arranged by the compiler
in Mini-C project. When defining the stack level in ASM project, users should arrange their locations carefully to
prevent address conflicts.
Fig. 12: Hardware diagram of Interrupt controller
Once the interrupt occurs, its operation will be:
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Page 38 of 68
PDK-DS-PMS15B/PMS150G-EN-V003–Jul. 24, 2020
PMS15B/PMS150G Family
8 bit OTP Type IO Controller
The program counter will be stored automatically to the stack memory specified by register sp.
New sp will be updated to sp+2.
Global interrupt will be disabled automatically.
The next instruction will be fetched from address 0x010.
During the interrupt service routine, the interrupt source can be determined by reading the intrq register.
Note: Even if INTEN=0, INTRQ will be still triggered by the interrupt source.
After finishing the interrupt service routine and issuing the reti instruction to return back, its operation will be:
The program counter will be restored automatically from the stack memory specified by register sp.
New sp will be updated to sp-2.
Global interrupt will be enabled automatically.
The next instruction will be the original one before interrupt.
User must reserve enough stack memory for interrupt, two bytes stack memory for one level interrupt and four
bytes for two levels interrupt. And so on, two bytes stack memory is for pushaf. For interrupt operation, the
following sample program shows how to handle the interrupt, noticing that it needs four bytes stack memory to
handle interrupt and pushaf.
void
{
FPPA0
(void)
...
$
INTEN PA0;
// INTEN =1; interrupt request when PA0 level changed
// clear INTRQ
INTRQ
ENGINT
...
=
0;
// global interrupt enable
DISGINT
...
// global interrupt disable
}
void Interrupt (void)
// interrupt service routine
Page 39 of 68 PDK-DS-PMS15B/PMS150G-EN-V003–Jul. 24, 2020
©Copyright 2020, PADAUK Technology Co. Ltd
PMS15B/PMS150G Family
8 bit OTP Type IO Controller
{
PUSHAF
// store ALU and FLAG register
// If INTEN.PA0 will be opened and closed dynamically,
// user can judge whether INTEN.PA0 =1 or not.
// Example: If (INTEN.PA0 && INTRQ.PA0) {…}
// If INTEN.PA0 is always enable,
// user can omit the INTEN.PA0 judgement to speed up interrupt service routine.
If (INTRQ.PA0)
{
// Here for PA0 interrupt service routine
INTRQ.PA0 = 0;
...
// Delete corresponding bit (take PA0 for example)
}
...
// X : INTRQ = 0;
// It is not recommended to use INTRQ = 0 to clear all at the end of
// the interrupt service routine.
// It may accidentally clear out the interrupts that have just occurred
// and are not yet processed.
POPAF
// restore ALU and FLAG register
}
5.10.Power-Save and Power-Down
There are three operational modes defined by hardware: ON mode, Power-Save mode and Power-Down
modes. ON mode is the state of normal operation with all functions ON, Power-Save mode (“stopexe”) is the
state to reduce operating current and CPU keeps ready to continue, Power-Down mode (“stopsys”) is used to
save power deeply. Therefore, Power-Save mode is used in the system which needs low operating power with
wake-up occasionally and Power-Down mode is used in the system which needs power down deeply with
seldom wake-up. Table 3 shows the differences in oscillator modules between Power-Save mode (“stopexe”)
and Power-Down mode (“stopsys”).
Differences in oscillator modules between STOPSYS and STOPEXE
IHRC
Stop
ILRC
Stop
STOPSYS
STOPEXE
No Change
No Change
Table 3: Differences in oscillator modules between STOPSYS and STOPEXE
©Copyright 2020, PADAUK Technology Co. Ltd
Page 40 of 68
PDK-DS-PMS15B/PMS150G-EN-V003–Jul. 24, 2020
PMS15B/PMS150G Family
8 bit OTP Type IO Controller
5.10.1. Power-Save mode (“stopexe”)
Using “stopexe” instruction to enter the Power-Save mode, only system clock is disabled, remaining all the
oscillator modules be active. For CPU, it stops executing; however, for Timer16, counter keep counting if its
clock source is not the system clock. The wake-up sources for “stopexe” can be IO-toggle or Timer16 counts
to set values when the clock source of Timer16 is IHRC or ILRC modules, or wakeup by comparator when
setting GPCC.7=1 and GPCS.6=1 to enable the comparator wakeup function at the same time. Wake-up
from input pins can be considered as a continuation of normal execution, the detail information for
Power-Save mode shown below:
IHRC oscillator modules: No change, keep active if it was enabled.
ILRC oscillator modules: must remain enabled, need to start with ILRC when be wakening up.
System clock: Disable, therefore, CPU stops execution.
OTP memory is turned off.
Timer counter: Stop counting if its clock source is system clock or the corresponding oscillator module is
disabled; otherwise, it keeps counting. (The Timer contains TM16, TM2.)
Wake-up sources:
a. IO toggle wake-up: IO toggling in digital input mode (PAC bit is 1 and PADIER bit is 1)
b. Timer wake-up: If the clock source of Timer is not the SYSCLK, the system will be awakened when
the Timer counter reaches the set value.
c. Comparator wake-up: It need setting GPCC.7=1 and GPCS.6=1 to enable the comparator wake-up
function at the same time.
The watchdog timer must be disabled before issuing the “stopexe” command, the example is shown as
below:
CLKMD.En_WatchDog
stopexe;
….
Wdreset;
CLKMD.En_WatchDog
=
=
0;
1;
// disable watchdog timer
// power saving
// enable watchdog timer
Another example shows how to use Timer16 to wake-up from “stopexe”:
$ T16M ILRC, /1, BIT8
…
// Timer16 setting
WORD
STT16
stopexe;
…
count
count;
=
0;
The initial counting value of Timer16 is zero and the system will be waken up after the Timer16 counts 256
ILRC clocks.
©Copyright 2020, PADAUK Technology Co. Ltd
Page 41 of 68
PDK-DS-PMS15B/PMS150G-EN-V003–Jul. 24, 2020
PMS15B/PMS150G Family
8 bit OTP Type IO Controller
5.10.2. Power-Down mode (“stopsys”)
Power-Down mode is the state of deeply power-saving with turning off all the oscillator modules. By using the
“stopsys” instruction, this chip will be put on Power-Down mode directly. It is recommend to set GPCC.7=0 to
disable the comparator before the command “stopsys”. The following shows the internal status of
PMS15B/PMS150G in detail when “stopsys” command is issued:
All the oscillator modules are turned off.
OTP memory is turned off.
The contents of SRAM and registers remain unchanged.
Wake-up sources: IO toggle in digital input mode (PADIER bit is 1)
Wake-up from input pins can be considered as a continuation of normal execution. To minimize power
consumption, all the I/O pins should be carefully manipulated before entering power-down mode. The
reference sample program for power down is shown as below:
CMKMD
=
0xF4;
0;
//
//
Change clock from IHRC to ILRC, disable watchdog timer
disable IHRC
CLKMD.4 =
…
while (1)
{
STOPSYS;
//
//
//
enter power-down
if (…) break;
if wakeup happen and check OK, then return to high speed,
else stay in power-down mode again.
}
CLKMD
=
0x3C;
//
Change clock from ILRC to IHRC/8
5.10.3. Wake-up
After entering the Power-Down or Power-Save modes, the PMS15B/PMS150G can be resumed to normal
operation by toggling IO pins. Wake-up from timer are available for Power-Save mode ONLY. Table 4 shows
the differences in wake-up sources between STOPSYS and STOPEXE.
Differences in wake-up sources between STOPSYS and STOPEXE
IO Toggle
Yes
Timer wake-up
STOPSYS
STOPEXE
No
Yes
Yes
Table 4: Differences in wake-up sources between Power-Save mode and Power-Down mode
When using the IO pins to wake-up the PMS15B/PMS150G, registers padier should be properly set to enable
the wake-up function for every corresponding pin. The time for normal wake-up is about 2048 ILRC clocks
counting from wake-up event; fast wake-up can be selected to reduce the wake-up time by misc.5 register,
and the time for fast wake-up is 32 ILRC clocks from IO toggling. But the fast wake-up from misc.5 register
only worked in slow boot-up mode.
©Copyright 2020, PADAUK Technology Co. Ltd
Page 42 of 68
PDK-DS-PMS15B/PMS150G-EN-V003–Jul. 24, 2020
PMS15B/PMS150G Family
8 bit OTP Type IO Controller
Suspend mode
Wake-up mode
Wake-up time (tWUP) from IO toggle
STOPEXE suspend
or
32 * TILRC,
Where TILRC is the time period of ILRC
fast wake-up
STOPSYS suspend
STOPEXE suspend
or
2048 * TILRC
,
normal wake-up
Where TILRC is the clock period of ILRC
STOPSYS suspend
Table 5: Differences in wake-up time between fast/normal wake-up
5.11.IO Pins
All the pins can be independently set into two states output or input by configuring the data registers (pa),
control registers (pac), pull-high registers (paph) and pull-low registers (papl). All these pins have
Schmitt-trigger input buffer and output driver with CMOS level. When it is set to output low, the
pull-high/pull-low resistor is turned off automatically. When the pull-high / pull-low resistor enabled at the same
time, the pull-low resistor will be turned off automatically. If user wants to read the pin state, please notice that it
should be set to input mode before reading the data port; if user reads the data port when it is set to output
mode, the reading data comes from data register, NOT from IO pad. As an example, Table 6 shows the
configuration table of bit 0 of port A. The hardware diagram of IO buffer is also shown as Fig. 13.
pa.0 pac.0 paph.0 papl.0
描述
X
X
X
X
0
0
0
0
0
1
1
0
1
0
1
X
X
0
0
1
1
X
X
Input without pull-high / pull-low resistor
Input with pull-high resistor
Input with pull-low resistor
Input with pull-high resistor only
Output low without pull-high / pull-low resistor
Output high without pull-high / pull-low resistor
1
Table 6: PA0 Configuration Table
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Page 43 of 68
PDK-DS-PMS15B/PMS150G-EN-V003–Jul. 24, 2020
PMS15B/PMS150G Family
8 bit OTP Type IO Controller
Fig. 13: Hardware diagram of IO buffer
PA5 can be set as Normal IO or Open-Drain mode through PA5_Open_Drain in Code Option.
Except PA5, all the IO pins have the same structure; When PMS15B/PMS150G is put in power-down or
power-save mode, every pin can be used to wake-up system by toggling its state. Therefore, those pins
needed to wake-up system must be set to input mode and set the corresponding bits of registers padier to high.
The same reason, padier.0 should be set to high when PA0 is used as external interrupt pin.
5.12. Reset
There are many causes to reset the PMS15B/PMS150G, once reset is asserted, all the registers in
PMS15B/PMS150G will be set to default values, system should be restarted once abnormal cases happen,
or by jumping program counter to address ’h0. The data memory is in uncertain state when reset comes from
power-up and LVR; however, the content will be kept when reset comes from PRSTB pin or WDT timeout.
©Copyright 2020, PADAUK Technology Co. Ltd
Page 44 of 68
PDK-DS-PMS15B/PMS150G-EN-V003–Jul. 24, 2020
PMS15B/PMS150G Family
8 bit OTP Type IO Controller
6. IO Registers
6.1. ACC Status Flag Register (flag), IO address = 0x00
Bit
7 - 4
3
Reset R/W
Description
-
-
-
Reserved. These four bits are “1” when read.
R/W OV (Overflow). This bit is set whenever the sign operation is overflow.
AC (Auxiliary Carry). There are two conditions to set this bit, the first one is carry out of low
R/W nibble in addition operation, and the other one is borrow from the high nibble into low nibble
in subtraction operation.
2
-
C (Carry). There are two conditions to set this bit, the first one is carry out in addition
R/W operation, and the other one is borrow in subtraction operation. Carry is also affected by
shift with carry instruction.
1
0
-
-
Z (Zero). This bit will be set when the result of arithmetic or logic operation is zero;
R/W
Otherwise, it is cleared.
6.2. Stack Pointer Register (sp), IO address = 0x02
Bit
Reset R/W
Description
Stack Pointer Register. Read out the current stack pointer, or write to change the stack
pointer. Please notice that bit 0 should be kept 0 due to program counter is 16 bits.
7 - 0
-
R/W
6.3. Clock Mode Register (clkmd), IO address = 0x03
Bit
Reset R/W
Description
System clock selection:
Type 0, clkmd[3]=0
Type 1, clkmd[3]=1
000: reserved
001: reserved
01x: reserved
10x: reserved
000: IHRC÷ 16
001: IHRC÷ 8
7 - 5
111 R/W
010: ILRC÷ 16 (ICE does NOT Support.)
011: IHRC÷ 32
110: ILRC÷ 4
100: IHRC÷ 64
111: ILRC (default)
1xx: reserved
4
3
1
0
R/W IHRC oscillator Enable. 0 / 1: disable / enable
Clock Type Select. This bit is used to select the clock type in bit [7:5].
0 / 1: Type 0 / Type 1
RW
ILRC Enable. 0 / 1: disable / enable
2
1
R/W
If ILRC is disabled, watchdog timer is also disabled.
1
0
1
0
R/W Watch Dog Enable. 0 / 1: disable / enable
R/W Pin PA5/PRSTB function. 0 / 1: PA5 / PRSTB
6.4. Interrupt Enable Register (inten), IO address = 0x04
Bit
Reset R/W
Description
7,5,3,1
-
-
-
-
-
-
Reserved.
6
4
2
0
R/W Enable interrupt from Timer2. 0 / 1: disable / enable.
R/W Enable interrupt from comparator. 0 / 1: disable / enable.
R/W Enable interrupt from Timer16 overflow. 0 / 1: disable / enable.
R/W Enable interrupt from PA0. 0 / 1: disable / enable.
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Page 45 of 68
PDK-DS-PMS15B/PMS150G-EN-V003–Jul. 24, 2020
PMS15B/PMS150G Family
8 bit OTP Type IO Controller
6.5. Interrupt Request Register (intrq), IO address = 0x05
Bit
Reset R/W
Description
7,5,3,1
-
-
Reserved.
Interrupt Request from Timer2, this bit is set by hardware and cleared by software.
0 / 1: No request / Request
6
4
2
0
-
R/W
Interrupt Request from comparator, this bit is set by hardware and cleared by software.
0 / 1: No request / Request
-
-
-
R/W
R/W
R/W
Interrupt Request from Timer16, this bit is set by hardware and cleared by software.
0 / 1: No request / Request
Interrupt Request from pin PA0, this bit is set by hardware and cleared by software.
0 / 1: No request / Request
6.6. Timer 16 mode Register (t16m), IO address = 0x06
Bit
Reset R/W
Description
Timer Clock source selection
000: Timer 16 is disabled
001: CLK (system clock)
010: reserved
7 - 5
000 R/W 011: PA4 falling edge (from external pin)
100: IHRC
101: reserved
110: ILRC
111: PA0 falling edge (from external pin)
Internal clock divider.
00: ÷ 1
4 - 3
00
R/W 01: ÷ 4
10: ÷ 16
11: ÷ 64
Interrupt source selection. Interrupt event happens when selected bit is changed.
0 : bit 8 of Timer16
1 : bit 9 of Timer16
2 : bit 10 of Timer16
2 - 0
000 R/W 3 : bit 11 of Timer16
4 : bit 12 of Timer16
5 : bit 13 of Timer16
6 : bit 14 of Timer16
7 : bit 15 of Timer16
6.7. External Oscillator setting Register (eoscr, write only), IO address = 0x0a
Bit
7 - 1
0
Reset R/W
Description
-
-
Reserved. Please keep 0.
0
WO Power-down the Band-gap and LVR hardware modules. 0 / 1: normal / power-down.
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Page 46 of 68
PDK-DS-PMS15B/PMS150G-EN-V003–Jul. 24, 2020
PMS15B/PMS150G Family
8 bit OTP Type IO Controller
6.8. Interrupt Edge Select Register (integs), IO address = 0x0c
Bit
Reset R/W
Description
Comparator edge selection.
00 : both rising edge and falling edge to trigger interrupt
7 - 6
00
WO 01 : rising edge to trigger interrupt
10 : falling edge to trigger interrupt
11 : reserved.
5
4
-
0
-
-
Reserved. Please keep 0.
Timer16 edge selection.
WO 0 : rising edge to trigger interrupt
1 : falling edge to trigger interrupt
3 - 2
-
Reserved.
PA0 edge selection.
00 : both rising edge and falling edge to trigger interrupt
1 - 0
00
WO 01 : rising edge to trigger interrupt
10 : falling edge to trigger interrupt
11 : reserved.
6.9. Port A Digital Input Enable Register (padier), IO address = 0x0d
Bit
Reset R/W
Description
Enable PA7~PA3 digital input and wake up event. 1 / 0 : enable / disable.
If these bits are set to low, PA7~PA3 will be analog pins and can NOT be used to wake-up
the system.
7 - 3 11111 WO
2 - 1
0
-
-
Reserved.
Enable PA0 digital input, wake up event and interrupt request. 1 / 0 : enable / disable.
If this bit is set to low, PA0 will be an analog pin and can NOT be used to wake-up the
system, and the interrupt request from this pin will also be disabled.
1
WO
6.10.Port A Data Registers (pa), IO address = 0x10
Bit
Reset R/W
Description
7 - 0 8’h00 R/W Data registers for Port A.
6.11.Port A Control Registers (pac), IO address = 0x11
Bit
Reset R/W
Description
Port A control registers. This register is used to define input mode or output mode for each
corresponding pin of port A. 0 / 1: input / output.
7 - 0 8’h00 R/W
6.12.Port A Pull-High Registers (paph), IO address = 0x12
Bit
Reset R/W
Description
Port A pull-high registers. This register is used to enable the internal pull-high device on
each corresponding pin of port A. 0 / 1 : disable / enable
7 - 0 8’h00 R/W
6.13.Port A Pull-Low Registers (papl), IO address = 0x13
Bit
Reset R/W
Description
Port A pull-low registers. This register is used to enable the internal pull-low device on each
corresponding pin of port A. 0 / 1 : disable / enable
7 - 0
0x00 R/W
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Page 47 of 68
PDK-DS-PMS15B/PMS150G-EN-V003–Jul. 24, 2020
PMS15B/PMS150G Family
8 bit OTP Type IO Controller
6.14.MISC Register (misc), IO address = 0x1b
Bit
Reset R/W
Description
7 - 6
-
-
Reserved
Enable fast Wake up. (Only worked in slow boot-up mode.)
0: Normal wake up. The wake-up time is 2048 ILRC clocks
5
0
WO 1: Fast wake up. The wake-up time is 32 ILRC clocks.
Note:
The wake-up time is 32 ILRC clocks when in fast boot-up mode.
4
3
-
-
Reserved
WO Reserved.
Disable LVR function.
0
2
0
WO
0 / 1 : Enable / Disable
Watch dog time out period
00: 8k ILRC clock period
1 - 0
00
WO 01: 16k ILRC clock period
10: 64k ILRC clock period
11: 256k ILRC clock period
6.15.Comparator Control Register (gpcc), IO address = 0x1A
Bit
Reset R/W
Description
Enable comparator.
0 / 1 : disable / enable
7
0
R/W
RO
When this bit is set to enable, please also set the corresponding analog input pins to be
digital disable to prevent IO leakage.
Comparator result of comparator.
6
5
4
-
0: plus input < minus input
1: plus input > minus input
Select whether the comparator result output will be sampled by TM2_CLK?
0
0
R/W 0: result output NOT sampled by TM2_CLK
1: result output sampled by TM2_CLK
Inverse the polarity of result output of comparator.
R/W 0: polarity is NOT inversed.
1: polarity is inversed.
Selection the minus input (-) of comparator.
000 : PA3
001 : PA4
010 : Internal 1.20 volt band-gap reference voltage
3 - 1
000
R/W
011 : Vinternal R
100 : PA6 (not for 5S-I-S01/2(B))
101 : PA7 (not for 5S-I-S01/2(B))
11X : reserved
Selection the plus input (+) of comparator.
R/W 0 : Vinternal R
0
0
1 : PA4
©Copyright 2020, PADAUK Technology Co. Ltd
Page 48 of 68
PDK-DS-PMS15B/PMS150G-EN-V003–Jul. 24, 2020
PMS15B/PMS150G Family
8 bit OTP Type IO Controller
6.16.Comparator Selection Register (gpcs), IO address = 0x1E
Bit
Reset R/W
Description
Comparator output enable (to PA0).
0 / 1 : disable / enable
7
0
WO
(Please avoid this situation: GPCS will affect the PA3 output function when selecting
output to PA0 output in ICE.)
Wakeup by comparator enable. (The comparator wake-up effectively when gpcc.6
6
0
WO electrical level changed.)
0 / 1 : disable / enable
5
4
0
0
WO Selection of high range of comparator.
WO Selection of low range of comparator.
Selection the voltage level of comparator.
3 - 0
0000
WO
0000 (lowest) ~ 1111 (highest)
6.17.Timer2 Control Register (tm2c), IO address = 0x1C
Bit Reset
R/W
Description
Timer2 clock selection.
0000 : disable
0001 : CLK
0010 : IHRC
0011 : reserved
0100 : ILRC
0101 : comparator output
1000 : PA0 (rising edge)
1001 : ~PA0 (falling edge)
1100 : PA4 (rising edge)
1101 : ~PA4 (falling edge)
Others: reserved
7 - 4
0000 R/W
Notice: In ICE mode and IHRC is selected for Timer2 clock, the clock sent to Timer2
does NOT be stopped, Timer2 will keep counting when ICE is in halt state.
Timer2 output selection.
00 : disable
3 - 2
00
R/W 01 : reserved
10 : PA3
11 : PA4 (not for 5S-I-S01/2(B))
Timer2 mode selection.
1
0
0
0
R/W
R/W
0 / 1 : period mode / PWM mode
Enable to inverse the polarity of Timer2 output.
0 / 1: disable / enable
6.18.Timer2 Counter Register (tm2ct), IO address = 0x1D
Bit
Reset R/W
Description
©Copyright 2020, PADAUK Technology Co. Ltd
Page 49 of 68
PDK-DS-PMS15B/PMS150G-EN-V003–Jul. 24, 2020
PMS15B/PMS150G Family
8 bit OTP Type IO Controller
7 - 0
0x00
R/W Bit [7:0] of Timer2 counter register.
6.19.Timer2 Bound Register (tm2b), IO address = 0x09
Bit
Reset R/W
Description
7 - 0
0x00 WO Timer2 bound register.
6.20.Timer2 Scalar Register (tm2s), IO address = 0x17
Bit
Reset R/W
Description
PWM resolution selection.
1 : 6-bit
7
0
WO 0 : 8-bit
Timer2 clock pre-scalar.
00 : ÷ 1
6 - 5
00
WO 01 : ÷ 4
10 : ÷ 16
11 : ÷ 64
4 - 0 00000 WO Timer2 clock scalar.
©Copyright 2020, PADAUK Technology Co. Ltd
Page 50 of 68
PDK-DS-PMS15B/PMS150G-EN-V003–Jul. 24, 2020
PMS15B/PMS150G Family
8 bit OTP Type IO Controller
7. Instructions
Symbol
Description
ACC
a
Accumulator ( Abbreviation of accumulator )
Accumulator ( Symbol of accumulator in program )
sp
flag
I
Stack pointer
ACC status flag register
Immediate data
&
Logical AND
|
Logical OR
←
Movement
^
Exclusive logic OR
+
Add
-
〜
〒
OV
Z
Subtraction
NOT (logical complement, 1’s complement)
NEG (2’s complement)
Overflow (The operational result is out of range in signed 2’s complement number system)
Zero (If the result of ALU operation is zero, this bit is set to 1)
Carry (The operational result is to have carry out for addition or to borrow carry for subtraction
in unsigned number system)
C
Auxiliary Carry (If there is a carry out from low nibble after the result of ALU operation, this bit is
set to 1)
AC
word
M.n
Only addressed in 0~0x1F (0~31) is allowed
Only addressed in 0~0xF (0~15) is allowed
The bit of register
IO.n
©Copyright 2020, PADAUK Technology Co. Ltd
Page 51 of 68
PDK-DS-PMS15B/PMS150G-EN-V003–Jul. 24, 2020
PMS15B/PMS150G Family
8 bit OTP Type IO Controller
7.1. Data Transfer Instructions
mov
mov
mov
mov
mov
a, I
Move immediate data into ACC.
Example: mov a, 0x0f;
Result: a ← 0fh;
Affected flags: 『N』Z 『N』C 『N』AC 『N』OV
M, a
a, M
Move data from ACC into memory
Example: mov
MEM, a;
Result: MEM ← a
Affected flags: 『N』Z 『N』C 『N』AC 『N』OV
Move data from memory into ACC
Example: mov
a, MEM ;
Result: a ← MEM; Flag Z is set when MEM is zero.
Affected flags: 『Y』Z 『N』C 『N』AC 『N』OV
a, IO
Move data from IO into ACC
Example: mov
a, pa ;
Result: a ← pa; Flag Z is set when pa is zero.
Affected flags: 『Y』Z 『N』C 『N』AC 『N』OV
IO, a
Move data from ACC into IO
Example: mov
Result: pa ← a
pa, a;
Affected flags: 『N』Z 『N』C 『N』AC 『N』OV
Move 16-bit counting values in Timer16 to memory in word.
Example: ldt16 word;
ldt16 word
Result:
word ← 16-bit timer
Affected flags: 『N』Z 『N』C 『N』AC 『N』OV
Application Example:
------------------------------------------------------------------------------------------------------------------------
word
…
T16val ;
// declare a RAM word
clear
clear
stt16
…
lb@ T16val ;
hb@ T16val ;
T16val ;
// clear T16val (LSB)
// clear T16val (MSB)
// initial T16 with 0
set1
…
t16m.5 ;
// enable Timer16
set0
ldt16
….
t16m.5 ;
T16val ;
// disable Timer 16
// save the T16 counting value to T16val
------------------------------------------------------------------------------------------------------------------------
©Copyright 2020, PADAUK Technology Co. Ltd
Page 52 of 68
PDK-DS-PMS15B/PMS150G-EN-V003–Jul. 24, 2020
PMS15B/PMS150G Family
8 bit OTP Type IO Controller
stt16 word
Store 16-bit data from memory in word to Timer16.
Example: stt16 word;
Result:
16-bit timer ←word
Affected flags: 『N』Z 『N』C 『N』AC 『N』OV
Application Example:
------------------------------------------------------------------------------------------------------------------------
word
…
T16val ;
// declare a RAM word
mov
mov
mov
mov
stt16
…
a, 0x34 ;
lb@ T16val , a ;
a, 0x12 ;
// move 0x34 to T16val (LSB)
hb@ T16val , a ; // move 0x12 to T16val (MSB)
T16val ; // initial T16 with 0x1234
----------------------------------------------------------------------------------------------------------------------
idxm a, index Move data from specified memory to ACC by indirect method. It needs 2T to execute this
instruction.
Example: idxm a, index;
Result:
a ← [index], where index is declared by word.
Affected flags: 『N』Z 『N』C 『N』AC 『N』OV
Application Example:
-----------------------------------------------------------------------------------------------------------------------
word
…
RAMIndex ;
// declare a RAM pointer
mov
mov
mov
mov
…
a, 0x5B ;
// assign pointer to an address (LSB)
// save pointer to RAM (LSB)
lb@RAMIndex, a ;
a, 0x00 ;
// assign 0x00 to an address (MSB), should be 0
hb@RAMIndex, a ; // save pointer to RAM (MSB)
idxm
a, RAMIndex ; // move memory data in address 0x5B to ACC
------------------------------------------------------------------------------------------------------------------------
©Copyright 2020, PADAUK Technology Co. Ltd
Page 53 of 68
PDK-DS-PMS15B/PMS150G-EN-V003–Jul. 24, 2020
PMS15B/PMS150G Family
8 bit OTP Type IO Controller
Idxm index, a Move data from ACC to specified memory by indirect method. It needs 2T to execute this
instruction.
Example: idxm index, a;
Result:
[index] ← a; where index is declared by word.
Affected flags: 『N』Z 『N』C 『N』AC 『N』OV
Application Example:
------------------------------------------------------------------------------------------------------------------------
word
…
RAMIndex ;
// declare a RAM pointer
mov
mov
mov
mov
…
a, 0x5B ;
// assign pointer to an address (LSB)
// save pointer to RAM (LSB)
lb@RAMIndex, a ;
a, 0x00 ;
// assign 0x00 to an address (MSB), should be 0
hb@RAMIndex, a ; // save pointer to RAM (MSB)
mov
idxm
a, 0xA5 ;
RAMIndex, a ;
// move 0xA5 to memory in address 0x5B
------------------------------------------------------------------------------------------------------------------------
Exchange data between ACC and memory
xch
M
Example: xch MEM ;
Result:
MEM ← a , a ← MEM
Affected flags: 『N』Z 『N』C 『N』AC 『N』OV
Move the ACC and flag register to memory that address specified in the stack pointer.
Example: pushaf;
pushaf
Result:
[sp] ← {flag, ACC};
sp ← sp + 2 ;
Affected flags: 『N』Z 『N』C 『N』AC 『N』OV
Application Example:
------------------------------------------------------------------------------------------------------------------------
.romadr 0x10 ;
// ISR entry address
pushaf ;
…
// put ACC and flag into stack memory
// ISR program
…
// ISR program
popaf ;
reti ;
// restore ACC and flag from stack memory
------------------------------------------------------------------------------------------------------------------------
Restore ACC and flag from the memory which address is specified in the stack pointer.
Example: popaf;
popaf
Result:
sp ← sp - 2
{Flag, ACC} ← [sp] ;
Affected flags: 『Y』Z 『Y』C 『Y』AC 『Y』OV
;
©Copyright 2020, PADAUK Technology Co. Ltd
Page 54 of 68
PDK-DS-PMS15B/PMS150G-EN-V003–Jul. 24, 2020
PMS15B/PMS150G Family
8 bit OTP Type IO Controller
7.2. Arithmetic Operation Instructions
add
add
add
a, I
Add immediate data with ACC, then put result into ACC
Example: add a, 0x0f ;
Result: a ← a + 0fh
Affected flags: 『Y』Z 『Y』C 『Y』AC 『Y』OV
a, M
M, a
Add data in memory with ACC, then put result into ACC
Example: add
a, MEM ;
Result: a ← a + MEM
Affected flags: 『Y』Z 『Y』C 『Y』AC 『Y』OV
Add data in memory with ACC, then put result into memory
Example: add
MEM, a;
Result: MEM ← a + MEM
Affected flags: 『Y』Z 『Y』C 『Y』AC 『Y』OV
addc a, M
addc M, a
Add data in memory with ACC and carry bit, then put result into ACC
Example: addc
a, MEM ;
Result: a ← a + MEM + C
Affected flags: 『Y』Z 『Y』C 『Y』AC 『Y』OV
Add data in memory with ACC and carry bit, then put result into memory
Example: addc
MEM, a ;
Result: MEM ← a + MEM + C
Affected flags: 『Y』Z 『Y』C 『Y』AC 『Y』OV
addc
addc
sub
a
Add carry with ACC, then put result into ACC
Example: addc
a ;
Result: a ← a + C
Affected flags: 『Y』Z 『Y』C 『Y』AC 『Y』OV
M
Add carry with memory, then put result into memory
Example: addc
MEM ;
Result: MEM ← MEM + C
Affected flags: 『Y』Z 『Y』C 『Y』AC 『Y』OV
a, I
a, M
M, a
Subtraction immediate data from ACC, then put result into ACC.
Example: sub
a, 0x0f;
Result: a ← a - 0fh ( a + [2’s complement of 0fh] )
Affected flags: 『Y』Z 『Y』C 『Y』AC 『Y』OV
sub
Subtraction data in memory from ACC, then put result into ACC
Example: sub
a, MEM ;
Result: a ← a - MEM ( a + [2’s complement of M] )
Affected flags: 『Y』Z 『Y』C 『Y』AC 『Y』OV
sub
Subtraction data in ACC from memory, then put result into memory
Example: sub
MEM, a;
Result: MEM ← MEM - a ( MEM + [2’s complement of a] )
Affected flags: 『Y』Z 『Y』C 『Y』AC 『Y』OV
subc a, M
Subtraction data in memory and carry from ACC, then put result into ACC
Example: subc
Result: a ← a – MEM - C
Affected flags: 『Y』Z 『Y』C 『Y』AC 『Y』OV
a, MEM;
©Copyright 2020, PADAUK Technology Co. Ltd
Page 55 of 68
PDK-DS-PMS15B/PMS150G-EN-V003–Jul. 24, 2020
PMS15B/PMS150G Family
8 bit OTP Type IO Controller
subc M, a
Subtraction ACC and carry bit from memory, then put result into memory
Example: subc
MEM, a ;
Result: MEM ← MEM – a - C
Affected flags: 『Y』Z 『Y』C 『Y』AC 『Y』OV
subc
subc
inc
a
Subtraction carry from ACC, then put result into ACC
Example: subc
a;
Result: a ← a - C
Affected flags: 『Y』Z 『Y』C 『Y』AC 『Y』OV
M
Subtraction carry from the content of memory, then put result into memory
Example: subc
MEM;
Result: MEM ← MEM - C
Affected flags: 『Y』Z 『Y』C 『Y』AC 『Y』OV
M
Increment the content of memory
Example: inc
MEM ;
Result: MEM ← MEM + 1
Affected flags: 『Y』Z 『Y』C 『Y』AC 『Y』OV
dec
M
Decrement the content of memory
Example: dec
MEM;
Result: MEM ← MEM - 1
Affected flags: 『Y』Z 『Y』C 『Y』AC 『Y』OV
clear
M
Clear the content of memory
Example: clear
Result: MEM ← 0
Affected flags: 『N』Z 『N』C 『N』AC 『N』OV
MEM ;
7.3. Shift Operation Instructions
sr
a
Shift right of ACC, shift 0 to bit 7
Example: sr a ;
Result: a (0,b7,b6,b5,b4,b3,b2,b1) ← a (b7,b6,b5,b4,b3,b2,b1,b0), C ← a(b0)
Affected flags: 『N』Z 『Y』C 『N』AC 『N』OV
Shift right of ACC with carry bit 7 to flag
src
sr
a
Example: src a ;
Result: a (c,b7,b6,b5,b4,b3,b2,b1) ← a (b7,b6,b5,b4,b3,b2,b1,b0), C ← a(b0)
Affected flags: 『N』Z 『Y』C 『N』AC 『N』OV
Shift right the content of memory, shift 0 to bit 7
M
Example: sr MEM ;
Result: MEM(0,b7,b6,b5,b4,b3,b2,b1) ← MEM(b7,b6,b5,b4,b3,b2,b1,b0), C ← MEM(b0)
Affected flags: 『N』Z 『Y』C 『N』AC 『N』OV
Shift right of memory with carry bit 7 to flag
src
sl
M
Example: src MEM ;
Result: MEM(c,b7,b6,b5,b4,b3,b2,b1) ← MEM (b7,b6,b5,b4,b3,b2,b1,b0), C ← MEM(b0)
Affected flags: 『N』Z 『Y』C 『N』AC 『N』OV
Shift left of ACC shift 0 to bit 0
a
Example: sl a ;
Result: a (b6,b5,b4,b3,b2,b1,b0,0) ← a (b7,b6,b5,b4,b3,b2,b1,b0), C ← a (b7)
Affected flags: 『N』Z 『Y』C 『N』AC 『N』OV
©Copyright 2020, PADAUK Technology Co. Ltd
Page 56 of 68
PDK-DS-PMS15B/PMS150G-EN-V003–Jul. 24, 2020
PMS15B/PMS150G Family
8 bit OTP Type IO Controller
slc
sl
a
Shift left of ACC with carry bit 0 to flag
Example: slc a ;
Result: a (b6,b5,b4,b3,b2,b1,b0,c) ← a (b7,b6,b5,b4,b3,b2,b1,b0), C ← a(b7)
Affected flags: 『N』Z 『Y』C 『N』AC 『N』OV
Shift left of memory, shift 0 to bit 0
M
Example: sl MEM ;
Result: MEM (b6,b5,b4,b3,b2,b1,b0,0) ← MEM (b7,b6,b5,b4,b3,b2,b1,b0), C ← MEM(b7)
Affected flags: 『N』Z 『Y』C 『N』AC 『N』OV
Shift left of memory with carry bit 0 to flag
slc
M
Example: slc MEM ;
Result: MEM (b6,b5,b4,b3,b2,b1,b0,C) ← MEM (b7,b6,b5,b4,b3,b2,b1,b0), C ← MEM (b7)
Affected flags: 『N』Z 『Y』C 『N』AC 『N』OV
Swap the high nibble and low nibble of ACC
swap
a
Example: swap
Result: a (b3,b2,b1,b0,b7,b6,b5,b4) ← a (b7,b6,b5,b4,b3,b2,b1,b0)
Affected flags: 『N』Z 『N』C 『N』AC 『N』OV
a ;
7.4. Logic Operation Instructions
and
and
and
a, I
a, M
M, a
a, I
Perform logic AND on ACC and immediate data, then put result into ACC
Example: and a, 0x0f ;
Result: a ← a & 0fh
Affected flags: 『Y』Z 『N』C 『N』AC 『N』OV
Perform logic AND on ACC and memory, then put result into ACC
Example: and
a, RAM10 ;
Result: a ← a & RAM10
Affected flags: 『Y』Z 『N』C 『N』AC 『N』OV
Perform logic AND on ACC and memory, then put result into memory
Example: and
MEM, a ;
Result: MEM ← a & MEM
Affected flags: 『Y』Z 『N』C 『N』AC 『N』OV
or
or
or
Perform logic OR on ACC and immediate data, then put result into ACC
Example: or
a, 0x0f ;
Result: a ← a | 0fh
Affected flags: 『Y』Z 『N』C 『N』AC 『N』OV
a, M
Perform logic OR on ACC and memory, then put result into ACC
Example: or
a, MEM ;
Result: a ← a | MEM
Affected flags: 『Y』Z 『N』C 『N』AC 『N』OV
M, a
a, I
Perform logic OR on ACC and memory, then put result into memory
Example: or
MEM, a ;
Result: MEM ← a | MEM
Affected flags: 『Y』Z 『N』C 『N』AC 『N』OV
xor
Perform logic XOR on ACC and immediate data, then put result into ACC
Example: xor
Result: a ← a ^ 0fh
Affected flags: 『Y』Z 『N』C 『N』AC 『N』OV
a, 0x0f ;
©Copyright 2020, PADAUK Technology Co. Ltd
Page 57 of 68
PDK-DS-PMS15B/PMS150G-EN-V003–Jul. 24, 2020
PMS15B/PMS150G Family
8 bit OTP Type IO Controller
xor
xor
xor
not
IO, a
a, M
M, a
a
Perform logic XOR on ACC and IO register, then put result into IO register
Example: xor
pa, a ;
Result: pa ← a ^ pa ; // pa is the data register of port A
Affected flags: 『N』Z 『N』C 『N』AC 『N』OV
Perform logic XOR on ACC and memory, then put result into ACC
Example: xor
a, MEM ;
Result: a ← a ^ RAM10
Affected flags: 『Y』Z 『N』C 『N』AC 『N』OV
Perform logic XOR on ACC and memory, then put result into memory
Example:
xor
MEM, a ;
Result:
MEM ← a ^ MEM
Affected flags: 『Y』Z 『N』C 『N』AC 『N』OV
Perform 1’s complement (logical complement) of ACC
Example: not
a ;
Result: a ← 〜a
Affected flags: 『Y』Z 『N』C 『N』AC 『N』OV
Application Example:
------------------------------------------------------------------------------------------------------------------------
mov
not
a, 0x38 ;
a ;
// ACC=0X38
// ACC=0XC7
------------------------------------------------------------------------------------------------------------------------
Perform 1’s complement (logical complement) of memory
not
M
Example: not
MEM ;
Result: MEM ← 〜MEM
Affected flags: 『Y』Z 『N』C 『N』AC 『N』OV
Application Example:
------------------------------------------------------------------------------------------------------------------------
mov
mov
not
a, 0x38 ;
mem, a ;
mem ;
// mem = 0x38
// mem = 0xC7
------------------------------------------------------------------------------------------------------------------------
Perform 2’s complement of ACC
neg
a
Example: neg
a;
Result: a ← 〒a
Affected flags: 『Y』Z 『N』C 『N』AC 『N』OV
Application Example:
------------------------------------------------------------------------------------------------------------------------
mov
neg
a, 0x38 ;
a ;
// ACC=0X38
// ACC=0XC8
------------------------------------------------------------------------------------------------------------------------
©Copyright 2020, PADAUK Technology Co. Ltd
Page 58 of 68
PDK-DS-PMS15B/PMS150G-EN-V003–Jul. 24, 2020
PMS15B/PMS150G Family
8 bit OTP Type IO Controller
neg
M
Perform 2’s complement of memory
Example: neg MEM;
Result: MEM ← 〒MEM
Affected flags: 『Y』Z 『N』C 『N』AC 『N』OV
Application Example:
------------------------------------------------------------------------------------------------------------------------
mov
mov
not
a, 0x38 ;
mem, a ;
mem ;
// mem = 0x38
// mem = 0xC8
------------------------------------------------------------------------------------------------------------------------
7.5. Bit Operation Instructions
set0 IO.n
set1 IO.n
set0 M.n
set1 M.n
Set bit n of IO port to low
Example: set0 pa.5 ;
Result: set bit 5 of port A to low
Affected flags: 『N』Z 『N』C 『N』AC 『N』OV
Set bit n of IO port to high
Example: set1 pa.5 ;
Result: set bit 5 of port A to high
Affected flags: 『N』Z 『N』C 『N』AC 『N』OV
Set bit n of memory to low
Example: set0 MEM.5 ;
Result: set bit 5 of MEM to low
Affected flags: 『N』Z 『N』C 『N』AC 『N』OV
Set bit n of memory to high
Example: set1 MEM.5 ;
Result: set bit 5 of MEM to high
Affected flags: 『N』Z 『N』C 『N』AC 『N』OV
7.6. Conditional Operation Instructions
ceqsn a, I
Compare ACC with immediate data and skip next instruction if both are equal.
Flag will be changed like as (a ← a - I)
Example: ceqsn
a, 0x55 ;
MEM ;
error ;
inc
goto
Result: If a=0x55, then “goto error”; otherwise, “inc MEM”.
Affected flags: 『Y』Z 『Y』C 『Y』AC 『Y』OV
Compare ACC with memory and skip next instruction if both are equal.
Flag will be changed like as (a ← a - M)
ceqsn a, M
Example: ceqsn
a, MEM;
Result: If a=MEM, skip next instruction
Affected flags: 『Y』Z 『Y』C 『Y』AC 『Y』OV
t0sn IO.n
Check IO bit and skip next instruction if it’s low
Example: t0sn
pa.5;
Result: If bit 5 of port A is low, skip next instruction
Affected flags: 『N』Z 『N』C 『N』AC 『N』OV
©Copyright 2020, PADAUK Technology Co. Ltd
Page 59 of 68
PDK-DS-PMS15B/PMS150G-EN-V003–Jul. 24, 2020
PMS15B/PMS150G Family
8 bit OTP Type IO Controller
t1sn IO.n
t0sn M.n
t1sn M.n
Check IO bit and skip next instruction if it’s high
Example: t1sn pa.5 ;
Result: If bit 5 of port A is high, skip next instruction
Affected flags: 『N』Z 『N』C 『N』AC 『N』OV
Check memory bit and skip next instruction if it’s low
Example: t0sn MEM.5 ;
Result: If bit 5 of MEM is low, then skip next instruction
Affected flags: 『N』Z 『N』C 『N』AC 『N』OV
Check memory bit and skip next instruction if it’s high
EX: t1sn MEM.5 ;
Result: If bit 5 of MEM is high, then skip next instruction
Affected flags: 『N』Z 『N』C 『N』AC 『N』OV
Increment ACC and skip next instruction if ACC is zero
izsn
dzsn
izsn
dzsn
a
Example: izsn
Result:
a;
a
←
a + 1,skip next instruction if a = 0
Affected flags: 『Y』Z 『Y』C 『Y』AC 『Y』OV
a
Decrement ACC and skip next instruction if ACC is zero
Example: dzsn
a;
Result: A ← A - 1,skip next instruction if a = 0
Affected flags: 『Y』Z 『Y』C 『Y』AC 『Y』OV
M
Increment memory and skip next instruction if memory is zero
Example: izsn
Result: MEM
MEM;
MEM + 1, skip next instruction if MEM= 0
←
Affected flags: 『Y』Z 『Y』C 『Y』AC 『Y』OV
M
Decrement memory and skip next instruction if memory is zero
Example: dzsn
Result: MEM
Affected flags: 『Y』Z 『Y』C 『Y』AC 『Y』OV
MEM;
←
MEM - 1, skip next instruction if MEM = 0
7.7. System control Instructions
call
label
Function call, address can be full range address space
Example: call
function1;
pc + 1
Result: [sp]
←
pc
sp
←
←
function1
sp + 2
Affected flags: 『N』Z 『N』C 『N』AC 『N』OV
goto label
Go to specific address which can be full range address space
Example: goto
error;
Result: Go to error and execute program.
Affected flags: 『N』Z 『N』C 『N』AC 『N』OV
Place immediate data to ACC, then return
Example: ret 0x55;
ret
I
Result:
A ← 55h
ret ;
Affected flags: 『N』Z 『N』C 『N』AC 『N』OV
©Copyright 2020, PADAUK Technology Co. Ltd
Page 60 of 68
PDK-DS-PMS15B/PMS150G-EN-V003–Jul. 24, 2020
PMS15B/PMS150G Family
8 bit OTP Type IO Controller
ret
Return to program which had function call
Example: ret;
Result: sp ← sp - 2
pc ← [sp]
Affected flags: 『N』Z 『N』C 『N』AC 『N』OV
reti
Return to program that is interrupt service routine. After this command is executed, global
interrupt is enabled automatically.
Example: reti;
Affected flags: 『N』Z 『N』C 『N』AC 『N』OV
nop
No operation
Example: nop;
Result: nothing changed
Affected flags: 『N』Z 『N』C 『N』AC 『N』OV
pcadd
a
Next program counter is current program counter plus ACC.
Example: pcadd a;
Result: pc ← pc + a
Affected flags: 『N』Z 『N』C 『N』AC 『N』OV
Application Example:
------------------------------------------------------------------------------------------------------------------------
…
mov
pcadd
goto
goto
goto
goto
…
a, 0x02 ;
a ;
// PC <- PC+2
// jump here
err1 ;
correct ;
err2 ;
err3 ;
correct:
…
// jump here
------------------------------------------------------------------------------------------------------------------------
Enable global interrupt enable
engint
Example: engint;
Result: Interrupt request can be sent to FPP0
Affected flags: 『N』Z 『N』C 『N』AC 『N』OV
Disable global interrupt enable
disgint
stopsys
stopexe
Example: disgint ;
Result: Interrupt request is blocked from FPP0
Affected flags: 『N』Z 『N』C 『N』AC 『N』OV
System halt.
Example: stopsys;
Result: Stop the system clocks and halt the system
Affected flags: 『N』Z 『N』C 『N』AC 『N』OV
CPU halt. The oscillator module is still active to output clock, however, system clock is disabled
to save power.
Example: stopexe;
Result: Stop the system clocks and keep oscillator modules active.
Affected flags: 『N』Z 『N』C 『N』AC 『N』OV
©Copyright 2020, PADAUK Technology Co. Ltd
Page 61 of 68
PDK-DS-PMS15B/PMS150G-EN-V003–Jul. 24, 2020
PMS15B/PMS150G Family
8 bit OTP Type IO Controller
reset
Reset the whole chip, its operation will be same as hardware reset.
Example: reset;
Result: Reset the whole chip.
Affected flags: 『N』Z 『N』C 『N』AC 『N』OV
Reset Watchdog timer.
wdreset
Example: wdreset ;
Result: Reset Watchdog timer.
Affected flags: 『N』Z 『N』C 『N』AC 『N』OV
7.8. Summary of Instructions Execution Cycle
goto, call, idxm, pcadd, ret, reti
2T
2T
1T
1T
Condition is fulfilled
ceqsn, cneqsn,t0sn, t1sn, dzsn, izsn
Condition is not fulfilled
Others
©Copyright 2020, PADAUK Technology Co. Ltd
Page 62 of 68
PDK-DS-PMS15B/PMS150G-EN-V003–Jul. 24, 2020
PMS15B/PMS150G Family
8 bit OTP Type IO Controller
7.9. Summary of affected flags by Instructions
Instruction
mov a, I
Z
-
C
-
AC OV Instruction
Z
-
C
-
AC OV Instruction
Z
Y
-
C
-
AC OV
-
-
-
-
mov M, a
mov IO, a
idxm a, index
pushaf
-
-
-
-
mov a, M
ldt16 word
idxm index, a
popaf
-
-
-
-
mov a, IO
stt16 word
Y
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
xch
M
-
-
-
-
-
-
-
-
Y
Y
Y
Y
Y
Y
-
Y
Y
Y
Y
Y
Y
Y
Y
Y
-
Y
Y
Y
Y
Y
Y
-
Y
Y
Y
Y
Y
Y
-
add a, I
Y
Y
Y
Y
Y
Y
-
Y
Y
Y
Y
Y
Y
Y
Y
Y
-
Y
Y
Y
Y
Y
Y
-
Y
Y
Y
Y
Y
Y
-
add a, M
addc M, a
sub a, I
Y
Y
Y
Y
Y
-
Y
Y
Y
Y
Y
-
Y
Y
Y
Y
Y
-
Y
Y
Y
Y
Y
-
add M, a
addc a, M
addc
a
addc
M
sub a, M
sub M, a
subc a, M
subc M, a
subc
dec
src
a
subc
clear
M
M
inc
sr a
src
sl
M
M
M
a
sr
M
-
Y
Y
-
-
-
-
-
-
sl
a
-
-
-
slc
a
-
-
-
M
-
-
-
slc
and
M
-
-
-
swap
and
a
-
-
-
and
a, I
Y
Y
Y
Y
Y
-
-
-
a, M
Y
Y
-
-
-
M, a
Y
Y
Y
Y
-
-
-
-
or a, I
-
-
-
or a, M
-
-
-
or M, a
-
-
-
xor
xor
neg
a, I
-
-
-
xor
not
neg
IO, a
-
-
-
xor
not
a, M
-
-
-
M, a
a
-
-
-
a
Y
Y
-
-
-
-
M
-
-
-
-
-
-
M
-
-
-
set0 IO.n
set1 M.n
t0sn IO.n
t1sn M.n
-
-
-
set1 IO.n
ceqsn a, I
t1sn IO.n
-
-
-
set0 M.n
ceqsn a, M
t0sn M.n
-
-
-
-
-
-
-
Y
-
Y
-
Y
-
Y
-
Y
-
Y
-
Y
-
Y
-
-
-
-
-
-
-
-
-
izsn
dzsn
ret
a
Y
Y
-
Y
Y
-
Y
Y
-
Y
Y
-
dzsn
call
a
Y
-
Y
-
Y
-
Y
-
izsn
M
Y
-
Y
-
Y
-
Y
-
M
label
goto label
reti
I
ret
-
-
-
-
-
-
-
-
nop
-
-
-
-
pcadd
a
-
-
-
-
engint
-
-
-
-
disgint
reset
-
-
-
-
stopsys
wdreset
-
-
-
-
stopexe
-
-
-
-
-
-
-
-
-
-
-
-
7.10.BIT definition
(1) Bit defined: Only addressed at 0x00 ~ 0x0F
(2) WORD defined : Only addressed at 0x00 ~ 0x1E
©Copyright 2020, PADAUK Technology Co. Ltd
Page 63 of 68
PDK-DS-PMS15B/PMS150G-EN-V003–Jul. 24, 2020
PMS15B/PMS150G Family
8 bit OTP Type IO Controller
8. Code Options
Option
Selection
Enable
Disable
4.0V
Description
OTP content is protected and program cannot be read back
OTP content is not protected so program can be read back
Select LVR = 4.0V
Security
3.5V
Select LVR = 3.5V
3.0V
Select LVR = 3.0V
2.75V
2.5V
Select LVR = 2.75V
LVR
Select LVR = 2.5V
2.2V
Select LVR = 2.2V
2.0V
Select LVR = 2.0V
1.8V
Select LVR = 1.8V
Slow
Please refer to tWUP and tSBP in Section 4.1
Please refer to tWUP and tSBP in Section 4.1
PA5 as open drain mode
Boot-up_Time
Fast
Enable
Disable
PA5 Open-Drain
PA5 as normal IO mode
©Copyright 2020, PADAUK Technology Co. Ltd
Page 64 of 68
PDK-DS-PMS15B/PMS150G-EN-V003–Jul. 24, 2020
PMS15B/PMS150G Family
8 bit OTP Type IO Controller
9. Special Notes
This chapter is to remind user who use PMS15B/PMS150G series IC in order to avoid frequent errors upon
operation.
9.1. Warning
User must read all application notes of the IC by detail before using it. Please download the relative application
notes from the following link:
http://www.padauk.com.tw/tw/technical/index.aspx
9.2. Using IC
9.2.1. IO pin usage and setting
(1) IO pin as digital input
When IO is set as digital input, the level of Vih and Vil would changes with the voltage and temperature.
Please follow the minimum value of Vih and the maximum value of Vil.
The value of internal pull high resistor would also changes with the voltage, temperature and pin voltage.
It is not the fixed value.
(2) If IO pin is set to be digital input and enable wake-up function
Configure IO pin as input
Set corresponding bit to “1” in PADIER
For those IO pins of PA that are not used, PADIER[1:2] should be set low in order to prevent them from
leakage.
(3) PA5 is set to be PRSTB input pin
Configure PA5 as input
Set CLKMD.0=1 to enable PA5 as PRSTB input pin
(4) PA5 is set to be input pin and to connect with a push button or a switch by a long wire
Needs to put a >10Ω resistor in between PA5 and the long wire
Avoid using PA5 as input in such application.
9.2.2. Interrupt
(1) When using the interrupt function, the procedure should be:
Step1: Set INTEN register, enable the interrupt control bit
Step2: Clear INTRQ register
Step3: In the main program, using ENGINT to enable CPU interrupt function
Step4: Wait for interrupt. When interrupt occurs, enter to Interrupt Service Routine
Step5: After the Interrupt Service Routine being executed, return to the main program
* Use DISGINT in the main program to disable all interrupts
* When interrupt service routine starts, use PUSHAF instruction to save ALU and FLAG register.
POPAF instruction is to restore ALU and FLAG register before RETI as below:
©Copyright 2020, PADAUK Technology Co. Ltd
Page 65 of 68
PDK-DS-PMS15B/PMS150G-EN-V003–Jul. 24, 2020
PMS15B/PMS150G Family
8 bit OTP Type IO Controller
void Interrupt (void)
// Once the interrupt occurs, jump to interrupt service routine
{
// enter DISGINT status automatically, no more interrupt is accepted
PUSHAF;
…
POPAF;
}
// RETI will be added automatically. After RETI being executed, ENGINT status will be restored.
(2) INTEN and INTRQ have no initial values. Please set required value before enabling interrupt function.
9.2.3. System clock switching
System clock can be switched by CLKMD register. Please notice that, NEVER switch the system clock and
turn off the original clock source at the same time. For example: When switching from clock A to clock B,
please switch to clock B first; and after that turn off the clock A oscillator through CLKMD.
Example : Switch system clock from ILRC to IHRC/8
CLKMD
=
0x3C;
0;
// switch to IHRC, ILRC can not be disabled here
CLKMD.2 =
// ILRC can be disabled at this time
ERROR: Switch ILRC to IHRC/8 and turn off ILRC simultaneously
CLKMD 0x38; // MCU will hang
=
9.2.4. Power down mode, wakeup and watchdog
Watchdog will be inactive once ILRC is disabled.
9.2.5. TIMER time out
When select $ INTEGS BIT_R (default value) and T16M counter BIT8 to generate interrupt, if T16M counts
from 0, the first interrupt will occur when the counter reaches to 0x100 (BIT8 from 0 to 1) and the second
interrupt will occur when the counter reaches 0x300 (BIT8 from 0 to 1). Therefore, selecting BIT8 as 1 to
generate interrupt means that the interrupt occurs every 512 counts. Please notice that if T16M counter is
restarted, the next interrupt will occur once Bit8 turns from 0 to 1.
If select $ INTEGS BIT_F(BIT triggers from 1 to 0) and T16M counter BIT8 to generate interrupt, the T16M
counter changes to an interrupt every 0x200/0x400/0x600/. Please pay attention to two differences with
setting INTEGS methods.
9.2.6. IHRC
(1) The IHRC frequency calibration is performed when IC is programmed by the writer.
(2) Because the characteristic of the Epoxy Molding Compound (EMC) would some degrees affects the
IHRC frequency (either for package or COB), if the calibration is done before molding process, the actual
IHRC frequency after molding may be deviated or becomes out of spec. Normally , the frequency is
getting slower a bit.
(3) It usually happens in COB package or Quick Turnover Programming (QTP). And PADAUK would not
take any responsibility for this situation.
©Copyright 2020, PADAUK Technology Co. Ltd
Page 66 of 68
PDK-DS-PMS15B/PMS150G-EN-V003–Jul. 24, 2020
PMS15B/PMS150G Family
8 bit OTP Type IO Controller
(4) Users can make some compensatory adjustments according to their own experiences. For example,
users can set IHRC frequency to be 0.5% ~ 1% higher and aim to get better re-targeting after molding.
9.2.7. LVR
(1) The setting of LVR (1.8V ~ 4.0V) will be valid just after successful power-on process.
(2) User can set MISC.2 as “1” to disable LVR. However, VDD must be kept as exceeding the lowest working
voltage of chip; Otherwise IC may work abnormally.
9.2.8. Program writing
There are 6 pins for using the writer to program: PA3, PA4, PA5, PA6, VDD and GND.
Please use PDK5S-P-003 or above Writer to program PMS15B/PMS150G, and follow the instructions shown
in the Writer software for jumper connecting. PDK5S-P-002 or older versions do not support programming
this IC.
Special notes about voltage and current while Multi-Chip-Package(MCP) or On-Board Programming
(1) PA5 (VPP) may be higher than 7.5V.
(2) VDD may be higher than 7.8V, and its maximum current may reach about 20mA.
(3) All other signal pins level (except GND) are the same as VDD.
User should confirm when using this product in MCP or On-Board Programming, the peripheral components
or circuit will not be damaged by the above voltages, and will not clam the above voltages.
Important Cautions:
You MUST follow the instructions on APN004 and APN011 for programming IC on the handler.
Connecting a 0.01uF capacitor between VDD and GND at the handler port to the IC is always good
for suppressing disturbance. But please DO NOT connect with >0.01uF capacitor, otherwise,
programming may be fail.
©Copyright 2020, PADAUK Technology Co. Ltd
Page 67 of 68
PDK-DS-PMS15B/PMS150G-EN-V003–Jul. 24, 2020
PMS15B/PMS150G Family
8 bit OTP Type IO Controller
9.3. Using ICE
Please use PDK5S-I-S01/2(B) ICE to emulate most of PMS15B/PMS150G function except as the list below:
(1) PDK5S-I-S01/2(B) doesn’t support SYSCLK=ILRC/16
(2) PDK5S-I-S01/2(B) doesn’t support PA6 and PA7 as the CIN- of the comparator.
(3) PDK5S-I-S01/2(B) doesn’t support TM2PWM output of PA4.
(4) PDK5S-I-S01/2(B) doesn’t support the INTEGS the Bit[7:6] dynamically switched.
(5) When GPCS[7]=1, the output of PA0 will affect the High function of PA3.
(6) When simulating PWM waveform, please check the waveform during program running. When the ICE is
suspended or single-step running, its waveform may be inconsistent with the reality.
(7) The ILRC frequency of the PDK5S-I-S01/2(B) simulator is different from the actual IC and is uncalibrated,
with a frequency range of about 34K~38KHz.
(8) Fast Wakeup time is different from PDK5S-I-S01/2(B): 128 SysClk, PMS15B/PMS150G: 32 ILRC
(9) Watch dog time out period is different from PDK5S-I-S01/2(B):
WDT period
misc[1:0]=00
misc[1:0]=01
misc[1:0]=10
misc[1:0]=11
PMS15B/PMS150G
8K* TILRC
PDK5S-I-S01/2(B)
2048* TILRC
4096* TILRC
16K* TILRC
64K* TILRC
16384* TILRC
256* TILRC
256K* TILRC
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Page 68 of 68
PDK-DS-PMS15B/PMS150G-EN-V003–Jul. 24, 2020
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