MN102H460B(128LQFP) [PANASONIC]
Microcontroller;
| 型号： | MN102H460B(128LQFP) |
| 厂家： | 
PANASONIC |
| 描述： | Microcontroller 微控制器 |
| 文件： | 总4页 (文件大小：129K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
16-bit
AM2 (MN102) Series
C Language Oriented 16-bit Single-chip Microcomputers
The AM2(MN102) Series of 16-bit single-chip microcomputers offers high-speed operation with a minimum in-
struction execution time of only 50 ns (at 40 MHz).
The C compiler generates ROM code that is only 20% larger than assembler code.
The Series continues to add new versions tailored for specific types of applications so as to bring the benefits
of compactness and high performance to a wider range of applications.
C Language Oriented Architecture
Programs that are only 1.2 times the size of assembly versions
The register set represents a careful bal-
ancing of hardware needs against C
Conventional code assignment for general register instruction
15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
compiler code generation efficiency.
Eight avairable registers are egualy di-
vided by two for addresses and data re-
spectively. The instruction format re-
quires only four bits to specify a register
pair. As a result, approximately 80% of
the basic instructions fit within a single
byte. The compiler then uses register
optimization to maximize the efficiency
of register usage. These enhancements
mean that programs developed in C are
only some 20% larger than their hand-
coded assembly language equivalents.
GRn
GRn
Operation field
Operation field
Basic instruction defined as two bytes.
Because each register field makes up three bits,
it is impossible to fit the instruction into a single byte.
AM2 Series instruction code assignments
7
6
5
4
3
2
1
0
Operation field
An/Dn
An/Dn
Basic instruction defined as single byte.
Since each register field takes two bits, basic instructions
(register-to-register operations, load/store operations) fit within a single byte.
High Performance, Low Power Consumption
Three-stage pipeline boosts throughput (Instruction speed: 50ns)
Instructions are executed in a three-
1 machine cycle
stage pipeline: instruction fetch, decod-
ing, and execution. The decoding stage
performs two ALU operations in a sin-
gle machine cycle so that it calculates
operand addresses right at the decoding
stage. The result is load/store instruc-
tions that take one machine cycle to ex-
ecute. For branch instructions, calculat-
ing the branch target address during the
decoding stage also allows execution in
a minimum of two machine cycles. This
increases the instruction execution effi-
ciency and can reduce power consump-
tion.
Time
Instruction
fetch
Instruction 1
Decoding
Address
Data calculation
calculation
(execution)
Instruction
fetch
Instruction 2
Decoding
Address
Data calculation
calculation
(execution)
21
Microcomputer Family
Microcomputer Family
(
)
)
(
AM2 MN102 Series
AM2 MN102 Series
Built-in Multiplier
24-bit result from two 16-bit operands in a single cycle
The multiplier built into the AM22
A0
A1
A2
A3
D0
D1
D2
D3
Clock
generator
(MN102H) CPU core produces a 24-bit
result from two 16-bit operands in a sin-
gle cycle and a 32-bit result in two cy-
cles.
The saturation function provides multi-
ply with saturation operations in only
two cycles.
MDR
Instruction execution
control block
A
B
Instruction decoder
Program
PSW
counter block
Incrementer
Multiplier
ALU
Interrupt
Instruction
queue
control block
Program address
Operand address
Interrupt bus
Bus control block
Peripheral
ROM bus
RAM bus
expansion bus
External interface
Built-in peripherals
On-chip ROM
On-chip RAM
External
expansion bus
BR BG
Application to DVD-system
Well-suited for DVD-ROM, DVD-
RAM, DVD-Player
Disk
ꢀ
ꢀ
Spindle
moter
Optical
pickup
Single-chip
Head Amp
Driver
Optical Disc
Controller
HostPC
ꢀ
(SODC)
System
Controller
AM2 Series
ꢀ
22
Series Lineup (16-bit microcomputer product lineup development plans)
Support for ASIC versions
*1: Under development
*2: ES (Engineering Sample)
available
*3: Under planning
Flash
Mask ROM
ROM
(byte)
ADC
Built-in Type
MN102H460B
0 K
MN102LF59D
MN102L59D
MN102HF60x
MN102H60x
64 K
128 K, 256 K
MN102H950F
0 K
ADC•DAC
MN102H730FGT
Built-in Type
0 K
MN102HF73x
MN102H73x
128 K, 256 K
MN102HF74G
MN102H74x
128 K
USB
Built-in Type
64 K, 128 K
MN102L35G
144 K
MN102HF75K
MN102H75K
TV channel
selector
MN102H90M
MN102HF85K
MN102H85K
384 K
256 K
256 K
64pin
84pin
100pin
128pin
160pin
The lineup has expanded by offering application specific models with on-chip peripherals tailored to the needs of such specific ap-
plications. Those include audiovisual applications such as video cameras, information processing and telecommunications applica-
tions such as floppy disk drives, CD-ROM drives, printers, cellular phones, and control applications for motors and air conditioners.
To permit application-specific IC (ASIC) development, the Series has a dedicated expansion bus, independent of the core's internal
buses, that simplifies the task of designing the interface between the microcomputer core and the custom logic. This bus specifica-
tion opens the door to the flexible addition of peripheral functions. Panasonic now provides a microcomputer core for ASIC applica-
tions that features this expansion bus as standard equipment.
Major Application Areas
Information and communications equip-
ment, portable equipment, audio-visual
equipment, computer peripherals, home
appliances etc.
23
Microcomputer Family
Microcomputer Family
(
)
)
(
AM2 MN102 Series
AM2 MN102 Series
ꢀ
AM2 (MN102) 16-bit Single-chip Microcontroller Series Specifications
Serial Interfaces
ADC Built-in
0.05/3.0 to 3.6 LQFP128-P-1818C
MN102H460B
4K
63
82
54
50
16
10
5
6
1
0
3
0
2
2
0
3
0
0
12
8
Type
0.1/2.0 to 3.6
TQFP128-P-1414B
LQFP100-P-1414
MN102H60G
MN102H60K
MN102HF60G
128K
256K
128K
256K
4K
10K
4K
MLGA100-L-1010
M
LQFP100-P-1414
LQFP100-P-1414
MLGA100-L-1010
0.058/3.0 to 3.6
62.5/3.0 to 3.6
F
MN102HF60K
MN102L59D
10K
LQFP100-P-1414
LQFP064-P-1414
TQFP128-P-1414B
TQFP128-P-1414A
M
F
64K
2K
0.1/4.5 to 5.5
52
66
24
50
9
3
5
0
0
2
2
0
2
0
0
0
0
12
12
MN102LF59D
MN102H730FGT
MN102H73G
MN102H73K
MN102HF73G
MN102HF73K
ADC-DAC
10K
Built-in Type
128K
256K
128K
256K
M
0.058/3.0 to 3.6
62.5/3.0 to 3.6
12K
10K
12K
10
4
105
F
TQFP128-P-1414B
LQFP100-P-1414
0.058/3.0 to 3.6
62.5/3.0 to 3.6
MN102H950F
10K
63
66
47
36
10
4
5
2
0
0
2
0
2
2
0
0
0
1
12
12
4
4
TV Channel
Selector
MN102H75K
MN102HF75K
MN102H85K
MN102HF85K
MN102H90M
MN102L35G
MN102LP35G
MN102H74D
MN102H74G
MN102HF74G
M
F
256K
8K
0.083/3.0 to 3.6 QFP084-P-1818E
M
F
256K
384K
144K
64K
8K
0.083/3.0 to 3.6 SDIP064-P-0750C
0.083/3.0 to 3.6 QFP160-P-2828F
50
36
4
10
2
2
0
2
0
0
0
0
0
0
2
3
1
0
0
0
1
3
1
12
12
8
4
4
4
M
M
E
20K
111 41
5K 0.167/4.75 to 5.25 SDIP064-P-0750C
50
27
USB Built-in
Type
M
F
0.0833/3.0 to 3.6
4K
LQFP100-P-1414
77
54
10
4
0
2
2
0
0
8
62.5/3.0 to 3.6
128K
[Internal ROM type] M:Mask ROM , E:EPROM , F:FLASH, ----㧦Extern
[Package]
٤
:under planning , ꢀ:under development , ꢁ:ES(Engineering Sample) available (All packages are lead (Pb) free.) ꢀ
Note on Naming
1: If the additional digits for customer ROM version, etc. should produce a device name exceeding 12 characters,
we reduce it to 12 characters with the following schema.
The final device name is determined on delivery specification documents.
Full device name (13 or more characters)
MN102xxxxxx…
Abbreviated name (12 characters)
MNPxxxxxx…
2: Operating voltage and frequency may vary depending on whether models feature built-in EPROM, built-in flash memory, or
mask ROM.
24
相关型号：
MN102H60R
Microcontroller, 16-Bit, MROM, MN10200 CPU, 34MHz, CMOS, PQFP100, 14 X 14 MM, PLASTIC, LQFP-100
PANASONIC
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