MN38662S [PANASONIC]
NTSC-Compatible CCD Video Signal Delay Element; NTSC兼容的CCD视频信号延时元
| 型号： | MN38662S |
| 厂家： | 
PANASONIC |
| 描述： | NTSC-Compatible CCD Video Signal Delay Element |
| 文件： | 总4页 (文件大小：60K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
CCD Delay Line Series
MN38662S
NTSC-Compatible CCD Video Signal Delay Element
Overview
Pin Assignment
The MN38662S is a CCD signal delay element for video
signal processing applications.
It contains such components as a threefold-frequency
circuit, a shift register clock driver, charge I/O blocks,
two CCD analog shift registers switchable between 681
and 605 stages, a clamp bias circuit, resampling output
amplifiers, and booster circuits.
XIC
VSS3
XIV
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
PCOUT
&
VCOIN
VDD3
–VBB
VSS2
VINC1
N.C.
When the switch input is "L" level, the MN38662S
samples the input using the supplied clock signal with a
frequency of three times the NTSC color signal subcarrier
frequency (3.579545 MHz) and, after adding in the at-
tached filter delay, produces independent delays of 1 H
(the horizontal scan period) each for the two lines. When
the switch input is "H" level, the MN38662S disables the
threefold-frequency circuit and samples the input with
the image sensor drive frequency (9.53496 MHz or
9.545454 MHz) for the camera's 510 horizontal pixels
and, after adding in the attached filter delay, produces
independent delays of 1 H (the horizontal scan period)
each for the two lines.
VDD2
VINVC
VGC1
VO1C
VDD1
VINVY
SW
VINC2
VGC2
VO2Y
VSS1
( TOP VIEW )
SOP020-P-0300
Features
Single 4.8 V power supply
Choice of camera and VCR modes, so that both the
camera and VCR portions of a video camera with 510
horizontal pixels can use the same MN38662S for sig-
nal processing
Applications
Video cameras
1
MN38662S
CCD Delay Line Series
Block Diagram
Booster
circuit
Voltage
generator
Clamp
circuit
Bias circuit
Mode switch
Voltage
generator
79-stage
analog
shift
L
L
6
Charge
input
VINVC
H
block
8
602-stage
analog
shift
register
H
H
Resampling
output amplifier
VO1C
Charge
detector
3-stage
analog
shift
4
Charge
input
block
VINC1
register
L
L
L
register
H
L
3-stage
analog
shift
15
Charge
input
block
VINVY
H
11
602-stage
analog
shift
H
H
Charge
detector
Resampling
output amplifier
register
VO2Y
13
79-stage
analog
shift
Charge
input
block
VINC2
register
L
L
register
L
H
øS driver
øR driver
øSH driver
20
XIV
H
L
H
1/3rd
frequency
divider
Waveform
amplifier
adjustment
block
Waveform
adjustment
block
ø1 driver
1
XIC
ø2 driver
Timing
adjustment
VCO
L
H
Phase
comparator
Substrate bias
generator
L
H
VSS
2
CCD Delay Line Series
MN38662S
Application Circuit Example
+
–
4.8V
10µF
4.8V or GND
0.01µF
0.01µF
0.1µ
0.1µ
0.1µ
Booster
circuit
Voltage
generator
Clamp
circuit
Bias circuit
Mode switch
Voltage
generator
Signal
input
79-stage
analog
shift
L
L
VINVC
+
6
4
Charge
input
–
H
0.47µF
VO1C
block
8
602-stage
analog
shift
register
H
H
Resampling
output amplifier
Charge
detector
Signal
input
Signal
output
(1C)
3-stage
analog
shift
VINC1
+
Charge
input
block
register
–
L
0.47µF
L
L
register
H
L
Signal
input
3-stage
analog
shift
VINVY 15
+
Charge
input
block
–
H
0.47µF
VO2Y
11
602-stage
analog
shift
H
H
Charge
detector
Resampling
output amplifier
register
Signal
input
Signal
output
(2Y)
VINC2 13
+
79-stage
analog
shift
Charge
input
block
register
–
0.47µF
L
L
Clock
input
register
L
H
øS driver
øR driver
øSH driver
XIV
20
1
H
L
1000pF
Clock
input
H
1/3rd
frequency
divider
Waveform
amplifier
adjustment
block
Waveform
adjustment
block
ø1 driver
XIC
1000pF
ø2 driver
Timing
adjustment
VCO
L
H
Phase
comparator
Substrate bias
generator
L
H
0.01µF
0.01µF
1000pF
820Ω
Note: If the capacitor attached to pin 18 has a polarity, attach the negative pole to pin 18.
3
MN38662S
CCD Delay Line Series
Package Dimensions (Unit:mm)
SOP020-P-0300
12.60±0.20
20
11
1.10±0.20
0 to 10°
0.30min.
1
10
1.27
(0.6)
0.40±0.10
SEATING PLANE
4
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