MN662724RPE [PANASONIC]
Signal Processing LSI for CD Players; 信号处理LSI的CD播放机
| 型号： | MN662724RPE |
| 厂家： | 
PANASONIC |
| 描述： | Signal Processing LSI for CD Players |
| 文件： | 总7页 (文件大小：45K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
For Audio Equipment
MN662724RPE
Signal Processing LSI for CD Players
Overview
The MN662724RPE is a CD signal processing LSI that,
on a single chip, combines an optics servo for the CD
player (focus, tracking, and traverse servos), digital sig-
nal processing (EFM demodulation and error correction),
and digital servo processing for the spindle motor.
(Other)
Built-in playback pitch control function (normal
speed only)(±13%)
Built-in support for jitter-free disc rotation synchro-
nization playback
Oscillator shutdown mode
Power management mode
Features
Operating voltage 4.5 to 5.5V
(Optics servo)
Focus, tracking, and traverse servos
Automatic adjustment functions for FO/TR gain,
FO/TR offset, and FO/TR balance
Built-in D/A converter for drive voltage output
Built-in dropout countermeasures
Anti-shock functions
Applications
CD Players
Built-in track cross counter
(Digital signal processing)
Built-in DSL and PLL
Frame synchronization detection, holding, and
insertion
Subcode data processing
Q data CRC check
Built-in Q data register
CIRC error detection and correction
C1 decoder: duplex error correction
C2 decoder: triplex error correction
Built-in 16-K bits of RAM for de-interleaving
Audio data interpolation
Average, hold of previous values
Soft muting
Digital attenuation (256 levels)
Software attenuation (256 levels)
Auto cue detection function
Digital audio interface (EIAJ format)
Two audio data serial interfaces:
One switchable between bit rates of 64 fs and
48 fs; the other fixed at 48 fs.
(Spindle motor servo)
CLV digital servo
Switchable servo gain
MN662724RPE
For Audio Equipment
Pin Assignment
BYTCK/TRVSTOP
CLDCK
FCLK
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
LDON
BDO
RFDET
TRCRS
OFT
IPFLAG
FLAG
CLVS
CRC
VDET
RFENV
TE
DEMPH
FLAG6/RESY
SDAT48
TEST
FE
TBAL
FBAL
VREF
FOD
AVDD1
LRCK48
AVSS1
TRD
KICK
ECS
ECM
PC
TVD
TRV
BCLK48
RSEL
CSEL
PSEL
MSEL
SSEL
(TOP VIEW)
QFS080-P-1414
For Audio Equipment
MN662724RPE
Block Diagram
66
CLVS
67
74
72
AVSS1
AVDD1
CRC
13
BLKCK
62
65
64
CLDCK
56
FLAG
IPFLAG
SBCK
55
SUBC
68
69
DEMPH
FLAG6/RESY
6
TX
80
SSEL
SQCK
SUBQ
14
15
51
AVSS2
50
24
23
ECM
PC
AVDD2
53
52
PCK/DSLB
2
73
3
70
1
EFM/CK384
48
LRCK
PLLF
41
LRCK48
SRDATA
SDAT48
BCLK
BCLK48
DMUTE
PLLF2
47
DSLF
45
IREF
46
75
16
DRF
44
ARF
76
RSEL
21
26
29
78
PSEL
TRV
KICK
VREF
9
MLD
7
61
25
22
27
28
31
30
12
11
42
40
54
MCLK
8
BYTCK/TRVSTOP
ECS
TVD
TRD
FOD
MDATA
49
VCOF
19
SMCK
63
TBAL
FBAL
FCLK
20
PMCK
77
TLOCK
FLOCK
PLAY
LDON
TOFS
CSEL
79
MSEL
59
X2
X1
58
43
10
17
WVEL
SENSE
STAT
SERVO
TIMING GENERATOR
A/D CONVERTER
INPUT PORT
MN662724RPE
For Audio Equipment
Pin Descriptions
Pin No.
Symbol
I/O
Function Description
SRDATA bit clock output.
1
BCLK
O
2
3
LRCK
SRDATA
DVDD1
DVSS1
O
O
I
Left/right channel discrimination signal output.
Serial data output.
4
Power supply for digital circuits.
Ground for digital circuits.
5
I
6
TX
O
I
Digital audio interface output signal.
7
MCLK
MDATA
MLD
Microcomputer command clock input. (Data is latched at rising edge.)
Microcomputer command data input.
8
I
9
I
Microcomputer command load signal input.
"L" level: load.
10
11
12
13
14
15
16
17
SENSE
FLOCK
TLOCK
BLKCK
SQCK
O
O
O
O
I
Sense signal output. (OFT, FESL, NACEND, NAJEND, SFG, and NWTEND)
Focus servo pull-in signal.
"L" level: pull-in state.
"L" level: pull-in state.
Tracking servo pull-in signal.
Subcode block clock signal (fBLKCK=75Hz)
External clock input for subcode Q register
Subcode Q data output
SUBQ
O
I
DMUTE
STAT
Muting input. (Effective only for an output bit rate of 64 fs) "H" level: muting.
Status signal.
O
(CRC, CUE, CLVS, TTSTOP, FCLV, SQOK, FLAG6, SENSE, FLOCK,
and TLOCK)
18
19
RST
I
Reset input.
"L" level: reset.
If MSEL is "H" level, 8.4672 MHz clock signal is outputted.
If MSEL is "L" level, 4.2336 MHz clock signal is outputted.
88.2kHz clock signal output.
SMCK
O
20
21
22
23
24
25
26
27
28
29
PMCK
TRV
TVD
PC
O
O
O
O
O
O
O
O
O
I
Traverse forced feed output.
Traverse drive output.
(tristate)
Spindle motor ON signal.
"L" level: ON (default).
ECM
ECS
Spindle motor drive signal (forced mode output). (tristate)
Spindle motor drive signal (servo error signal output)
KICK
TRD
FOD
VREF
Kick pulse output.
Tracking drive output.
Focus drive output.
(tristate)
Reference voltage for D/A output (TVD, ECS, TRD, FOD, FBAL, TBAL,
and TOFS).
30
31
32
33
34
35
36
37
FBAL
TBAL
FE
O
O
I
Focus balance adjustment output.
Tracking balance adjustment output.
Focus error signal input.
Tracking error signal input.
RF envelope signal input.
(analog input)
(analog input)
(analog input)
TE
I
RFENV
VDET
OFT
I
I
Vibration detection signal input. "H" level: vibration detected.
I
Offtrack signal input.
"H" level: offtrack.
(analog input)
TRCRS
I
Track cross signal input.
For Audio Equipment
MN662724RPE
Pins Descriptions (continued)
Pin No.
Symbol
I/O
Function Description
RF detection signal input. "L" level: detected.
38
RFDET
I
39
40
41
42
43
44
45
46
47
48
49
50
BDO
LDON
PLLF2
PLAY
WVEL
ARF
I
O
Dropout signal input.
"H" level: dropout
"H" level: ON.
Laser ON signal output.
PLL loop-filter characteristic switching pin.
Play signal output.
I/O
O
"H" level: play.
O
Double-speed status signal output.
RF signal input.
"H" level: double-speed.
I
IREF
I
Reference current input pin
DSL bias pin.
DRF
I
DSLF
PLLF
VCOF
AVDD2
I/O
I/O
I/O
I
DSL loop-filter pin.
PLL loop-filter pin.
VCO loop-filter pin.
Power supply for analog circuits (DSL, PLL, D/A converter output, and A/D
converter).
51
52
AVSS2
I
Ground for analog circuits (DSL, PLL, D/A converter output, and A/D
converter).
EFM
O
EFM signal output. • EFM output.
or CK384
• Crystal oscillator 16.9344 MHz output.
• 384 fs output from signal processing block. (During
variable-pitch operation, this is the VCO clock.)
Commands permit switching among the above three outputs.
53
PCK
or DSLB
TOFS
O
Clock for PLL or DSL balance output.
fPCK=4.3218MHz
54
55
56
57
58
59
60
61
O
O
I
Tracking offset adjustment output.
Subcode serial output.
SUBC
SBCK
VSS
Clock input for subcode serial output.
Ground for oscillator circuit.
Crystal oscillator circuit input pin.
I
X1
I
f=16.9344MHz, 33.8688MHz
X2
O
I
Crystal oscillator circuit output pin. f=16.9344MHz, 33.8688MHz
Oscillator circuit power supply.
VDD
BYTCK or
TRVSTOP
CLDCK
FCLK
IPFLAG
FLAG
CLVS
O
During default operation, byte clock signal output.
During command execution, traverse stop signal output. "H" level: stop mode.
62
63
64
65
66
O
O
O
O
O
Subcode frame clock signal output pin.
Crystal frame clock signal output.
Interpolation flag signal output.
Flag signal output.
(fCLDCK=7.35kHz)
(fFCLK=7.35kHz)
"H" level: interpolation.
Spindle servo phase synchronization signal output. "H" level: CLV.
"L" level: rough servo.
67
68
CRC
O
O
Subcode CRC check result output.
De-emphasis detection signal output.
"H" level: OK. "L" level: no good.
"H" level: on.
DEMPH
MN662724RPE
For Audio Equipment
Pin Descriptions (continued)
Pin No.
Symbol
I/O
Function description
69
FLAG6
O
During default operation, FLAG6 output, that is the resetting signal for the
address of RAM used to de-interleave error correction data. "L" level: address reset.
During command execution, RESY output, that is the frame resynchronization
signal. "H" level: synchronized. "L" level: out of sync.
or RESY
70
71
72
73
74
75
76
SDAT48
TEST
O
I
Serial data output for bit rate 48 fs.
Test pin.
Keep this at "H" level.
AVDD1
LRCK48
AVSS1
I
Power supply for digital circuits.
O
I
Left/right channel discrimination signal output for bit rate 48 fs.
Ground for digital circuits.
BCLK48
RSEL
O
I
Bit clock output for bit rate 48 fs.
RF signal polarity selection pin. "H" level: bright level is "H."
"L" level: bright level is "L."
77
CSEL
I
Crystal oscillator frequency specification pin. "H" level: 33.8688 MHz.
"L" level: 16.9344 MHz
78
79
PSEL
I
I
Test pin.
Keep this at "L" level.
MSEL
SMCK pin output.
SMCK frequency selection pin.
"H" level: 8.4672 MHz.
"L" level: 4.2336 MHz.
80
SSEL
I
SUBQ pin output mode selection pin.
"H" level: Buffered Q code mode.
"L" level: CLDCK synchronization mode.
For Audio Equipment
Package Dimensions (Unit: mm)
QFS080-P-1414
MN662724RPE
16.2±0.2
14.0±0.2
60
41
40
61
80
21
1
20
1.1±0.1
+0.10
0.65
-0.05
0.3
0.15
SEATING PLANE
0.55±0.1
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