EPF8032S [PCA]
100BX Module for Multi-port Application with Enhanced Common Mode Attenuation; 对于多端口应用100BX模块，加强了共模衰减
| 型号： | EPF8032S |
| 厂家： | 
PCA ELECTRONICS INC. |
| 描述： | 100BX Module for Multi-port Application with Enhanced Common Mode Attenuation |
| 文件： | 总2页 (文件大小：61K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
100BX Module for
Multi-port Application with
Enhanced Common Mode Attenuation
E L E C T R O N I C S I N C .
EPF8032S
• Optimized for DP83840A/Twister combination •
• Recommended for use with ICS1890 series, SSI TSC78Q2120 chips •
(with appropriate circuitry)
• Guaranteed to operate with 8 mA DC bias at 70°C •
• Complies with or exceeds IEEE 802.3, 10 BT/100 BX Standards •
Electrical Parameters @ 25° C
Insertion Loss
Return Loss
(dB Min.)
Common Mode Rejection
Crosstalk (dB Min.)
[Between Channels]
OCL
@ 70°C
(dB Max.)
(dB Min.)
10-100
MHz
0.1-80
MHz
100
MHz
150
MHz
1-10
MHz
60
MHz
100
MHz
30-100
MHz
200-300
MHz
500
MHz
5-10
MHz
100 KHz, 0.1 Vrms
8 mA DC Bias
Cable Side
Xmit Rcv Xmit Rcv Xmit Rcv Xmit Rcv Xmit Rcv Xmit Rcv Xmit Rcv Xmit Rcv Xmit Rcv
-1 -1 -1 -1 -3.5 -3 -18 -18 -18 -18 -10 -10 -35 -30 -20 -20 -15 -15
350µH
-40
-30
•
Isolation : 1500 Vrms
•
Impedance : 100 Ω
•
Rise Time : 3.0 nS Max.
•
Schematic
Transmit Channel
Receive Channel
1(12)
34(23)
7(18)
1 : 1
100BX
40(29)
8(19)
9(20)
2(13)
3(14)
4(15)
33(22)
32(21)
1 : 1
39(28)
38(27)
10BT
5(16)
0.5 : 1
Dimensions
Package
(Inches)
(Millimeters)
A
Dim.
Min.
1.110 1.130
Max. Nom. Min. Max. Nom.
N
J
A
B
C
D
E
F
G
H
I
28.19 28.70
11.94 12.45
.470
.235
.950
.008
.050
.620
.016
.008
.085
0°
.490
.255
Typ.
.012
Typ.
.640
.022.
.012
Typ.
8°
5.97
6.48
24.13 Typ.
40
Solder Pad Layout
Q
21
20
PCA
EPF8032S
Date Code
.203
1.27
15.75 16.26
.305
Typ.
P
B
1
.406
.203
2.16
0°
.559
.305
Typ.
8°
J
K
L
D
M
.045
Typ.
1.14
Typ.
M
N
P
Q
.030
.050
.090
.670
.762
1.27
I
2.29
K
C
17.02
E
L
H
F
G
CSF8032Sa Rev. 2 5/16/97
PCA ELECTRONICS, INC.
16799 SCHOENBORN ST.
NORTH HILLS, CA 91343
TEL: (818) 892-0761
FAX: (818) 894-5791
http://www.pca.com
100BX Module for
Multi-port Application with
Enhanced Common Mode Attenuation
E L E C T R O N I C S I N C .
The circuit below is a guideline for interconnecting PCA’s EPF8032S with National DP83840A and DP83223 twister chip set
for 10/100 Mb/s applications. Further details can be obtained from the chip manufacturer application notes. Please
consult PCA for applications help regarding the SSI78Q2120 or ICS1890 series parts or consult with the respective
application notes.
Typical insertion loss of the isolation transformer is 0.5dB. This parameter covers the entire spectrum of the encoded
signals in 10/100 protocols. Under terminated conditions, to transmit a 2V pk-pk signal across the cable, you must adjust
the TXREF resistor of the twister chip to get at least 2.12V pk-pk across pins 16-15.
Note that significant low frequency response improvement can be obtained in the system (improving equalization effects) if
the DC blocking capacitors were not used; this can only be done by choosing a different pinout for the 10 Base-T receiver
side. This is accomplished without impacting any other behavior. If any user has a need to improve this feature, please
consult with the PCA Technical support group. Parts similar to EPF8032S are available from several LAN magnetics
vendors.
It is recommended that system designers do not ground the receiver side center tap, via a capacitor. This may worsen
EMI, specifically if the secondary “common mode termination” is pulled to chassis ground as shown.
The phantom resistors shown around the connector have been known to suppress unwanted radiation that unused wires
pick up from the immediate environment. Their placement and use are to be considered carefully before a design is
finalized.
The “common mode termination” load of 75 Ω shown from the center taps of the secondary may be taken to chassis ground
via a cap of suitable value. This depends upon user’s design, EMI margin etc.
It is recommended that there be a neat separation of ground planes in the layout. It is generally accepted practice to limit
the plane off at least 0.05 inches away from the chip side pins of EPF8032S. There need not be any ground plane beyond
this point.
For best results, PCB designer should design the outgoing traces preferably to be 50 Ω, balanced and well coupled to
achieve minimum radiation from these traces.
Typical Application Circuit for UTP (only one port shown)
0.10µF {Note 1}
+
-
7
8
8
34
33
32
40
39
38
RXD
TXU
Rcv
50Ω
50Ω
7
1
5
0.1µF
{Note 1}
1000pF
75Ω
12.1Ω
12.1Ω
4
4
+
-
RJ45*
Xmit
5
1
1
2
75Ω
1000pF
2000V
2
6
3
+
-
Isolation Cap
EPF8032S
TXO
+
-
TD
PMRD
Chassis
Ground
RXI
DP83840A
DP83223
SD
PMID
+
SD
RD
Other pull down/up resistors not shown, for clarification please refer to National’s application notes.
-
+
Notes : 1. See text above for clarification.
2. Hub side connections show only one port.
-
CSF8032Sb Rev. 2 5/16/97
PCA ELECTRONICS, INC.
16799 SCHOENBORN ST.
NORTH HILLS, CA 91343
TEL: (818) 892-0761
FAX: (818) 894-5791
http://www.pca.com
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