PI3VDP3212ZLSE [PERICOM]
2-Lane DisplayPort Rev 1.2 Compliant Switch;
| 型号： | PI3VDP3212ZLSE |
| 厂家： | 
PERICOM SEMICONDUCTOR CORPORATION |
| 描述： | 2-Lane DisplayPort Rev 1.2 Compliant Switch |
| 文件： | 总12页 (文件大小：1290K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
PI3VDP3212
2-Lane DisplayPort™ Rev 1.2 Compliant Switch
Description
Features
ꢀÎ2-lane, 1:2 mux/demux that will support RBR, HBR1, or
Pericom Semiconductor’s PI3VDP3212 mux/demux is targeted
for next generation digital video signals. is device can be used
to connect a DisplayPort™ Source to two Independent Display-
Port Sinks or to connect two DisplayPort sources to a single DP
display.
HBR2
ꢀÎ1-channel 1:2 mux/demux for DP_HPD signal
ꢀÎ1-differential channel 1:2 mux/demux for DP_Aux signal
with support up to 720Mbps
e newly released DisplayPort spec requires a data rate of 5.4
Gbps. Pericom's solution has been specifically designed around
this standard and will support such signals.
ꢀÎInsertion Loss for high speed channels @ 2.7 GHz: -1.7dB
ꢀÎ-3dB Bandwidth for high speed channels: 4.7GHz
ꢀÎReturn loss for high speed channels @ 2.7GHz: -16dB
ꢀÎLow Bit-to-Bit Skew , 7ps max (between '+' and '-' bits)
ꢀÎLow Crosstalk for high speed channels: -25dB@5.4 Gbps
Application
Routing of DisplayPort signals with low signal attenuation be-
tween source and sink.
ꢀÎLow Off Isolation for high speed channels: -25dB@5.4 Gbps
Operating Range: 3.3V +/-10%
ꢀÎV
DD
ꢀÎESD Tolerance: 2kV HBM
ꢀÎLow channel-to-channel skew, 35ps max
ꢀÎPackaging (Pb-free & Green):
à 32 TQFN (ZL)
Block Diagram
D0+
D0+A
D0-A
D1+A
D1-A
-
D0
D1+
-
D1
D0+B
D0-B
D1+B
D1-B
AUX+
AUX
HPD
AUX+ A
AUX-A
HPD A
-
AUX+ B
AUX- B
HPD B
OE
Logic
Control
SEL
AUX_SEL
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PI3VDP3212
2-Lane DisplayPort™ Rev 1.2 Compliant Switch
Pin Assignment (TQFN-32)
Truth Table
AUX_
SEL
OE
SEL
Function
Low
Low
Low
Low
High
Low
Low
High
High
x
Low
High
Low
High
x
Port A active for all channels
Port A for HS, port B for HPD/AUX
Port B for HS, port A for HPD/AUX
Port B active for all channels
1
27
26
25
24
23
22
21
20
19
18
17
D0+
D1+A
D1-A
All I/O's are hi-z and IC is power down
2
D0-
3
VDD
D0+B
D0-B
4
D1+
5
D1-
D1+B
D1-B
GND
6
AUX+
7
GND
AUX-
8
VDD
HPD
9
AUX+A
AUX-A
HPD_A
VDD
10
SEL
11
OE
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PI3VDP3212
2-Lane DisplayPort™ Rev 1.2 Compliant Switch
Pin Description
pin#
pin Name Signal Type Description
1
2
3
4
5
6
7
8
9
D0+
D0-
I/O
positive differential signal 0 for COM port
I/O
negative differential signal 0 for COM port
3.3V +/-10% power supply
VDD
D1+
Power
I/O
positive differential signal 1 for COM port
negative differential signal 1 for COM port
positive differential signal for AUX COM port
negative differential signal for AUX COM port
HPD for COM port
D1-
I/O
AUX+
AUX-
HPD
VDD
I/O
I/O
I/O
Power
3.3V +/-10% power supply
switch logic control.
10
SEL
I
If HIGH, then path B is selected for high speed channels only
If LOW, then path A is selected for high speed channels only
Output enable. if OE is low, IC is enabled. If OE is high, then IC is power
down and all I/Os are hi-z
11
OE
I
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
VDD
Power
I/O
3.3V +/-10% power supply
HPD_B
AUX-B
AUX+B
VDD
HPD for port B
I/O
negative differential signal for AUX, port B
positive differential signal for AUX, port B
3.3V +/-10% power supply
I/O
Power
I/O
HPD_A
AUX-A
AUX+A
VDD
HPD for port A
I/O
negative differential signal for AUX, port A
positive differential signal for AUX, port A
3.3V +/-10% power supply
I/O
Power
Ground
I/O
GND
Ground
D1-B
negative differential signal 1 for port B
positive differential signal 1 for port B
negative differential signal 0 for port B
positive differential signal 0 for port B
negative differential signal 1 for port A
positive differential signal 1 for port A
Ground
D1+B
I/O
D0-B
I/O
D0+B
D1-A
I/O
I/O
D1+A
GND
I/O
Ground
Power
I/O
VDD
3.3V +/-10% power supply
D0-A
D0+A
negative differential signal 0 for port A
positive differential signal 0 for port A
switches only the AUX and HPD channels from port A vs. port B
If High, path B is selected
I/O
32
AUX_SEL
I
If LOW, path A is selected
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PI3VDP3212
2-Lane DisplayPort™ Rev 1.2 Compliant Switch
Maximum Ratings
(Above which useful life may be impaired. For user guidelines, not tested.)
Note: Stresses greater than those listed under MAXI-
MUM RATINGS may cause permanent damage to the
device. is is a stress rating only and functional op-
eration of the device at these or any other conditions
above those indicated in the operational sections of this
specification is not implied. Exposure to absolute maxi-
mum rating conditions for extended periods may affect
reliability.
Storage Temperature .......................................................... –65°C to +150°C
Supply Voltage to Ground Potential ....................................–0.5V to +4.2V
DC Input Voltage ..................................................................... –0.5V to V
DD
DC Output Current .............................................................................120mA
Power Dissipation ................................................................................... 0.5W
DC Electrical Characteristics for Switching over Operating Range (TA = –40°C to +85°C, VDD =
3.3V ±10%)
(1)
(1)
Typ
Parameter Description
Test Conditions
Min
Max
Units
V
V
V
Input HIGH Voltage
Input LOW Voltage
Guaranteed HIGH level
Guaranteed LOW level
1.5
IH
IL
0.75
–1.8
5
V
Clamp Diode Voltage, Dx
Input HIGH Current
V
V
= Max., I = –18mA
–1.6
DD
DD
IN
IK
I
I
= Max., V = V
IH
IN
DD
Input LOW Current
V
= Max., V = GND
5
DD
DD
IN
IL
µA
I/O leakage when part is off for side
band signals only (DDC, AUX, HPD)
I
V
V
= 0V, V
= 0V to 3.6V
20
INPUT
OFF_SB
On resistance between input to out-
put for high speed signals
= 3.3V, Vinput = 0V to 2V,
= 20mA
DD
R
R
10
7
Ohm
Ohm
ON_HS
I
INPUT
On resistance between input to out-
put for side-band signals (AUX)
V
INPUT
= 3.3V, Vinput = 0 to 3.3V,
DD
ON_AUX
I
= 20mA
Aux_ss
HPD_I
HPD_O
Signal Swing Tolerance in Aux path
Input voltage tolerance on HPD path
Output voltage on HPD path
V
= 3.0V
–0.5
3.6
5.5
3.6
V
V
V
DD
HPD input from 0V to 5.25V
Power Supply Characteristics (TA = –40°C to +85°C)
(1)
(1)
Typ
Parameter
Description
Test Conditions
Min
Max
Units
I
CC
Quiescent Power Supply Current
V
= 3.3V., V = GND or V
320
500
uA
DD
IN
DD
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PI3VDP3212
2-Lane DisplayPort™ Rev 1.2 Compliant Switch
Dynamic Electrical Characteristics over Operating Range (TA = -40º to +85ºC, VDD = 3.3V ±10%)
Parameter Description
Test Conditions
Typ.
Max Units
f= 2.7 GHz
-25dB
See Fig. 1 for Measurement
Setup
X
Crosstalk on High Speed Channels
TALK
f = 1.35 GHz -32dB
f= 2.7 GHz -22dB
dB
See Fig. 2 for Measurement
Setup,
O
IRR
OFF Isolation on High Speed Channels
f = 1.35 GHz -30dB
Differential Insertion Loss on High Speed
Channels
I
@5.4Gbps (see figure 3)
@ 2.7GHz
-1.7
-16
4.7
1.5
dB
LOSS
Differential Return Loss on high speed
channels
R
dB
loss
Bandwidth -3dB for Main high speed
path (Dx )
BW_Dx
See figure 3
GHz
GHz
BW_AUX/
HPD
-3dB BW for AUX and HPD signals
See figure 3
time it takes to switch from port A to port
B
Tsw a-b
1
us
time it takes to switch from port B to port
A
Tsw b-a
Tstartup
Twakeup
1
us
us
us
Vdd valid to channel enable
10
10
Enabling output by changing OE from
low to High
1. For Max. or Min. conditions, use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at V = 3.3V, T = 25°C ambient and maximum loading.
DD
A
Switching Characteristics (T = -40º to +85ºC, V
= 3.3V±10%)
DD
A
Parameter
Description
Min.
Typ.
Max.
Units
T
Propagation delay (input pin to output pin)
Bit-to-bit skew within the same differential pair
Channel-to-channel skew
80
5
ps
ps
ps
pd
t
t
b-b
50
ch-ch
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PI3VDP3212
2-Lane DisplayPort™ Rev 1.2 Compliant Switch
50
+
+
BALANCED
PORT1
50
–
–
50
50
+
+
BALANCED
PORT2
–
–
DUT
Fig 1. Crosstalk Setup
50
50
+
+
BALANCED
PORT1
–
–
+
BALANCED
PORT2
–
DUT
Fig 2. Off-isolation setup
+
+
BALANCED
PORT1
BALANCED
–
PORT2
–
DUT
Fig 3. Differential Insertion Loss set up
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PI3VDP3212
2-Lane DisplayPort™ Rev 1.2 Compliant Switch
-20.0
-30.0
-40.0
-50.0
-60.0
-70.0
-80.0
-90.0
-100.0
1.00E+09
1.00E+10
1.00E+07
1.00E+08
Frequency (Hz)
Fig 4. Xtalk for high speed channels (D0 and D1)
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PI3VDP3212
2-Lane DisplayPort™ Rev 1.2 Compliant Switch
-0.0
-10.0
-20.0
-30.0
-40.0
-50.0
-60.0
-70.0
-80.0
1.00E+09
1.00E+10
1.00E+07
1.00E+08
Frequency (Hz)
Fig 5. Off Isolation for high speed channels (D0 an D1). Red is for path B and Blue is for path A
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PI3VDP3212
2-Lane DisplayPort™ Rev 1.2 Compliant Switch
-0.0
-1.0
-2.0
-3.0
-4.0
-5.0
-6.0
1.00E+09
1.00E+10
1.00E+07
1.00E+08
Frequency (Hz)
Fig 6. Insertion Loss for high speed channels, D0 and D1. Red is for path B and Blue is for path A
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PI3VDP3212
2-Lane DisplayPort™ Rev 1.2 Compliant Switch
Test Circuit for Electrical Characteristics(1-5)
2 * VDD
VDD
200-ohm
VIN
Pulse
Generator
VOUT
D.U.T
4pF
200-ohm
CL
RT
Notes:
1. C = Load capacitance: includes jig and probe capacitance.
L
2. R = Termination resistance: should be equal to Z
of the Pulse Generator
OUT
T
3. Output 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
4. Output 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
5. All input impulses are supplied by generators having the following characteristics: PRR ≤ MHz, Z = 50Ω, t ≤ 2.5ns, t ≤ 2.5ns.
O
R
F
6. e outputs are measured one at a time with one transition per measurement.
Switching Waveforms
V
DD
SEL
50%
50%
0V
V
t
PZL
t
PLZ
Output 1
OH
10%
V
V
OL
t
t
PHZ
PZH
OH
90%
V
Output 2
OL
Voltage Waveforms Enable and Disable Times
Switch Positions
Test
Switch
t
t
, t
(output on B-side)
(output on B-side)
2 * Vdd
GND
PLZ PZL
, t
PHZ PZH
Prop Delay
Open
Test Circuit for Dynamic Electrical Characteristics
Agilent PNA-L Network Analyzer
Balanced port 2
Balanced port 1
DUT
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PI3VDP3212
2-Lane DisplayPort™ Rev 1.2 Compliant Switch
Packaging Mechanical: 32-Contact TQFN (ZL)
DATE: 10/09/09
DESCRIPTION: 32-contact, Thin Fine Pitch Quad Flat No-Lead (TQFN)
PACKAGE CODE: ZL (ZL32)
REVISION: A
DOCUMENT CONTROL #: PD-2044
09-0125
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PI3VDP3212
2-Lane DisplayPort™ Rev 1.2 Compliant Switch
DATE: 11/11/13
DESCRIPTION: 32-contact, Thin Fine Pitch Quad Flat No-Lead (TQFN)
PACKAGE CODE: ZLS (ZLS32)
REVISION: --
DOCUMENT CONTROL #: PD-2175
Note:
For latest package info, please check: http://www.pericom.com/products/packaging/mechanicals.php
Ordering Information
Ordering Code
Package Code
Package Description
PI3VDP3212ZLE
PI3VDP3212ZLSE
ZL
Pb-free & Green, 32-contact TQFN
Pb-free & Green, 32-contact TQFN
ZLS
Notes:
• ermal characteristics can be found on the company web site at www.pericom.com/packaging/
• "E" denotes Pb-free and Green
• Adding an "X" at the end of the ordering code denotes tape and reel packaging
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