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PI3VDP612-AZHE [PERICOM]

4-Lane DisplayPort Rev 1.1a Compliant Switch with Triple Control Logic for Fast Switching;
PI3VDP612-AZHE
型号： PI3VDP612-AZHE
厂家： PERICOM SEMICONDUCTOR CORPORATION    PERICOM SEMICONDUCTOR CORPORATION
描述：

4-Lane DisplayPort Rev 1.1a Compliant Switch with Triple Control Logic for Fast Switching
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PI3VDP612-A  
4-Lane DisplayPort™ Rev 1.1a Compliant Switch  
with Triple Control Logic for Fast Switching  
Features  
Description  
Î 4-lane, 1:2 mux/demux that will support 2.7Gbps or  
Pericom Semiconductor’s PI3VDP612-A mux/demux is targeted  
for next generation digital video signals. is device can be used  
to connect a DisplayPort™ Source to two Independent Display-  
1.62Gbps DP rev 1.1a signals  
Î 1-channel 1:2 mux/demux for DP_HPD signal  
Port Sinks or to connect two DisplayPort sources to a single DP  
display.  
Î 1-differential channel 1:2 mux/demux for DP_Aux signal  
Î Insertion Loss for high speed channels @ 2.7 Gbps: -1.5dB  
Î -3dB Bandwidth for high speed channels of 3.25 Ghz  
Î Low Bit-to-Bit Skew , 7ps max (between '+' and '-' bits)  
Î Low Crosstalk for high speed channels: -33dB@2.7 Gbps  
Î Low Off Isolation for high speed channels: -26dB@2.7 Gbps  
e newly released DisplayPort spec requires a data rate of 2.7  
Gbps with AC coupled I/Os. Pericom's solution has been specifi-  
cally designed around this standard and will support such sig-  
nals.  
Î V Operating Range: 3.3V 10%  
DD  
Application  
Routing of DisplayPort signals with low signal attenuation be-  
tween source and sink.  
Î ESD Tolerance: +/-8kV contact on Ports A and B per  
IEC61000-4-2 Specification  
Î Low channel-to-channel skew, 35ps max  
Î Packaging (Pb-free & Green):  
à
à
-56 TQFN (ZFE)  
-42 TQFN (ZHE)  
Pin Description - 56-Pin  
Block Diagram  
D0+  
D0+A  
D0-A  
D1+A  
D1-A  
-
D0  
D1+  
1
2
48 GND  
AUX_SEL  
D0+  
-
D1  
47  
D2+A  
D2+  
D2-  
D3+  
D3-  
D2+A  
D2-A  
D3+A  
D3-A  
3
46  
D2-A  
D0-  
4
45  
D3+A  
D1+  
5
44  
D3-A  
D1-  
6
43  
D0+B  
VDD  
D0+B  
D0-B  
D1+B  
D1-B  
7
42  
D0-B  
D2+  
8
41  
D1+B  
D2-  
9
40  
D1-B  
D3+  
GND  
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
20  
39  
D3-  
D2+B  
D2+B  
D2-B  
D3+B  
D3-B  
38  
GND  
D2-B  
37  
AUX+  
AUX-  
HPD  
D3+B  
36  
D3-B  
35  
GND  
AUX+  
AUX  
HPD  
CAB_DET/LED  
AUX+ A  
AUX- A  
HPD A  
CAB_DETA/LEDA  
34  
-
CAB_DET/LED  
GND  
VDD  
33  
AUX+A  
32  
VDD  
AUX-A  
31  
AUX+ B  
AUX- B  
HPD B  
CAB_DETB/LEDB  
SEL1  
SEL2  
GND  
HPD_A  
30  
CAB_DET/LEDA  
GND  
29  
SEL2  
SEL1  
Logic  
Control  
AUX_SEL  
PS9056A  
07/12/11  
1
11-0103  
PI3VDP612-A  
4-Lane DisplayPort™ Rev 1.1a Compliant Switch  
with Triple Control Logic for Fast Switching  
Pin Description - 42-Pin  
D0+A  
1
2
38 D2+A  
AUX_SEL  
D0+  
37  
36  
35  
34  
33  
32  
31  
30  
29  
28  
27  
26  
25  
24  
23  
22  
D2-A  
3
D3+A  
4
D0-  
D3-A  
5
D1+  
D0+B  
6
D1-  
D0-B  
7
D2+  
D1+B  
8
D2-  
D1-B  
GND  
9
D3+  
D2+B  
10  
11  
12  
13  
14  
15  
16  
17  
D3-  
D2-B  
AUX+  
AUX-  
HPD  
D3+B  
D3-B  
VDD  
CAB_DET/LED  
VDD  
AUX+A  
AUX-A  
HPD_ A  
CAB_DETA/LED_A  
SEL1  
SEL2  
PS9056A  
07/12/11  
2
11-0103  
PI3VDP612-A  
4-Lane DisplayPort™ Rev 1.1a Compliant Switch  
with Triple Control Logic for Fast Switching  
Pin Description  
42-Package 56-Package  
Signal  
Type  
Pin #  
Pin #  
Pin Name  
Description  
ESD  
Logic control for AUX signals:  
if LOW then AUX from COM port will connect to  
AUX from port A.  
2
1
AUX_SEL  
Input  
If HIGH, then AUX from COM port will connect to  
AUX from port B.  
3
4
5
6
2
3
4
5
D0+  
D0-  
D1+  
D1-  
I/O  
I/O  
I/O  
I/O  
Positive Lane0 signal for common port  
Negative Lane0 signal for common port  
Positive Lane1 signal for common port  
Negative Lane1 signal for common port  
+/-7kV  
+/-7kV  
+/-7kV  
+/-7kV  
6, 17, 22, 27,  
34, 50, 55  
15, 26, 39  
V
Power  
3.3V Power Supply  
DD  
7
7
D2+  
D2-  
D3+  
D3-  
I/O  
I/O  
I/O  
I/O  
Positive Lane2 signal for common port  
Negative Lane2 signal for common port  
Positive Lane3 signal for common port  
Negative Lane3 signal for common port  
+/-7kV  
+/-7kV  
+/-7kV  
+/-7kV  
8
8
9
9
10  
10  
11, 16, 20, 21,  
*GND plate 28, 29, 35,  
48, 49, 56  
GND  
Ground  
Ground  
11  
12  
13  
12  
13  
14  
AUX+  
AUX-  
HPD  
I/O  
I/O  
I/O  
Positive AUX signal for common port  
Negative AUX signal for common port  
HPD for common port  
+/-8kV  
+/-8kV  
+/-8kV  
Common port pin for cable detect signal or LED  
common port  
14  
16  
15  
18  
CAB_DET/LED I/O  
+/-8kV  
Port Selection Control. If LOW, then port A is ac-  
tive. If HIGH, then port B is active  
SEL1  
Input  
Port Selection Control for HPD path and CAB_  
DET/LED path only:  
17  
19  
SEL2  
Input  
If LOW, then port A is active.  
If HIGH, then port B is active.  
Ground  
20  
21  
22  
GND  
GND  
Power  
Power  
Power  
Ground  
V
3.3V Power Supply  
DD  
CAB_DETB/  
LEDB  
Port B pin13 from dual mode DP connector or LED  
from port B  
18  
23  
I/O  
+/-8kV  
19  
20  
21  
24  
25  
26  
HPD_B  
AUX-B  
AUX+B  
I/O  
I/O  
I/O  
HPD for port B  
+/-8kV  
+/-8kV  
+/-8kV  
Negative AUX signal for Port B  
Positive AUX signal for Port B  
(Continued)  
PS9056A  
07/12/11  
3
11-0103  
PI3VDP612-A  
4-Lane DisplayPort™ Rev 1.1a Compliant Switch  
with Triple Control Logic for Fast Switching  
Pin Description  
42-Package 56-Package  
Signal  
Type  
Pin #  
Pin #  
Pin Name  
Description  
ESD  
CAB_DETA/  
LEDA  
Port A cable detect from dual mode DP connector  
or LED from port A  
22  
30  
I/O  
+/-8kV  
23  
24  
25  
27  
28  
29  
30  
31  
32  
33  
34  
35  
36  
37  
38  
40  
41  
42  
1
31  
32  
33  
36  
37  
38  
39  
40  
41  
42  
43  
44  
45  
46  
47  
51  
52  
53  
54  
HPD_A  
AUX-A  
AUX+A  
D3-B  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
HPD for port A  
+/-8kV  
+/-8kV  
+/-8kV  
+/-8kV  
+/-8kV  
+/-8kV  
+/-8kV  
+/-8kV  
+/-8kV  
+/-8kV  
+/-8kV  
+/-8kV  
+/-8kV  
+/-8kV  
+/-8kV  
+/-8kV  
+/-8kV  
+/-8kV  
+/-8kV  
Negative AUX signal for Port A  
Positive AUX signal for Port A  
Negative Lane3 signal for Port B  
Positive Lane3 signal for Port B  
Negative Lane2 signal for Port B  
Positive Lane2 signal for Port B  
Negative Lane1 signal for Port B  
Positive Lane1 signal for Port B  
Negative Lane0 signal for Port B  
Positive Lane0 signal for Port B  
Negative Lane3 signal for Port A  
Positive Lane3 signal for Port A  
Negative Lane2 signal for Port A  
Positive Lane2 signal for Port A  
Negative Lane1 signal for Port A  
Positive Lane1 signal for Port A  
Negative Lane0 signal for Port A  
Positive Lane0 signal for Port A  
D3+B  
D2-B  
D2+B  
D1-B  
D1+B  
D0-B  
D0+B  
D3-A  
D3+A  
D2-A  
D2+A  
D1-A  
D1+A  
D0-A  
D0+A  
Truth Table (SEL control)  
Function  
SEL 1/SEL2/AUX_SEL  
Port A is active  
L
Port B is active  
H
Notes:  
SEL1 is only for DP lanes  
SEL2 is only for HPD/CAB_DET signals  
AUX_SEL is only for AUX path  
PS9056A  
07/12/11  
4
11-0103  
PI3VDP612-A  
4-Lane DisplayPort™ Rev 1.1a Compliant Switch  
with Triple Control Logic for Fast Switching  
Maximum Ratings  
(Above which useful life may be impaired. For user guidelines, not tested.)  
Note: Stresses greater than those listed under MAXIMUM  
RATINGS may cause permanent damage to the device. This  
is a stress rating only and functional operation of the device  
at these or any other conditions above those indicated in the  
operational sections of this specification is not implied. Expo-  
sure to absolute maximum rating conditions for extended  
periods may affect reliability.  
Storage Temperature ....................................................–65°C to +150°C  
Supply Voltage to Ground Potential ................................–0.5V to +3.6V  
DC Input Voltage ..............................................................–0.7V to 3.6V  
DC Output Current .......................................................................120mA  
Power Dissipation ...........................................................................0.5W  
DC Electrical Characteristics for Switching over Operating Range (T = –40°C to +85°C, V  
=
DD  
A
3.3V ±10%)  
(1)  
(1)  
Typ  
Parameter  
Description  
Test Conditions  
Min  
Max  
Units  
V
V
V
Input HIGH Voltage  
Input LOW Voltage  
Clamp Diode Voltage  
Input HIGH Current  
Guaranteed HIGH level  
Guaranteed LOW level  
1.6  
IH  
IL  
0.75  
–1.2  
5
V
V
V
= Max., I = –18mA  
–0.7  
DD  
DD  
IN  
IK  
I
I
I
= Max., V = V  
IH  
IN  
DD  
Input LOW Current  
V
= Max., V = GND  
5
µA  
DD  
IN  
IL  
I/O leakage when part is off  
V
V
V
= 0V, V  
= 0V to 3.6V  
INPUT  
50  
7
DD  
DD  
DD  
OFF  
= 3.0V, -0.6V<V  
<0.6V  
Ohm  
Ohm  
INPUT  
On resistance between input to  
output  
R
ON  
= 3.0V, 1.0V<V  
<1.5V  
10  
INPUT  
Power Supply Characteristics (T = 0°C to +70°C)  
A
(1)  
(1)  
Typ  
Parameter  
Description  
Test Conditions  
Min  
Max  
Units  
I
CC  
Quiescent Power Supply Current  
V
= Max., V = GND or V  
DD  
70  
µA  
DD  
IN  
Dynamic Electrical Characteristics over Operating Range (T = -40º to +85ºC, V = 3.3V ±10%,  
A
DD  
GND=0V)  
(2)  
Parameter  
Description  
Test Conditions  
Typ.  
Units  
f= 1.35 GHz  
f = 100 MHz  
f= 1.35 GHz  
-33dB  
-48dB  
-33dB  
See Fig. 1 for Measurement  
Setup  
X
Crosstalk on High Speed Channels  
TALK  
dB  
See Fig. 2 for Measurement  
Setup,  
O
OFF Isolation on High Speed Channels  
IRR  
f = 100 MHz  
-56dB  
-1.5  
Differential Insertion Loss on High  
Speed Channels  
I
@2.7Gbps (see figure 3)  
dB  
LOSS  
Bandwidth -3dB for Main high speed  
path (Dx )  
BW_Dx  
See figure 3  
See figure 3  
3.25  
1.5  
GHz  
GHz  
BW_AUX/HPD -3dB BW for AUX and HPD signals  
Notes:  
1. For Max. or Min. conditions, use appropriate value specified under Electrical Characteristics for the applicable device type.  
2. Typical values are at V = 3.3V, T = 25°C ambient and maximum loading.  
DD  
A
PS9056A  
07/12/11  
5
11-0103  
PI3VDP612-A  
4-Lane DisplayPort™ Rev 1.1a Compliant Switch  
with Triple Control Logic for Fast Switching  
50  
+
+
BALANCED  
PORT1  
50  
–
–
50  
50  
+
+
BALANCED  
PORT2  
–
–
DUT  
Fig 1. Crosstalk Setup  
50  
50  
+
+
BALANCED  
PORT1  
–
–
+
BALANCED  
PORT2  
–
DUT  
Fig 2. Off-isolation setup  
+
+
BALANCED  
PORT1  
BALANCED  
–
PORT2  
–
DUT  
Fig 3. Differential Insertion Loss  
PS9056A  
07/12/11  
6
11-0103  
PI3VDP612-A  
4-Lane DisplayPort™ Rev 1.1a Compliant Switch  
with Triple Control Logic for Fast Switching  
Fig 4. Xtalk  
PS9056A  
07/12/11  
7
11-0103  
PI3VDP612-A  
4-Lane DisplayPort™ Rev 1.1a Compliant Switch  
with Triple Control Logic for Fast Switching  
Fig 5. Off Isolation  
PS9056A  
07/12/11  
8
11-0103  
PI3VDP612-A  
4-Lane DisplayPort™ Rev 1.1a Compliant Switch  
with Triple Control Logic for Fast Switching  
Fig 6. Insertion Loss  
PS9056A  
07/12/11  
9
11-0103  
PI3VDP612-A  
4-Lane DisplayPort™ Rev 1.1a Compliant Switch  
with Triple Control Logic for Fast Switching  
(OHMS)  
20.0  
RON  
2.00/div  
0.00  
0.00  
VIN (V)  
200.m /div  
3.00  
Fig 7. Ron Curve for High Speed Signal Path Only (Dx )  
PS9056A  
07/12/11  
10  
11-0103  
PI3VDP612-A  
4-Lane DisplayPort™ Rev 1.1a Compliant Switch  
with Triple Control Logic for Fast Switching  
Switching Characteristics (T = -40º to +85ºC, V  
= 3.3V±10%)  
DD  
A
Parameter  
Description  
Min.  
Max.  
Units  
t
t
, t  
PZH PZL  
Line Enable Time  
Line Disable Time  
0.5  
0.5  
15.0  
15.0  
200  
7
ns  
, t  
PLZ  
PHZ  
T
Propagation delay (input pin to output pin)  
Bit-to-bit skew within the same differential pair  
Channel-to-channel skew  
ps  
ps  
ps  
pd  
t
t
b-b  
ch-ch  
50  
Test Circuit for Electrical Characteristics(1-5)  
6.0V  
VDD  
200-ohm  
VIN  
Pulse  
Generator  
VOUT  
D.U.T  
4pF  
CL  
200-ohm  
RT  
Notes:  
1. CL = Load capacitance: includes jig and probe capacitance.  
2. RT = Termination resistance: should be equal to ZOUT of the Pulse Generator  
3. Output 1 is for an output with internal conditions such that the output is low except when disabled by the output control.  
output 2 is for an output with internal conditions such that the output is high except when disabled by the output control.  
4. All input impulses are supplied by generators having the following characteristics: PRR ≤ MHz, ZO = 50Ω, tR ≤ 2.5ns, tF ≤ 2.5ns.  
5. The outputs are measured one at a time with one transition per measurement.  
Switching Waveforms  
V
DD  
SEL  
V
/2  
V
/2  
DD  
DD  
0V  
t
PZL  
t
PLZ  
V
Output 1  
OH  
V
V
DD/2  
DD/2  
VOL + 0.3V  
V
V
OL  
t
t
PHZ  
PZH  
OH  
VOH – 0.3V  
V
Output 2  
OL  
Voltage Waveforms Enable and Disable Times  
Switch Positions  
Test  
Switch  
t
t
, t  
(output on B-side)  
(output on B-side)  
6.0V  
PLZ PZL  
, t  
GND  
Open  
PHZ PZH  
Prop Delay  
PS9056A  
07/12/11  
11  
11-0103  
PI3VDP612-A  
4-Lane DisplayPort™ Rev 1.1a Compliant Switch  
with Triple Control Logic for Fast Switching  
Test Circuit for Dynamic Electrical Characteristics  
Agilent N5230A 300kHz-20GHz PNA-L Network Analyzer  
PI3VDP12412  
HP11667A  
Application Section - Pre-Emphasis Waveforms  
Input Pre-emphasis = 9.5dB; Red waveform is input of PI3VDP612-A & Black is output of PI3VDP612-A  
PS9056A  
07/12/11  
12  
11-0103  
PI3VDP612-A  
4-Lane DisplayPort™ Rev 1.1a Compliant Switch  
with Triple Control Logic for Fast Switching  
Input Pre-emphasis = 6dB; Red waveform is input of PI3VDP612-A and Black is output of PI3VDP612-A  
PS9056A  
07/12/11  
13  
11-0103  
PI3VDP612-A  
4-Lane DisplayPort™ Rev 1.1a Compliant Switch  
with Triple Control Logic for Fast Switching  
Input Pre-emphasis = 3.5dB; Red waveform is input of PI3VDP612-A & Black is output of PI3VDP612-A  
PS9056A  
07/12/11  
14  
11-0103  
PI3VDP612-A  
4-Lane DisplayPort™ Rev 1.1a Compliant Switch  
with Triple Control Logic for Fast Switching  
Packaging Mechanical: 56-Contact TQFN (ZF)  
DATE: 05/15/08  
DESCRIPTION: 56-contact, Thin Fine Pitch Quad Flat No-lead (TQFN)  
PACKAGE CODE: ZF56  
REVISION: C  
DOCUMENT CONTROL #: PD-2024  
08-0208  
Note:  
• For latest package info, please check: http://www.pericom.com/products/packaging/mechanicals.php  
PS9056A  
07/12/11  
15  
11-0103  
PI3VDP612-A  
4-Lane DisplayPort™ Rev 1.1a Compliant Switch  
with Triple Control Logic for Fast Switching  
Packaging Mechanical: 42-Pin TQFN (ZH)  
DATE: 02/17/09  
Notes:  
1. All dimensions are in millimeters, angles in degrees.  
2. Coplanarity applies to the exposed thermal pad as well as the terminals.  
3. Refer JEDEC MO-220  
4. Recommended Land Pattern is for reference only.  
5. Thermal Pad Soldering Area  
DESCRIPTION: 42-contact Thin Fine Pitch Quad Flat No-Lead (TQFN)  
PACKAGE CODE: ZH (ZH42)  
REVISION: C  
DOCUMENT CONTROL #: PD-2035  
09-0116  
Note:  
• For latest package info, please check: http://www.pericom.com/products/packaging/mechanicals.php  
Ordering Information  
Ordering Code  
Package Code  
Package Description  
PI3VDP612-AZFE  
PI3VDP612-AZHE  
ZF  
Pb-free & Green, 56-contact TQFN  
Pb-free & Green, 42-contact TQFN  
ZH  
Notes:  
•
•
•
Thermal characteristics can be found on the company web site at www.pericom.com/packaging/  
"E" denotes Pb-free and Green  
Adding an "X" at the end of the ordering code denotes tape and reel packaging  
Pericom Semiconductor Corporation • 1-800-435-2336 • www.pericom.com  
PS9056A  
07/12/11  
16  
11-0103  
DisplayPort is a trademark of VESA www.vesa.org  

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