PI4IOE5V9570 [PERICOM]

4-bit general purpose outputs;
PI4IOE5V9570
型号: PI4IOE5V9570
厂家: PERICOM SEMICONDUCTOR CORPORATION    PERICOM SEMICONDUCTOR CORPORATION
描述:

4-bit general purpose outputs

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中文:  中文翻译
下载:  下载PDF数据表文档文件
PI4IOE5V9570  
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4-bit general purpose outputs for 1MHz I2C bus  
Features  
Description  
Operation power supply voltage from 2.3V to 5.5V  
4-bit I2C-bus GPO  
The PI4IOE5V9570 is a CMOS device that  
provides 4bits of General Purpose parallel Output  
(GPO) expansion in low voltage processor and  
handheld battery powered mobile applications. It  
operates at 1 MHz I2C-bus speeds while maintaining  
backward compatibility to Fast-mode (400 kHz) and  
Standard-mode (100 kHz).  
1 MHz I2C-bus interface with 30 mA SDA sink  
capability for 4000pF  
Latched outputs with 25mA capability for directly  
driving LEDs  
Software Reset; Power-on reset  
Low standby current  
The PI4IOE5V9570 is a streamlined GPO that  
consists of 4-bit push-pull outputs that offer low  
current consumption, small packaging options The  
PI4IOE5V9570 output expander provides a simple  
solution when additional outputs are needed while  
keeping interconnections and floor space to a  
minimum, for example, in battery powered mobile  
applications where PCBs are crowded for interfacing  
to sensors, push buttons, etc.  
ESD protection (4KV HBM and 1KV CDM)  
Offered in two different packages:UQFN 1.6x1.6-  
8,MSOP-8  
The PI4IOE5V9570 contains an internal Power-On  
Reset (POR) and a Software Reset feature that  
initializes the device to its default state.  
Pin Configuration  
Figure1 : MSOP-8  
Figure2 : UQFN 1.6x1.6-8  
2015-07-0044  
PT0559  
08/05/15  
1
PI4IOE5V9570  
4-bit general purpose outputs  
for 1MHz I2C bus  
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Pin Description  
Table 1. Pin configuration  
* I = Input; O = Output; P = Power; G = Ground  
TDFN 1.6*1.6  
1
TSSOP  
1
Name  
P0  
Type  
I/O  
Description  
Input/ output 0  
2
3
4
5
6
7
8
2
3
4
5
6
7
8
P1  
P2  
I/O  
I/O  
G
Input/ output 1  
Input/ output 2  
Supply Ground  
Input/ output 3  
Serial clock line  
Serial data line  
Power supply  
GND  
P3  
I/O  
I
SCL  
SDA  
VCC  
I/O  
P
2015-07-0044  
PT0559  
08/05/15  
2
PI4IOE5V9570  
4-bit general purpose outputs  
for 1MHz I2C bus  
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Maximum Ratings  
Note:  
Powersupply......................................................................................................-0.5Vto+6.0V  
Voltageonan I/Opin..........................................................................GND-0.5Vto +6.0V  
Inputcurrent.....................................................................................................................±20mA  
Outputcurrenton anI/Opin ......................................................................................±50mA  
Supplycurrent....................................................................................................................85mA  
Groundsupplycurrent...................................................................................................100mA  
Totalpowerdissipation................................................................................................200mW  
Operationtemperature...............................................................................................-40~85  
Stresses greater than those listed under MAXIMUM  
RATINGS may cause permanent damage to the  
device. This is a stress rating only and functional  
operation of the device at these or any other  
conditions above those indicated in the operational  
sections of this specification is not implied.  
Exposure to absolute maximum rating conditions  
for extended periods may affect reliability.  
Storagetemperature ................................................................................................-65~150℃  
Maximum Junctiontemperature,Tj(max) ................................................................125℃  
Static characteristics  
VCC =2.3 V to 5.5V; GND = 0 V; Tamb= -40 °C to +85 °C; unless otherwise specified.  
Table 2: Static characteristics  
Conditions  
Symbol  
Parameter  
Min.  
Typ.  
Max.  
Unit  
Power supply  
VCC  
IDD  
Supply voltage  
Supply current  
2.3  
-
-
5.5  
500  
10  
V
μA  
uA  
V
Operating mode; no load;  
200  
4.5  
VI = VCC or GND; fSCL = 1 MHz;  
Standby mode; VCC = 5.5 V; no load;  
VI = VCC; fSCL= 0 kHz; I/O = inputs  
Standby mode; no load;  
Istb  
Standby current  
-
[1]  
VPOR  
-
1.16  
1.41  
Power-on reset voltage  
VI = VCC or GND; fSCL = 0 kHz  
Input SCL, input/output SDA  
Low level input voltage  
V
IL  
-0.5  
0.7VCC  
20  
0.3VCC  
V
V
V
IH  
High level input voltage  
5.5  
-
VOL =0.4V;VCC =2.3V  
VOL = 0.4 V; VCC = 3.0 V  
VOL = 0.4 V; VCC = 4.5 V  
VI=VCC=GND  
35  
44  
57  
-
mA  
IOL  
Low level output current  
25  
30  
IL  
Leakage current  
Input capacitance  
-1  
1
μA  
Ci  
VI =GND  
-
5
10  
pF  
2015-07-0044  
PT0559  
08/05/15  
3
PI4IOE5V9570  
4-bit general purpose outputs  
for 1MHz I2C bus  
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Conditions  
Symbol  
I/Os  
VIL  
VIH  
Parameter  
Min.  
Typ.  
Max.  
Unit  
LOW-level input voltage  
HIGH-level input voltage  
-0.5  
1.8  
12  
0.81  
5.5  
V
V
VCC = 2.3 V; VOL = 0.5 V[2]  
VCC =3.0V; VOL = 0.5 V[2]  
VCC =4.5V; VOL = 0.5 V[2]  
26  
33  
40  
mA  
mA  
mA  
IOL  
Low level output current  
17  
25  
total LOW-level output  
current  
IOL(tot)  
IOH  
VOL=0.5V;VCC=4.5V  
VOH = GND  
200  
mA  
uA  
HIGH-level output current  
-30  
-359  
-1.0  
-480  
transient boosted pull-up  
current  
Itrt(pu)  
VOH= GND  
-0.5  
mA  
Ci  
Input capacitance  
Output capacitance  
-
-
2.1  
2.1  
10  
10  
pF  
pF  
Co  
Note:  
[1]: VCC must be lowered to 0.2 V for at least 5 us in order to reset part.  
[2]: Each I/O must be externally limited to a maximum of 25 mA and the total package limited to 100 mA due to internal busing  
limits.  
[3]: The value is not tested, but verified on sampling basis.  
2015-07-0044  
PT0559  
08/05/15  
4
PI4IOE5V9570  
4-bit general purpose outputs  
for 1MHz I2C bus  
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Dymaic Characteristics  
Table 3: Dynamic characteristics  
Standard mode  
I2C  
1 MHz  
I2C-bus  
Fast mode I2C  
Unit  
Test  
Conditions  
Symbol  
Parameter  
Min  
0
Max  
Min  
0
Max  
Min  
Max  
fSCL  
tBUF  
SCL clock frequency  
100  
400  
0
1000 kHz  
bus free time between a STOP  
and START condition  
hold time (repeated) START  
condition  
set-up time for a repeated  
START condition  
4.7  
4.0  
-
-
1.3  
0.6  
-
-
0.5  
μs  
μs  
tHD;STA  
tSU;STA  
tSU;STO  
0.26  
0.26  
0.26  
4.7  
4.0  
-
-
-
0.6  
0.6  
-
-
-
μs  
μs  
set-up time for STOP  
condition  
[1]  
tVD;ACK  
data valid acknowledge time  
data hold time  
3.45  
0.9  
0
0.45  
0.45  
μs  
ns  
us  
ns  
μs  
μs  
ns  
ns  
tHD;DAT  
0
[2]  
tVD;DAT  
data valid time  
3.45  
-
100  
1.3  
0.6  
-
0.9  
-
tSU;DAT  
tLOW  
tHIGH  
tf  
data set-up time  
250  
4.7  
4.0  
-
-
-
50  
0.5  
0.26  
-
LOW period of the SCL clock  
HIGH period of the SCL clock  
-
-
-
fall time of both SDA and SCL  
signals  
rise time of both SDA and  
SCL signals  
300  
1000  
300  
300  
120  
120  
tr  
-
-
-
pulse width of spikes that must  
be  
[3]  
tSP  
-
50  
-
50  
-
50  
ns  
suppressed by the input filter  
Port timing  
tv(Q)  
Data output valid time  
200  
200  
200  
ns  
Note:  
[1] tVD;ACK = time for Acknowledgement signal from SCL LOW to SDA (out) LOW.  
[2] tVD;DAT = minimum time for SDA data out to be valid following SCL LOW.  
[3] Input filters on the SDA and SCL inputs suppress noise spikes less than 50 ns.  
2015-07-0044  
PT0559  
08/05/15  
5
PI4IOE5V9570  
4-bit general purpose outputs  
for 1MHz I2C bus  
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PI4IOE5V9570 Block Diagram  
Fig 3: Block diagram of PI4IOE5V9570  
Details Description  
a. Device Address  
b7(MSB) b6  
b5  
0
b4  
0
b3  
1
b2  
0
b1  
b0  
Address Byte  
0
1
0
R/W  
b. Software Reset Call  
General Call address: allows resetting the device through the I2C-bus upon reception of the right I2C-bus sequence.  
b7(MSB) b6  
b5  
0
b4  
0
b3  
0
b2  
0
b1  
0
b0  
0
General Call  
Address  
0
0
c. Software Reset  
The Software Reset Call allows all the devices in the I2C-bus to be reset to the power-up state value through a specific  
formatted I2C-bus command. To be performed correctly, it implies that the I2C-bus is functional and that there is no device  
hanging the bus.  
The Software Reset sequence is defined as following:  
1. A START command is sent by the I2C-bus master.  
2. The reserved General Call I2C-bus address ‘0000 000’ with the R/W bit set to 0 (write) is sent by the I2C-bus master.  
3. The device acknowledges after seeing the General Call address ‘0000 0000’ (00h) only. If the R/W bit is set to 1 (read), no  
acknowledge is returned to the I2C-bus master.  
4. Once the General Call address has been sent and acknowledged, the master sends 1 byte. The value of the byte must be  
equal to 06h.  
a. The device acknowledges this value only. If the byte is not equal to 06h, the device does not acknowledge it.  
2015-07-0044  
PT0559  
08/05/15  
6
PI4IOE5V9570  
4-bit general purpose outputs  
for 1MHz I2C bus  
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b. If more than 1 byte of data is sent, the device does not acknowledge any more.  
5. Once the right byte has been sent and correctly acknowledged, the master sends a STOP command to end the Software  
Reset sequence: the device then resets to the default value (power-up value) and is ready to be addressed again within the specified  
bus free time. If the master sends a Repeated START instead, no reset is performed.  
The I2C-bus master must interpret a non-acknowledge from the device (at any time) as a Software Reset Abort’. The device  
does not initiate a reset of its registers.  
The unique sequence that initiates a Software Reset is described in Figure 4.  
Figure 4: Software reset  
d. Quasi-bidirectional I/O architecture  
The device ports are entirely independent and are output ports. The state of the ports at the pin is transferred from the ports to  
the microcontroller in the Read mode (see Figure 7). Output data is transmitted to the ports in the Write mode (see Figure 6).At  
power-on all ports are HIGH. The state of the Output Port register determines if either Q1 or Q2 is on, driving the line either  
HIGH or LOW. A bit set to 1 in the data byte drives the line HIGH at the corresponding port. A bit set to 0 in the data byte drives  
the line LOW at the corresponding port.  
If an external voltage is applied to an output, care should be exercised because of the low-impedance path that exists between  
the pin and either VCC or GND.  
Figure 5:I/O architecture  
2015-07-0044  
PT0559  
08/05/15  
7
PI4IOE5V9570  
4-bit general purpose outputs  
for 1MHz I2C bus  
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e. Bus Transaction  
Writing to the port (output mode)  
To write, the master (microcontroller) first addresses the slave device. By setting the last bit of the byte containing the slave  
address to logic 0, the Write mode is entered. The device acknowledges and the master sends the data byte for P7 to P0 and is  
acknowledged by the device. Writes to P7 to P4 are ignored in the PI4IOE5V9570 as only P3 through P0 are available. The 4-bit  
data is presented on the port lines after it has been acknowledged by the device. The number of data bytes that can be sent  
successively is not limited. The previous data is overwritten every time a data byte has been sent.  
Figure 6: Write to configuration registers  
Reading from a port (input mode)  
All ports are outputs and cannot be used as inputs. When reading the device, the data returned is the port state at the pin. To read,  
the master (microcontroller) first addresses the slave device by setting the last bit of the byte containing the slave address to logic  
1. The data byte that follows on the SDA is the value of the ports pins. There is no limit to the number of bytes read, and the state  
of the output port pins is updated at each acknowledge cycle. Logic 1 means that the port is HIGH. Logic 0 means that the port is  
LOW. When the PI4IOE5V9570 is read, P7 through P4 return logic ‘1’.  
Figure 7: Read from registers  
Note: Transfer can be stopped at any time by a STOP condition.  
f. Power-on reset  
When power is applied to VCC, an internal Power-On Reset (POR) holds the device in a reset condition until VCC has reached  
VPOR. At that point, the reset condition is released and the device registers and I2C-bus/SMBus state machine initialize to their  
default states.  
2015-07-0044  
PT0559  
08/05/15  
8
PI4IOE5V9570  
4-bit general purpose outputs  
for 1MHz I2C bus  
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I/O expander applications  
Bellow figure shows a 4-bit output expander application. The desired HIGH or LOW logic levels are controlled by the master with  
speeds of up to 1 MHz .This allows the host processor to control various functions quickly and with very low overhead. The port  
read function of the device enables the host processor to poll the status of the output port pins. This is useful for system recovery  
operations or debugging.  
Figure 8: Application  
2015-07-0044  
PT0559  
08/05/15  
9
PI4IOE5V9570  
4-bit general purpose outputs  
for 1MHz I2C bus  
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Mechanical Information  
MSOP-8(U)  
2015-07-0044  
PT0559  
08/05/15  
10  
PI4IOE5V9570  
4-bit general purpose outputs  
for 1MHz I2C bus  
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UQFN-8(XT)  
Ordering Information  
Part No.  
Package Code  
Package  
8-Pin, Mini Small Outline Package(MSOP)  
PI4IOEV9570UE  
U
8-Pin, Mini Small Outline Package(MSOP),  
Tape & Reel  
PI4IOE5V9570UE  
U
PI4IOE5V9570XTEX  
XT  
8-pin UQFN 1.6x1.6, Tape & Reel  
Note:  
E = Pb-free and Green  
Adding X Suffix= Tape/Reel  
Pericom Semiconductor Corporation 1-800-435-2336 www.pericom.com  
Pericom reserves the right to make changes to its products or specifications at any time, without notice, in order to improve design or performance and to supply  
the best possible product. Pericom does not assume any responsibility for use of any circuitry described other than the circuitry embodied in Pericom product. The  
company makes no representations that circuitry described herein is free from patent infringement or other rights, of Pericom.  
2015-07-0044  
PT0559  
08/05/15  
11  

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