PI6C184HEX [PERICOM]
Low Skew Clock Driver, 6C Series, 13 True Output(s), 0 Inverted Output(s), CMOS, PDSO28, 5.30 MM, 0.65 MM PITCH, SSOP-28;
| 型号： | PI6C184HEX |
| 厂家： | 
PERICOM SEMICONDUCTOR CORPORATION |
| 描述： | Low Skew Clock Driver, 6C Series, 13 True Output(s), 0 Inverted Output(s), CMOS, PDSO28, 5.30 MM, 0.65 MM PITCH, SSOP-28 驱动 光电二极管 逻辑集成电路 |
| 文件： | 总7页 (文件大小：1782K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
PI6C184
Precision 1-13 Clock Buffer
Description
Features
The PI6C184 is a high-speed low-noise 1-13 non-inverting
buffer designed for SDRAM clock buffer applications.
• High-speed, low-noise, non-inverting, 1-13 buffer
• Supports up to four SDRAM DIMMs
• Low skew (< 250ps) between any two output clocks
ThisbufferisintendedtobeusedwiththePI6C104clockgenerator
for Intel Architecture for both desktop and mobile systems.
2
2
• I CSerialConfigurationinterface
At power-up, all SDRAM outputs are enabled and active. TChe I
Serial control may be used to individually activate/deactivate any
of the 13 output drivers.
• Multiple V , V pins for noise reduction
DD SS
• 3.3V power supply voltage
• Separate Hi-Z pin for testing
Note:
2
Purchase of IC components from Pericom conveys a license to
2
use them in an CI system as defined by Philips®.
• Packaging(Pb-free&Greenavailable):
-28-pinSSOP(H)
BlockDiagram
PinConfiguration
SDRAM0
SDRAM1
28
27
26
25
24
23
22
21
20
19
18
17
16
15
V
1
V
S
DD
DD
S
DRAM
0
DRAM11
2
S
DRAM
1
3
S
V
V
S
S
V
V
S
S
V
V
S
DRAM10
BUF_IN
V
V
4
SS
SS
DD
SDRAM2
SDRAM3
5
DD
S
DRAM
DRAM
2
3
6
DRAM
DRAM
9
8
S
7
V
8
SS
SS
BUF_IN
9
DD
S
DRAM
DRAM
DRAM12
4
10
11
12
13
14
DRAM
7
6
SDRAM12
S
5
DRAM
S
SS
V
DD
SS
SDATA
SCLK
2
I C
S
DATA
CLK
I/O
08-0298
PS8320E
11/13/08
1
PI6C184
Precision 1-13 Clock Buffer
PinDescription
Quantit-
y
Pin
Symbol
Type
Description
2,3,6,7,10,11,18,19
SDRAM [0.7]
SDRAM [10.12]
SDRAM [8.9]
BUF_IN
0
0
0
1
8
3
2
1
SDRAM Byte 0 clock output
26,27,12
22,23
9
SDRAM Byte 1 clock output
SDRAM Byte 2 clock output
Input for 1-13-buffer
2
Data pin for I C circuitry. Has a
100k Internal pull-up resistor
14
15
SDATA
SCLK
I/O
I/O
1
1
2
Clock pin for I C circuitry. Has a 100k Internal pull-up
resistor
1,5,13,20,24,28
4,8,16,17,21,25
V
Power
6
6
3.3V power supply for SDRAM buffer
DD
V
Ground
Ground for SDRAM Buffers
SS
2
I C Address Assignment
SerialConfigurationMap
Byte0:SDRAMActive/InactiveRegister
(1 = enable, 0 = disable)
A6
1
A5
1
A4
0
A3
1
A2
0
A1
0
A0
R/W
0
1
Bit
Pin #
19
18
11
10
7
Description
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
SDRAM7 (Active/Inactive)
SDRAM6 (Active/Inactive)
SDRAM5 (Active/Inactive)
SDRAM4 (Active/Inactive)
SDRAM3 (Active/Inactive)
SDRAM2 (Active/Inactive)
SDRAM1 (Active/Inactive)
SDRAM0 (Active/Inactive)
6
3
2
Note:
Inactive means outputs are held LOW and are
disabled from switching
08-0298
PS8320E
11/13/08
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PI6C184
Precision 1-13 Clock Buffer
2
2-WireI CControl
2
a stop condition. The first byte after a start condition is always a
7-bit address byte followed by a read/write bit. (HIGH = read from
addresseddevice, LOW=writetoaddresseddevice). Ifthedevice’s
own address is detected, PI6C184 generates an acknowledge by
pulling SDATA line LOW during ninth clock pulse, then accepts
The I C interface permits individual enable/disable of each clock
output and test mode enable.
ThePI6C184 isaslavereceiverdevice. Itcannotbereadback. Sub
addressing is not supported. All preceding bytes must be sent in
order to change one of the control bytes.
the following data bytes until another start or stop condition is
detected.
Every bite put on the SDATA line must be 8-bits long (MSB first),
followed by an acknowledge bit generated by the receiving device.
DuringnormaldatatransfersSDATAchangesonlywhen SCLK is
LOW. Exceptions: A HIGH-to-LOW transition on SDATA while
SCLK is HIGH indicates a “start” condition. A LOW-to-HIGH
transition on SDATA while SCLK is HIGH is a “stop” condition
and indicates the end of a data transfer cycle.
Following acknowledgement of the address byte (D2), two more
bytes must be sent:
1. “Command Code” byte, and
2. “Byte Count” byte.
Although the data bits on these two bytes are “don’t care,” they
must be sent and acknowledged.
Each data transfer is initiated with a start condition and ended with
Byte2: Optional Register for Possible Future
Requirements (1 = enable, 0 = disable)
Byte1: SDRAM Active/Inactive Register
(1 = enable, 0 = disable)
Bit
Pin #
Description
NC (Initialize to 0)
Bit
Pin #
Description
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
23
22
-
SDRAM9 (Active/Inactive)
SDRAM8 (Active/Inactive)
(Reserved)
NC (Initialize to 0)
NC (Initialize to 0)
-
(Reserved)
NC (Initialize to 0)
-
(Reserved)
NC (Initialize to 0)
-
(Reserved)
12
27
26
SDRAM12 (Active/Inactive)
SDRAM11(Active/Inactive)
SDRAM10 (Active/Inactive)
-
(Reserved)
-
(Reserved)
MaximumRatings
(Above which the useful life may be impaired. For user guidelines, not tested.)
Note:
Stresses greater than those listed under MAXIMUM RAT-
INGS may cause permanent damage to the device. This is a
stress rating only and functional operation of the device at
these or any other conditions above those indicated in the
operational sections of this specification is not implied.
Exposuretoabsolutemaximumratingconditionsforextended
periods may affect reliability.
Storage Temperatur..e..........................................–..6.5°Cto+150°C
Ambient Temperature with Power Appli.e..d.............. –0°Cto+70°C
3.3V Supply Voltage toGround Potentia.l.................–0.5Vto+4.6V
DC InputVoltage...................................................–..0..5Vto+4.6V
SupplyCurrent (V =+3.465V,C
=Max.)
DD
LOAD
Symbol
Parameter
Test Condition
BUF_IN = 0 MHz
M in.
Typ.
M ax.
3
Units
mA
I
I
I
Supply Current
Supply Current
Supply Current
DD
DD
DD
BUF_IN = 66.66 MHz
BUF_IN = 100.0 MHz
230
360
08-0298
PS8320E
11/13/08
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PI6C184
Precision 1-13 Clock Buffer
DCOperatingSpecifications(V =+3.3V±5%, T =0°C-70°C)
DD
A
Symbol
Parameter
Test Condition
M in.
2.0
M ax.
Units
Input Voltage
V
IH
V
IL
Input high voltage
Input low voltage
Input leakage current
V
V
+0.3
DD
DD
V
V
–0.3
0.8
SS
I
0 < V < V
DD
–5
+5
mA
IL
IN
V
[0-9] = 3.3V ±5%
DD
V
V
Output high voltage
Output low voltage
Output pin capacitance
Input pin capacitance
Pin Inductance
I
= -1mA
OH
2.4
OH
OL
V
I
= 1mA
0.4
6
OL
C
OUT
pF
C
5
IN
L
7
nH
°C
PIN
T
Ambient Temperature
No Airflow
0
70
A
SDRAMClockBufferOperatingSpecification
Symbol
Parameter
Pull-up current
Test Conditions
= 2.0V
M in.
Typ.
M ax.
–46
Units
I
I
I
I
V
V
V
V
–54
OHMIN
OUT
OUT
OUT
OUT
Pull-up current
= 3.135V
= 1.0V
OHMAX
OLMIN
OLMAX
mA
Pull-down current
54
Pull-down current
= 0.4V
53
4
t
SDRAM
Output rise edge rate SDRAM only
Output fall edge rate SDRAM only
3.3V ±5% @ 04V-2.4V
3.3V ±5% @ 2.4V-0.4V
1.5
1.5
RH
V/ns
t
TH
SDRAM
4
AC Timing
Symbol
Parameter
66MHz
100MHz
Units
Min.
15.0
5.6
5.3
1.5
1.5
1.0
1.0
45
Max.
15.5
Min.
Max.
10.5
T
T
T
T
T
SDRAMCLKperiod
10.0
3.3
3.1
1.5
1.5
1.0
1.0
45
ns
ns
DSKP
SDKH
SDKL
SDRAMCLKhightime
SDRAMCLKlowtime
ns
SDRAMCLKrisetime
SDRAMCLKfalltime
4.0
4.0
5.5
5.5
55
4.0
4.0
5.0
5.0
55
V/ns
SDRISE
SDFALL
PLH
V/ns
t
t
SDRAM Buffer LH prop delay
SDRAM Buffer HL prop delay
ns
ns
%
PHL
DutyCycle Measured at 1.5V
tSDSKW SDRAM Output to Output Skew
250
250
ps
08-0298
PS8320E
11/13/08
4
PI6C184
Precision 1-13 Clock Buffer
Test
Point
Output
Buffer
Test Load
tSDKP
tSDKH
3.3V
Clocking
Interface
(TTL)
2.4
1.5
0.4
tSDKL
tSDRISE
tSDFALL
Input
Waveform
1.5V
1.5V
tplh
tphl
Output
Waveform
1.5V
1.5V
Figure1. ClockWaveforms
MinimumandMaximumExpectedCapacitiveLoads
Clock
M in. Load
20
M ax. Load
30
Units
pF
Notes
SDRAM DIMM Specification
SDRAM
Notes:
1. Maximum rise/fall times are guaranteed at maximum specified load.
2. Minimum rise/fall times are guaranteed at minimum specified load.
3. Rise/fall times are specified with pure capacitive load as shown.
Testing is done with an additional 5Ω00resistor in parallel.
Design Guidelines to Reduce EMI
1. Place series resistors and CI capacitors as close as possible to the respective clock pins. Typical value
for CI is 10pF. Series resistor value can be increased to reduce EMI provided that the rise and fall time
are still within the specified values.
2. Minimize the number of “vias” of the clock traces.
3. Route clock traces over a continuous ground plane or over a continuous power plane. Avoid routing
clock traces from plane to plane (refer to rule #2).
4. Position clock signals away from signals that go to any cables or any external connectors.
08-0298
PS8320E
11/13/08
5
PI6C184
Precision 1-13 Clock Buffer
PCBLayoutSuggestion
C1
C4
C5
C6
28
VDD
VDD
1
Ferrite Bead
VCC
2
27
26
25
24
23
3
C7
VSS
C2
VSS
VDD
4
VDD
5
22µF
6
7
22
21
20
19
18
17
VSS
VSS
VDD
8
9
10
11
12
13
14
Via to GND Plane
Via to VDD Plane
VSS
VSS
C3
VDD
16
15
Void in Power Plane
Note:
This is only a suggested layout. There may be alternate solutions
depending on actual PCB design and layout.
As a general rule, C1-C7 should be placed as close as possible to their
Recommended capacitor values:
C1-C7 ................. 0.µ1F, ceramic
C8 ..................... 2µ2F
respective V .
DD
PI6C184
SDRAM
100/66 MHz
Clock from
Chipset
22Ω
SDRAM
DIMM
Spec.
13
C
L
Figure 2. Design Guidelines
08-0298
PS8320E
11/13/08
6
PI6C184
Precision 1-13 Clock Buꢀer
PackagingMechanical:28-pinSSOP(H)
OrderingInformation
OrderingCode
PI6C184HE
PackageCode
PackageType
Pb-free&Green,28-pinSSOP
H
Notes:
1. Thermal characteristics can be found on the company web site at www.pericom.com/packaging/
PericomSemiconductorCorporation • 1-800-435-2336 • www.pericom.com
08-0298
PS8320E
11/13/08
7
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