PI6C2308-6WX [PERICOM]
PLL Based Clock Driver, 6C Series, 8 True Output(s), 0 Inverted Output(s), PDSO16, 0.150 INCH, SOIC-16;
| 型号： | PI6C2308-6WX |
| 厂家： | 
PERICOM SEMICONDUCTOR CORPORATION |
| 描述： | PLL Based Clock Driver, 6C Series, 8 True Output(s), 0 Inverted Output(s), PDSO16, 0.150 INCH, SOIC-16 驱动 光电二极管 逻辑集成电路 |
| 文件： | 总9页 (文件大小：442K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
PI6C2308
Zero-Delay Clock Buffer
ProductFeatures
FunctionalDescription
• Maximumratedfrequency:133MHz
• Lowcycle-to-cyclejitter
The PI6C2308 is a PLL-based, zero-delay buffer, with the ability
to distribute eight outputs of up to 133 MHz at 3.3 V. Two banks of
four outputs exist, and, depending on product option ordered, can
supply either reference frequency, prescaled half frequency, or
multiplied2xor4xinputclockfrequencies. ThePI6C2308familyhas
a power-sparing feature: when input SEL2 is 0, the component will
3-state one or both banks of outputs depending on the state of input
SEL1. A PLL bypass test mode also exists. This product line is
available in high-drive and industrial environment versions.
• Input to output delay, less than 200ps
• External feedback pin allows outputs to be synchronized
to the clock input
• 5V tolerant input*
• Operatesat3.3VVDD
• Test mode allows bypass of the PLL for system testing
purposes (e.g., IBIS measurements)
An external feedback pin is used to synchronize the outputs to the
input; the relationship between loading of this signal and the other
outputs determines the input-output delay.
• Clock frequency multipliers ½x to 4x dependent on option
• Space-saving Packages:
16-pin,150-milSOIC (W)
16-pin173-milTSSOP (L)
The PI6C2308 is characterized for both commercial and industrial
operation.
* FB_IN and CLKIN must reference the same voltage thresh-
olds for the PLL to deliver zero delay skewing
Notice: This device is subject to import restriction. Please refer
to the Import Restriction Notice under the Ordering Information
section.
BlockDiagram
PinConfigurationPI6C2308
FB_IN
CLKIN
÷2
PLL
OUTA1
OUTA2
OUTA3
OUTA4
MUX
CLKIN
OUTA1
OUTA2
16
15 OUTA4
1
2
3
4
5
6
7
8
FB_IN
Option (-3, -4)
14
13
12
11
10
9
OUTA3
16-Pin
W,L
SEL1
SEL2
Decode
Logic
V
V
GND
DD
DD
GND
OUTB1
OUTB2
SEL2
÷2
OUTB4
OUTB3
SEL1
OUTB1
OUTB2
OUTB3
OUTB4
Option (-2, -3)
PI6C2308 (-1, -1H, -2, -3, -4)
FB_IN
PLL
OUTA1
OUTA2
OUTA3
OUTA4
MUX
CLKIN
SEL2
SEL1
Decode
Logic
÷2
MUX
PI6C2308-6
OUTB1
OUTB2
OUTB3
OUTB4
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PI6C2308
Zero Delay Clock Buffer
Input Select Decoding for PI6C2308 (-1, -1H,-4)
SEL2
SEL1
OUTA [1-4]
3-State
PLL
OUTB [1-4]
3-State
3-State
CLKIN
PLL
Output Source
PLL
OFF
ON
0
0
1
1
0
1
0
1
PLL
PLL
CLKIN
PLL
CLKIN
PLL
OFF
ON
Input Select Decoding for PI6C2308 (-2,-3)
SEL2
SEL1
OUTA [1-4]
3-State
PLL
OUTB [1-4]
3-State
Output Source
PLL
PLL
OFF
ON
0
0
1
1
0
1
0
1
3-State
PLL
CLKIN
PLL
CLKIN/2
PLL
CLKIN
PLL
OFF
ON
Input Select Decoding for PI6C2308-6
SEL2
SEL1
OUTA [1-4]
OUTB [1-4]
3-State
Output Source
PLL
PLL
OFF
OFF
ON
0
0
1
1
0
1
0
1
3-State
CLKIN
PLL
CLKIN/2
PLL
CLKIN
PLL
PLL
PLL/2
PLL
ON
PI6C2308Configurations
Device
Feedback From
OUTA [1-4] Frequency
CLKIN
OUTB [1-4] Frequency
CLKIN
PI6C2308-1
OUTA or OUTB
OUTA or OUTB
OUTA
PI6C2308-1H
PI6C2308-2
CLKIN
CLKIN
CLKIN
CLKIN/2
PI6C2308-2
OUTB
2X CLKIN
2X CLKIN
4X CLKIN
2X CLKIN
CLKIN
CLKIN
PI6C2308-3
OUTA
CLKIN or CLKIN(1)
PI6C2308-3
OUTB
2X CLKIN
PI6C2308-4
OUTA or OUTB
OUTA
2XCLKIN
PI6C2308-6
CLKIN or CLKIN/2
CLKIN
PI6C2308-6
OUTB
CLKIN or 2X CLKIN
Note:
1. Output phase is indeterminant (0° or 180° from CLKIN)
PS8384D
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PI6C2308
Zero Delay Clock Buffer
PinDescription
Pin
Signal
Description
1
CLKIN
Input clock reference frequency (weak pull-down)
Clock output, Bank A (weak pull-down)
3.3V supply
2, 3, 14, 15
OUTA[1-4]
VDD
4, 13
5, 12
GND
Ground
6, 7, 10 ,11
OUTB[1-4]
SEL2
Clock output, Bank B (weak pull-down)
Select input, bit 2 (weak pull-up)
Select input, bit 1 (weak pull-up)
PLL feedback input
8
9
SEL1
16
FB_IN
ZeroDelayandSkewControl
CLKINInputtoOutputBankDelayvs.DifferenceinLoadingbetweenFB_INpinandOUTA/OUTBpins
800
600
400
200
0
0
5
10
15
20
25
-25
-20
-15
-10
-5
-200
-400
PI6C2308-1H
-600
-800
PI6C2308-1,2,3,4,6
-900
-1000
Output Load Difference: FB_IN Load - OUTA/OUTB Load (pF)
The relationship between loading of the FB_IN signal and other outputs determines the input-output delay. Zero delay is achieved when
all outputs, including feedback, are loaded equally.
MaximumRatings
Supply Voltage to Ground Potential ............................................................................................................................. 0.5Vto+7.0V
DCInputVoltage(ExceptCLKIN) ........................................................................................................................ 0.5VtoV +0.5V
DD
DCInputVoltageCLKIN ......................................................................................................................................................0.5to7V
StorageTemperature................................................................................................................................................... 65ºCto+150ºC
MaximumSolderingTemperature(10seconds)........................................................................................................................... 260ºC
Junction Temperature .................................................................................................................................................................. 150ºC
StaticDischargeVoltage(perMIL-STD-883,Method3015) .................................................................................................... >2000V
PS8384D
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PI6C2308
Zero Delay Clock Buffer
OperatingConditions(VCC =3.3V±0.3V)
Parameter
Description
Min.
3.0
0
Max.
3.6
70
Units
VDD
Supply Voltage
V
Commerical Operating Temperature
Industrial Operating Temperature
Load Capacitance, below 100 MHz
Load Capacitance, from 100 MHz to 133 MHz
Input Capacitance
TA
ºC
pF
40
85
30
CL
15
CIN
7
DCElectricalCharacteristicsforIndustrialTemperatureDevices
Parameter
VIL
Description
Input LOW Voltage
Input HIGH Voltage
Input LOW Current
Input HIGH Current
Output LOW Voltage
Output HIGH Voltage
Test Conditions
Min.
Max.
Units
0.8
V
VIH
IIL
2.0
VIN = 0V
50.0
100.0
0.4
A
IIH
VIN = VDD
VOL
VOH
IOL = 8mA (1, 2, 3,4, 6); IOL = 12mA (1H)
IOH = 8mA (1, 2, 3,4, 6); IOH = 12mA (1H)
V
2.4
IDD (PD mode) Pwr Dwn Supply Current SEL1 = 0 (1, 2, 3, 4, 1H); SEL2 = 0 (6)
25.0
54.0
A
IDD
Supply Current
Unloaded outputs 100 MHz,
Select inputs at VDD or GND
70.0 (1H)
39.0
mA
Unloaded outputs 66 MHz, CLKIN, except (1H)
Unloaded outputs 33MHz, CLKIN, except (1H)
20.0
PS8384D
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PI6C2308
Zero Delay Clock Buffer
ACElectricalCharacteristicsforIndustialTemperatureDevices
Parameters
Name
Test Conditions
Min. Typ. Max. Units
30pF load
100
FO
Output Frequency
20pF load, (1H)
10.0
MHz
133
60.0
55.0
15pF load, (1, 2, 3, 4, 6)
tDC
Duty Cycle(1)
(1, 2, 3, 4, 6)
Measured at VDD/2, FOUT <66.67MHz 30pF load
Measured at VDD/2, FOUT <133MHz 15pF load
Measured at VDD/2, FOUT <45MHz 15pF load
Measured at VDD/2, FOUT <66.67MHz 30pF load
Measured at VDD/2, FOUT <133MHz 15pF load
Measured at VDD/2V, FOUT <45MHz 30pF load
Measured between 0.8V and 2.0V, 30pF load
Measured between 0.8V and 2.0V, 15pF load
Measured between 0.8V and 2.0V, 30pF load
Measured between 0.8V and 2.0V, 30pF load
Measured between 0.8V and 2.0V, 15pF load
Measured between 0.8V and 2.0V, 30pF load
All outputs equally loaded
40.0
45.0
45.0
40.0
45.0
50
%
Duty Cycle(1) (1H)
60.0
55.0
2.2
Rise Time(1) (1, 2, 3, 4,)
tR
1.50
1.50
2.50
1.50
1.25
Rise Time(1) (1H)
ns
Fall Time(1) (1, 2, 3, 4,)
tF
Fall Time(1) (1H)
tSK(O)
Output to Output Skew within
same Bank (1,2,3,4,6)(1)
200
OUTA to OUTB Skew(1)
(1,1H,4)
OUTA to OUTB Skew(1)
(2,3,6)
ps
400
t0
Measured at VDD/2
Delay, CLKIN Rising Edge
to FB_IN Rising Edge(1)
0
0
±200
600
tSK(D)
tSLEW
Device-to-Device Skew(1)
Output Slew Rate(1)
Measured at VDD/2 on FB_IN pins of devices
Measured between 0.8V & 2.0V on 1H device
using Test Crt #2
1
V/ns
ps
tJIT
Cycle-to-Cycle Jitter(1)
(1,1H,4)
Measured at 66.67 MHz, loaded 30pF load
Measured at 133 MHz, loaded 15pF load
200
100
Cycle-to-Cycle Jitter(1)
(2,3,6)
PLL Lock Time(1)
Measured at 66.67 MHz, loaded 30pF load
400
1.0
tLOCK
Stable power supply, valid clocks
presented on CLKIN and FB_IN pins
ms
Notes:
1. See Switching Waveforms on page 7.
PS8384D
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PI6C2308
Zero Delay Clock Buffer
DCElectricalCharacteristicsforCommercialTemperatureDevices
Parameter
VIL
Description
Input LOW Voltage
Input HIGH Voltage
Input LOW Current
Input HIGH Current
Output LOW Voltage
Output HIGH Voltage
Test Conditions
Min. Max. Units
0.8
V
VIH
IIL
2.0
VIN = 0V
50
A
IIH
VIN = VDD
100
VOL
VOH
IOL = 8mA (1, 2, 3,4, 6); IOL = 12mA (1H)
IOH = 8mA (1, 2, 3,4, 6); IOH = 12mA (1H)
0.4
V
2.4
IDD (PD mode) Power Down Supply Current SEL1 = 0 (-1,-2,-3,-4,-1H); SEL2 = 0 (-6)
25
39
54
A
IDD
IDD
Supply Current
Supply Current
Unloaded outputs, 66.67 MHz, Select inputs at VDD or GND
Unloaded outputs 100 MHz Select Inputs @ VDD or GND
mA
ACElectricalCharacteristicsforCommercialTemperatureDevice
Parameters
Name
Test Conditions
Min. Typ. Max. Units
30pF load
100
FO
tDC
tR
Output Frequency
20pF load, (1H)
10
MHz
%
133
15pF load, (1, 2, 3, 4, 6)
Measured at VDD/2, for high drive output
Measured at VDD/2, for normal drive output
Duty Cycle(1) (1H)
45
40
50
50
55
60
Duty Cycle (1, 2, 3, 4, 6)
Rise Time(1) @30pF
Rise Time(1) @15pF
Rise Time(1) @30pF (1H)
Fall Time(1) @30pF
Fall Time(1) @15pF
Fall Time(1) @30pF (1H)
Output to Output Skew(1) within same
bank (1,1H,2,3,4,6)
OUTA to OUTB Skew(1) (1,1H,4) All outputs equally loaded, VDD/2
OUTA to OUTB Skew(1) (2,3,6)
2.2
1.5
1.5
2.2
1.5
1.25
Measured between 0.8V and 2.0V
ns
ps
tF
tSK(O)
All outputs equally loaded, VDD/2
200
200
400
All outputs equally loaded, VDD/2
t0
Input to Output Delay, CLKIN
Measured at VDD/2
0
0
±200
600
Rising Edge to FB_IN Rising Edge(1)
tSK(D)
tSLEW
Device to Device Skew(1)
Output Slew Rate(1)
Measured at VDD/2 on FB_IN pins of devices
Measured between 0.8V and 2.0V on 1H
device using Test Circuit #2
1
V/ns
ps
tJIT
Cycle-to-Cycle Jitter(1) (1,1H,4)
Measured at 66.67 MHz, loaded 30pF outputs
Measured at 133 MHz, loaded 15pF outputs
Measured at 66.7 MHz, loaded 30pF outputs
200
100
400
Cycle-to-Cycle Jitter(1) (2,3,6)
PLL Lock Time(1)
tLOCK
Stable power supply, valid clocks
presented on CLKIN and FB_IN pins
1.0
ms
Notes:
1. See Switching Waveforms on page 7.
PS8384D
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PI6C2308
Zero Delay Clock Buffer
SwitchingWaveforms
Duty Cycle Timing
t
t
LOW
HIGH
/2
t
HIGH
t
t
DC =
V
/2
DD
V
V
DD
/2
t
+
LOW
DD
HIGH
All Outputs Rise/Fall Time
3.3V
2.0V
0.8V
2.0V
0.8V
OUTPUT
0V
t
t
R
F
Output-Output Skew
Device-Device Skew
V
/2
DD
OUTPUT
OUTPUT
V
/2
DD
t
SK(O)
V
/2
DD
OUTPUT Device 1
OUTPUT Device 2
V
/2
DD
t
SK(D)
Input-Output Propagation Delay
V
/2
DD
INPUT
FB_IN
V
/2
DD
t
0
Test Circuit 1
Test Circuit 2
0.1µF
0.1µF
0.1µF
V
V
V
DD
OUTPUTS
DD
1k
1k
CLK out
CLK out
10pF
OUTPUTS
C
LOAD
V
0.1µF
DD
DD
GND GND
GND GND
Test Circuit for all parameters except t
Test Circuit for t
Output slew rate on –1H device
,
SLEW
SLEW
PS8384D
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PI6C2308
Zero Delay Clock Buffer
16-PinSOIC(W)Package
16
3.78
3.99
.149
.157
0.25
0.50
.0099
.0196
x 45˚
1
0.19
0.25
.0075
.0098
0-8˚
.386
.393
9.80
10.00
0.41
1.27
.016
.050
1.35
1.75
.053
.068
.0155
.0260
.2284
.2440
5.80
6.20
0.393
0.660
SEATING PLANE
REF
0.10
0.25
.0040
.0098
.050
.013
BSC
.020
1.27
0.330
0.508
X.XX
X.XX
DENOTES DIMENSIONS
IN MILLIMETERS
16-PinTSSOP(L)Package
16
.169
.177
4.3
4.5
1
0.09
0.20
.193
.201
.004
.008
4.9
5.1
.047
0.45 .018
0.75 .030
max.
1.20
SEATING
PLANE
.252
BSC
6.4
.002
.006
0.05
0.15
.0256
BSC
.007
.012
X.XX DENOTES CONTROLLING
X.XX DIMENSIONS IN MILLIMETERS
0.65
0.19
0.30
Note:Controllingdimensions inmillimeters.Ref:JEDECMS-012AC
PS8384D
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PI6C2308
Zero Delay Clock Buffer
OrderingInformation (CommercialTemperatureDevice)
Ordering Code
PI6C2308-1W
Package Name
Package Type
Operating Range
PI6C2308-1HW
PI6C2308-2W
PI6C2308-3W
PI6C2308-4W
PI6C2308-6W
PI6C2308-1L
PI6C2308-1HL
W16
16-pin 150-mil SOIC
Commercial
L16
16-pin TSSOP
Package Type
OrderingInformation(Industrial TemperatureDevice)
Ordering Code
PI6C2308-1WI
PI6C2308-1HWI
PI6C2308-2WI
PI6C2308-3WI
PI6C2308-4WI
PI6C2308-6WI
PI6C2308-1LI
Package Name
Operating Range
W16
16-pin 150-mil SOIC
Industrial
L16
16-pin TSSOP
PI6C2308-1HLI
Import Restriction Notice:
Due to an agreement to settle a patent dispute, this device is only available for sale outside of the US and may not be subsequently
re-imported into the US as an individual component or as incorporated into equipment. Any sale is expressly conditioned on the
customer's agreement not to export the device or any product or equipment containing the device to the United States. Pericom
disclaims any liability for indemnity or other obligation or warranty if the devices or any product or equipment containing the
devices are imported in violation of this agreement.
Pericom Semiconductor Corporation
2380 Bering Drive San Jose, CA 95131 1-800-435-2336 Fax (408) 435-1100 http://www.pericom.com
PS8384D
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