PI6C2308A-2L [PERICOM]
3.3V Zero-Delay Buffer; 3.3V零延迟缓冲器
| 型号： | PI6C2308A-2L |
| 厂家： | 
PERICOM SEMICONDUCTOR CORPORATION |
| 描述： | 3.3V Zero-Delay Buffer |
| 文件： | 总10页 (文件大小：388K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
PI6C2308A
3.3V Zero-Delay Buffer
Product Features
FunctionalDescription
• 10 MHz to 140 MHz operating range
• Zero input-output propagation delay, adjustable by
capacitive load on FBK input
• Multipleconfigurations, seeAvailablePI6C2308A
Configurations table
Providingtwobanksof fouroutputs,thePI6C2308Aisa 3.3Vzero-
delay buffer designed to distribute clock signals in applications
includingPC,workstation,datacom,telecom,andhigh-performance
systems. Each bank of four outputs can be controlled by the select
inputs as shown in the Select Input Decoding Table.
The PI6C2308A provides 8 copies of a clock signal that has 150ps
phase error compared to a reference clock. The skew between the
output clock signals for PI6C2308Ais less than 200ps. When there
arenorisingedgesontheREFinput,thePI6C2308Aentersapower
downstate.Inthismode,thePLLisoffandalloutputsareHi-Z.This
resultsinlessthan12µAofcurrentdraw.TheSelectInputDecoding
table shows additional examples when the PLL shuts down. The
PI6C2308A configuration table shows all available devices.
• Input to output delay, less than 150ps
• Multiple low skew outputs
- Output-output skew less than 200ps
- Device-device skew less than 500ps
- Two banks of four outputs, Hi-Z by two select inputs
• Low Jitter, less than 200ps
• 3.3Voperation
The base part, PI6C2308A-1, provides output clocks in sync with
areferenceclock. Withfasterriseandfalltimes,thePI6C2308A-1H
isthehigh-driveversionofthePI6C2308A-1.Dependingonwhich
output drives the feedback pin, PI6C2308A-2 provides 2X and 1X
clocksignalsoneachoutputbank.ThePI6C2308A-3allowstheuser
to obtain 4X and 2X frequencies on the outputs. The PI6C2308A-4
provides 2X clock signals on all outputs. PI6C2308A (-1, -2, -3, -4)
allowsbankBtobeHi-Zwhenalloutputclocksarenotrequired.The
PI6C2308A-6allowsbankBtoswitchfromReferenceclocktohalf
ofthefrequencyofReferenceclockusingthecontrolinputsS1and
S2 if Bank A is connected to feedback FBK. In addition, using the
controlinputsS1andS2,thePI6C2308A-6allowsbankAtoswitch
fromReferenceclockto2XthefrequencyofReferenceclockifBank
B is connected to feedback FBK. For testing purposes, the select
inputs connect the input clock directly to outputs.
• Availableinindustrial&commercialtemperatures
• Packages:
-Space-saving16-pin,150-milSOIC(W)
-16-pinTSSOP(L)
BlockDiagrams
÷2
FBK
CLKA1
PLL
REF
MUX
CLKA2
CLKA3
CLKA4
Extra Divider (-3, -4)
S2
S1
Select Input
Decoding
÷2
CLKB1
CLKB2
CLKB3
CLKB4
Extra Divider (-2,-3)
PI6C2308A (-1, -1H, -2, -3, -4)
PinConfigurationPI6C2308A(-1,-1H,-2,-3,-4,-6)
FBK
CLKA1
PLL
REF
MUX
CLKA2
CLKA3
CLKA4
16
15
14
13
12
11
10
9
REF
CLKA1
CLKA2
1
2
3
4
5
6
7
8
FBK
CLKA4
CLKA3
S2
S1
Select Input
Decoding
16-Pin
W,L
V
V
DD
DD
÷2
MUX
GND
GND
CLKB1
CLKB2
S2
CLKB4
CLKB3
S1
CLKB1
CLKB2
CLKB3
CLKB4
PI6C2308A-6
PS8385B
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PI6C2308A
3.3V Zero Delay Buffer
Select Input Decoding for PI6C2308A (-1, -1H, -2, -3, -4)
S2
0
S1
0
CLKA [1-4]
Hi-Z
CLKB [1-4]
Hi-Z
Output Source
PLL Shutdown
PLL
PLL
Y
N
Y
N
0
1
Driven
Hi-Z
1
0
Driven
Driven
Driven
Reference
PLL
1
1
Driven
SelectInputDecodingforPI6C2308A-6
S2
S1
CLKA [1-4]
CLKB [1-4]
Output Source
PLL Shutdown
0
0
Hi-Z
Hi-Z
PLL
Y
Driven =
Reference/2
0
1
Driven = Reference
Reference
Y
1
1
0
1
Driven = PLL
Driven = PLL
Driven = PLL
PLL
PLL
N
N
Driven = PLL/2
AvailablePI6C2308AConfigurations
Device
Feedback From
Bank A Frequency
Reference
Bank B Frequency
PI6C2308A-1
PI6C2308A-1H
PI6C2308A-2
PI6C2308A-2
PI6C2308A-3
PI6C2308A-3
PI6C2308A-4
PI6C2308A-6
PI6C2308A-6
Bank A or Bank B
Bank A or Bank B
Bank A
Reference
Reference
Reference
Reference
Reference/2
Bank B
2X Reference
2X Reference
4X Reference
2X Reference
Reference
Reference
Bank A
Reference
Bank B
2X Reference
2X Reference
Reference or Reference/2
Reference
Bank A or Bank B
Bank A
Bank B
Reference or 2X Reference
PS8385B
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PI6C2308A
3.3V Zero Delay Buffer
ZeroDelayandSkewControl
REF.InputtoCLKA/CLKBDelayvs.DifferenceinLoadingbetweenFBKpinandCLKA/CLKBpins
800
600
400
200
0
0
5
10
15
20
25
-25
-20
-15
-10
-5
-200
-400
PI6C2308A-1H
-600
-800
PI6C2308A-1,2,3,4,6
-900
-1000
Output Load Difference: FBK Load - CLKA/CLKB Load (pF)
For applications requiring zero input-output delay, all outputs
including the one providing feedback should be equally loaded. If
input-output delay adjustments are required, use the above graph to
calculate loading differences between the feedback output and
remaining outputs.
To close the feedback loop of the PI6C2308A, the FBK pin can be
driven from any of the 8 available output pins. The output driving
the FBK pin will be driving a total load of 7pF plus any additional
load that it drives. The relative loading of this output (with respect
to the remaining outputs) can adjust the input-output delay. This is
shown in the graph above.
Maximum Ratings
Supply Voltage to Ground Potential ...................................................0.5Vto+7.0V
DCInputVoltage(ExceptREF) ..................................................0.5VtoV +0.5V
DD
DCInputVoltageREF................................................................................ 0.5to7V
StorageTemperature........................................................................ 65ºCto+150ºC
MaximumSolderingTemperature(10seconds)................................................ 260ºC
Junction Temperature ....................................................................................... 150ºC
StaticDischargeVoltage
(perMIL-STD-883,Method3015).................................................................. >2000V
OperatingConditions(overtheoperatingrange,TA =0ºCto+70°C,VCC=3.3V±0.3V)
Parameter
Description
Supply Voltage
Min.
3.0
0
Max.
3.6
70
Units
V
V
DD
T
A
Operating Temperature (Ambient)
Load Capacitance
ºC
C
30
l
pF
C
Input Capacitance
7
in
PS8385B
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PI6C2308A
3.3V Zero Delay Buffer
Pin Description
Pin
Signal
Description
(1)
1
2
REF
Input reference frequency, 5VTolerant input, allows spread spectrum clock input
(2)
(2)
CLKA1
CLKA2
Clock output, Bank A
Clock output, Bank A
3.3V supply
3
4
V
DD
5
GND
Ground
(2)
(2)
6
CLKB1
CLKB2
Clock output, Bank B
Clock output, Bank B
Select input, bit 2
Select input, bit 1
Clock output, Bank B
Clock output, Bank B
Ground
7
(3)
8
S2
(3)
9
S1
(2)
(2)
10
11
12
13
14
15
16
CLKB3
CLKB4
GND
V
DD
3.3V, supply
(2)
(2)
CLKA3
CLKA4
FBK
Clock output, Bank A
Clock output, Bank A
PLL feedback input
ElectricalCharacteristicsforCommercialTemperatureDevice
Parameter
Description
Test Conditions
Min.
Max.
Units
(4)
V
IL
Input LOW Voltage
0.8
V
(4)
V
Input HIGH Voltage
Input LOW Current
2.0
IH
I
IL
V
= 0V
50.0
IN
µA
I
IH
Input HIGH Current
Output LOW Voltage
V
IN
= V
DD
200.0
I
OL
= 8mA
= 12mA (-1H)
(5)
(5)
V
OL
0.4
I
OL
V
I
OH
= 8mA
= 12mA (-1H)
V
OH
Output HIGH Voltage
2.4
I
OH
I
(PD mode) Power Down Supply Current
Supply Current
REF = 0 MHz
12.0
39
µA
mA
DD
Unloaded outputs, 66.66 MHz,
Select inputs at V or GND
I
DD
DD
Unloaded outputs, 100 MHz,
Select inputs at V or GND
I
DD
Supply Current
54
DD
PS8385B
08/03/00
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PI6C2308A
3.3V Zero Delay Buffer
SwitchingCharacteristics(5,6) forCommercialTemperatureDevice
Parameters
Name
Output Frequency
Test Conditions
15pF to 30pF load
Min.
Typ. Max. Units
FCLK
10
45
140
55
MHz
Duty Cycle(5) = t2 ÷ t1
Measured at VDD/2
50
50
50
Measured at 1.4V,
FOUT ≤45 MHz
t2
Duty Cycle(5) = t2 ÷ t1 (-1H)
45
40
55
%
Duty Cycle = t2 ÷ t1 (-1,-2,-3,-4,-6)
Rise Time(5) @30pF
Measured at 1.4V
60
2.2
1.5
1.5
2.2
1.5
1.25
t3
t3
t3
t4
t4
t4
Rise Time(5) @15pF
Rise Time(5) @30pF (-1H)
Fall Time(5) @30pF
Measured between
0.8V and 2.0V
ns
Fall Time(5) @15pF
Fall Time(5) @30pF (-1H)
Output to Output Skew(5)
same bank
t5
t5
t6
t7
All outputs equally loaded, VDD/2
All outputs equally loaded, VDD/2
Measured at VDD/2
200
400
Output to Output Skew(5)
different bank (2,3,6)
ps
Delay, REF Rising Edge to
FBK Rising Edge(5)
0
0
±150
500
Measured at VDD/2 on the
FBK pins of devices
Device to Device Skew(5)
Measured between 0.8V and 2.0V
on -1H device using
t8
Output Slew Rate(5)
1
V/ns
Test Circuit #2
Measured at 66.67 MHz,
loaded outputs
tJ
Cycle to Cycle Jitter(5)
PLL Lock Time(5)
200
1.0
ps
Stable power supply, valid clocks
presented on REF and FBK pins
tLOCK
ms
Notes:
1. Weak pull-down.
2. Weak pull-down on all outputs.
3. Weak pull-ups on these inputs.
4. REF and FBK inputs have a threshhold voltage of V /2.
DD
5. Parameter is guaranteed by design and characterization. Not 100% tested in production.
6. For definition of t , see Switching Waveforms on page 6
1-8
PS8385B
08/03/00
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PI6C2308A
3.3V Zero Delay Buffer
OperatingConditionsforIndustrialTemperatureDevices
Parameter
Description
Min.
3.0
Max.
3.6
85
Units
V
V
DD
Supply Voltage
T
A
Operating Temperature (Ambient Temperature)
Load Capacitance, below 100 MHz
Load Capacitance, from 100 MHz to 133 MHz
Input Capacitance
40
ºC
30
C
L
15
pF
C
7
IN
ElectricalCharacteristicsforIndustrialTemperatureDevices
Parameter
Description
Input LOW Voltage
Input HIGH Voltage
Input LOW Current
Input HIGH Current
Test Conditions
Min.
Max.
Units
V
IL
0.8
V
V
IH
2.0
I
IL
V
= 0V
50.0
IN
µA
I
IH
V
IN
= V
DD
100.0
I
= 8 mA (1,2,3,4)
= 12 mA (1H,5)
OL
(4)
V
OL
Output LOW Voltage
0.4
I
OL
V
I
= 8 mA (1,2,3,4)
= 12 mA (1H,5)
OH
(4)
V
OH
Output HIGH Voltage
2.4
I
OH
I
DD
(PD mode)
Power Down Supply Current
REF = 0 MHz
25.0
45.0
µA
Unloaded outputs, 100 MHz,
Select inputs at V or GND
DD
70.0 (1H)
Unloaded outputs, 66 MHz,
REF, except 1H
I
DD
Supply Current
mA
35.0
20.0
Unloaded outputs, 33 MHz,
REF, except 1H
PS8385B
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PI6C2308A
3.3V Zero Delay Buffer
SwitchingCharacteristicsforIndustrialTemperatureDevices(5)
Parameter
Name
Test Conditions
Min. Typ. Max. Units
30pF load, All devices
100
t
1
Output Frequency
20pF load, 1H, 5, devices
10
140 MHz
140
15pF load, 1,2,3,4 devices
t
2
Measured at 1.4V, F
Measured at 1.4V, F
Measured at 1.4V, F
Measured at 1.4V, F
Measured at 1.4V, F
Measured at 1.4V, F
<66.66MHz 30-pF load
<100 MHz 15-pF load
<133 MHz 15-pF load
< 45MHz
OUT
OUT
OUT
OUT
OUT
OUT
(4)
40.0
35.0
40.0
45.0
60.0
Duty Cycle = t ÷ t
2
1
(1,2,3,4)
50.0
%
(4)
Duty Cycle = t ÷ t (1H,5)
55.0
2
1
<66.66 MHz 15-pF load
<45MHz
(4)
Duty Cycle = t ÷ t (1H,5)
2
1
(4)
Rise Time (1,2,3,4)
Measured between 0.8V and 2.0V, 30-pF load
Measured between 0.8V and 2.0V, 15-pF load
Measured between 0.8V and 2.0V, 30-pF load
Measured between 0.8V and 2.0V, 30-pF load
Measured between 0.8V and 2.0V, 15-pF load
Measured between 0.8V and 2.0V, 30-pF load
2.2
(4)
Rise Time (1,2,3,4)
1.50
t
3
(4)
Rise Time (1H,5)
1.50
ns
2.50
(4)
Fall Time (1,2,3,4)
(4)
t
4
Fall Time (1,2,3,4)
1.50
1.25
(4)
Fall Time (1H,5)
Output to Output Skew on same
(4)
Bank (1,2,3,4)
Output to Output Skew (1H,5)
200
t
5
All outputs equally loaded
Output Bank A to Output Bank B
Skew (1, 4, 5)
ps
Output Bank A to Output Bank B
Skew (2, 3)
400
Delay, REF Rising Edge to FBK
Rising Edge
t
Measured at V /2
0
±150
500
6
DD
(4)
(4)
t
7
Device to Device Skew
Measured at V /2 MHz, on the FBK pins of devices
DD
Measured twx 0.8V & 2.0V on
1H,5 device using Test Circuit #2.
(4)
t
8
Output Slew Rate
1
V/ns
(4)
Cycle to Cycle Jitter
(1, 1H,5, 4)
,
Measured at 66.67 MHz, loaded outputs, 30pF Load
200
t
J
ps
(4)
Cycle to Cycle Jitter , (2,3)
Measured at 66.67 MHz, loaded outputs, 15pF Load
Measured at 66.67 MHz, loaded outputs
100
(4)
Cycle to Cycle Jitter , (2,3)
400
(4)
t
PLL Lock Time
Stable power supply, valid clocks presented on REF and FBK pins
1.0
ms
LOCK
Notes:
1. Weak pull-down.
2. Weak pull-down on all outputs.
3. Weak pull-ups on these inputs.
4. REF and FBK inputs have a threshhold voltage of V /2.
DD
5. Parameter is guaranteed by design and characterization. Not 100% tested in production.
6. For definition of t , see Switching Waveforms on page 6
1-8
PS8385B
08/03/00
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PI6C2308A
3.3V Zero Delay Buffer
Switching Waveforms
Duty Cycle Timing
t
1
t
2
1.4V
1.4V
1.4V
All Outputs Rise/Fall Time
3.3V
2.0V
0.8V
2.0V
0.8V
OUTPUT
0V
t
t
4
3
Output-Output Skew
1.4V
OUTPUT
1.4V
OUTPUT
t
5
Input-Output Propagation Delay
V
/2
DD
INPUT
V
/2
DD
FBK
t
6
Device-Device Skew
V
/2
DD
FBK Device 1
V
/2
DD
FBK Device 2
t
7
TestCircuit#1
Test Circuit #2
0.1 F
0.1 F
0.1 F
0.1 F
VDD
VDD
1k
CLK out
CLK out
CLOAD
OUTPUTS
OUTPUTS
10pF
1k
VDD
VDD
GND
GND
GND
GND
Test Circuit for all parameters except t8
Test Circuit for t8 Output slew rate on -1H device
,
PS8385B
08/03/00
8
PI6C2308A
3.3V Zero Delay Buffer
Package Diagrams
16-PinSOIC(W)
16
3.78
3.99
.149
.157
1
0.25
0.50
.0099
.0196
x 45˚
.386
.393
9.80
10.00
0.19
0.25
.0075
.0098
0-8˚
1.35
1.75
.053
.068
.0155
.0260
0.41
1.27
.016
.050
0.393
0.660
SEATING PLANE
.2284
REF
.2440
5.80
6.20
0.10
0.25
.0040
.0098
.050
BSC
.013
.020
1.27
0.330
0.508
X.XX
X.XX
DENOTES DIMENSIONS
IN MILLIMETERS
16-PinTSSOP(L)
16
.169
.177
4.3
4.5
1
.193
.201
0.09
0.20
.004
.008
4.9
5.1
.047
max.
0.45 .018
0.75 .030
1.20
SEATING
PLANE
.252
BSC
6.4
.002
.006
0.05
0.15
.0256
BSC
.007
.012
0.65
0.19
0.30
X.XX DENOTES CONTROLLING
X.XX DIMENSIONS IN MILLIMETERS
Note: Controlling dimensions in millimeters. Ref: JEDEC MS - 012 AC
PS8385B
08/03/00
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PI6C2308A
3.3V Zero Delay Buffer
OrderingInformation(CommercialTemperatureDevice)
Ordering Code
PI6C2308A-1W
Package Name
Package Type
Operating Range
PI6C2308A-1HW
PI6C2308A-2W
PI6C2308A-3W
PI6C2308A-4W
PI6C2308A-6W
PI6C2308A-1L
PI6C2308A-1HL
PI6C2308A-2L
PI6C2308A3L
PI6C2308A4L
PI6C2308A-6L
W16
16-pin 150-mil SOIC
Commercial
L16
16-pin TSSOP
OrderingInformation(IndustrialTemperatureDevice)
Ordering Code
PI6C2308A-1WI
Package Name
Package Type
Operating Range
PI6C2308A-1HWI
PI6C2308A-2WI
PI6C2308A-3WI
PI6C2308A-4WI
PI6C2308A-6WI
PI6C2308A-1LI
PI6C2308A-1HLI
PI6C2308A-2LI
PI6C2308A-3LI
PI6C2308A-4LI
PI6C2308A-6LII
W16
16-pin 150-mil SOIC
Industrial
L16
16-pin TSSOP
Pericom Semiconductor Corporation
2380 Bering Drive • San Jose, CA 95131 • 1-800-435-2336 • Fax (408) 435-1100 • http://www.pericom.com
PS8385B
08/03/00
10
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